~hc/RK356X_SDK_RELEASE.git

..	..	@@ -74,32 +74,65 @@
74	74	#define MAX_HBA_QUEUE_DEPTH 30000
75	75	#define MAX_CHAIN_DEPTH 100000
76	76	static int max_queue_depth = -1;
77		-module_param(max_queue_depth, int, 0);
	77	+module_param(max_queue_depth, int, 0444);
78	78	MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
79	79
80	80	static int max_sgl_entries = -1;
81		-module_param(max_sgl_entries, int, 0);
	81	+module_param(max_sgl_entries, int, 0444);
82	82	MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
83	83
84	84	static int msix_disable = -1;
85		-module_param(msix_disable, int, 0);
	85	+module_param(msix_disable, int, 0444);
86	86	MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
87	87
88	88	static int smp_affinity_enable = 1;
89		-module_param(smp_affinity_enable, int, S_IRUGO);
	89	+module_param(smp_affinity_enable, int, 0444);
90	90	MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
91	91
92	92	static int max_msix_vectors = -1;
93		-module_param(max_msix_vectors, int, 0);
	93	+module_param(max_msix_vectors, int, 0444);
94	94	MODULE_PARM_DESC(max_msix_vectors,
95	95	" max msix vectors");
	96	+
	97	+static int irqpoll_weight = -1;
	98	+module_param(irqpoll_weight, int, 0444);
	99	+MODULE_PARM_DESC(irqpoll_weight,
	100	+ "irq poll weight (default= one fourth of HBA queue depth)");
96	101
97	102	static int mpt3sas_fwfault_debug;
98	103	MODULE_PARM_DESC(mpt3sas_fwfault_debug,
99	104	" enable detection of firmware fault and halt firmware - (default=0)");
100	105
	106	+static int perf_mode = -1;
	107	+module_param(perf_mode, int, 0444);
	108	+MODULE_PARM_DESC(perf_mode,
	109	+ "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
	110	+ "0 - balanced: high iops mode is enabled &\n\t\t"
	111	+ "interrupt coalescing is enabled only on high iops queues,\n\t\t"
	112	+ "1 - iops: high iops mode is disabled &\n\t\t"
	113	+ "interrupt coalescing is enabled on all queues,\n\t\t"
	114	+ "2 - latency: high iops mode is disabled &\n\t\t"
	115	+ "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
	116	+ "\t\tdefault - default perf_mode is 'balanced'"
	117	+ );
	118	+
	119	+enum mpt3sas_perf_mode {
	120	+ MPT_PERF_MODE_DEFAULT = -1,
	121	+ MPT_PERF_MODE_BALANCED = 0,
	122	+ MPT_PERF_MODE_IOPS = 1,
	123	+ MPT_PERF_MODE_LATENCY = 2,
	124	+};
	125	+
	126	+static int
	127	+_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
	128	+ u32 ioc_state, int timeout);
101	129	static int
102	130	_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
	131	+static void
	132	+_base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
	133	+
	134	+static u32
	135	+_base_readl_ext_retry(const volatile void __iomem *addr);
103	136
104	137	/**
105	138	* mpt3sas_base_check_cmd_timeout - Function
..	..	@@ -122,8 +155,8 @@
122	155	if (!(status & MPT3_CMD_RESET))
123	156	issue_reset = 1;
124	157
125		- pr_err(MPT3SAS_FMT "Command %s\n", ioc->name,
126		- ((issue_reset == 0) ? "terminated due to Host Reset" : "Timeout"));
	158	+ ioc_err(ioc, "Command %s\n",
	159	+ issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
127	160	_debug_dump_mf(mpi_request, sz);
128	161
129	162	return issue_reset;
..	..	@@ -155,6 +188,46 @@
155	188	}
156	189	module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
157	190	param_get_int, &mpt3sas_fwfault_debug, 0644);
	191	+
	192	+/**
	193	+ * _base_readl_aero - retry readl for max three times.
	194	+ * @addr: MPT Fusion system interface register address
	195	+ *
	196	+ * Retry the readl() for max three times if it gets zero value
	197	+ * while reading the system interface register.
	198	+ */
	199	+static inline u32
	200	+_base_readl_aero(const volatile void __iomem *addr)
	201	+{
	202	+ u32 i = 0, ret_val;
	203	+
	204	+ do {
	205	+ ret_val = readl(addr);
	206	+ i++;
	207	+ } while (ret_val == 0 && i < 3);
	208	+
	209	+ return ret_val;
	210	+}
	211	+
	212	+static u32
	213	+_base_readl_ext_retry(const volatile void __iomem *addr)
	214	+{
	215	+ u32 i, ret_val;
	216	+
	217	+ for (i = 0 ; i < 30 ; i++) {
	218	+ ret_val = readl(addr);
	219	+ if (ret_val == 0)
	220	+ continue;
	221	+ }
	222	+
	223	+ return ret_val;
	224	+}
	225	+
	226	+static inline u32
	227	+_base_readl(const volatile void __iomem *addr)
	228	+{
	229	+ return readl(addr);
	230	+}
158	231
159	232	/**
160	233	* _base_clone_reply_to_sys_mem - copies reply to reply free iomem
..	..	@@ -336,9 +409,7 @@
336	409	return ct->chain_buffer;
337	410	}
338	411	}
339		- pr_info(MPT3SAS_FMT
340		- "Provided chain_buffer_dma address is not in the lookup list\n",
341		- ioc->name);
	412	+ ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
342	413	return NULL;
343	414	}
344	415
..	..	@@ -357,7 +428,7 @@
357	428	{
358	429	Mpi2SGESimple32_t sgel, sgel_next;
359	430	u32 sgl_flags, sge_chain_count = 0;
360		- bool is_write = 0;
	431	+ bool is_write = false;
361	432	u16 i = 0;
362	433	void __iomem *buffer_iomem;
363	434	phys_addr_t buffer_iomem_phys;
..	..	@@ -394,7 +465,7 @@
394	465	/* Get scsi_cmd using smid */
395	466	scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
396	467	if (scmd == NULL) {
397		- pr_err(MPT3SAS_FMT "scmd is NULL\n", ioc->name);
	468	+ ioc_err(ioc, "scmd is NULL\n");
398	469	return;
399	470	}
400	471
..	..	@@ -426,7 +497,7 @@
426	497
427	498	if (le32_to_cpu(sgel->FlagsLength) &
428	499	(MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
429		- is_write = 1;
	500	+ is_write = true;
430	501
431	502	for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
432	503
..	..	@@ -532,11 +603,11 @@
532	603	struct MPT3SAS_ADAPTER ioc = (struct MPT3SAS_ADAPTER )arg;
533	604	struct pci_dev *pdev;
534	605
535		- if ((ioc == NULL))
	606	+ if (!ioc)
536	607	return -1;
537	608
538	609	pdev = ioc->pdev;
539		- if ((pdev == NULL))
	610	+ if (!pdev)
540	611	return -1;
541	612	pci_stop_and_remove_bus_device_locked(pdev);
542	613	return 0;
..	..	@@ -560,14 +631,14 @@
560	631
561	632
562	633	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
563		- if (ioc->shost_recovery \|\| ioc->pci_error_recovery)
	634	+ if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) \|\|
	635	+ ioc->pci_error_recovery)
564	636	goto rearm_timer;
565	637	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
566	638
567	639	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
568	640	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
569		- pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
570		- ioc->name);
	641	+ ioc_err(ioc, "SAS host is non-operational !!!!\n");
571	642
572	643	/* It may be possible that EEH recovery can resolve some of
573	644	* pci bus failure issues rather removing the dead ioc function
..	..	@@ -600,30 +671,72 @@
600	671	p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
601	672	"%s_dead_ioc_%d", ioc->driver_name, ioc->id);
602	673	if (IS_ERR(p))
603		- pr_err(MPT3SAS_FMT
604		- "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
605		- ioc->name, __func__);
	674	+ ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
	675	+ __func__);
606	676	else
607		- pr_err(MPT3SAS_FMT
608		- "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
609		- ioc->name, __func__);
	677	+ ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
	678	+ __func__);
610	679	return; /* don't rearm timer */
611	680	}
612	681
613		- ioc->non_operational_loop = 0;
	682	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
	683	+ u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
	684	+ ioc->manu_pg11.CoreDumpTOSec :
	685	+ MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
614	686
	687	+ timeout /= (FAULT_POLLING_INTERVAL/1000);
	688	+
	689	+ if (ioc->ioc_coredump_loop == 0) {
	690	+ mpt3sas_print_coredump_info(ioc,
	691	+ doorbell & MPI2_DOORBELL_DATA_MASK);
	692	+ /* do not accept any IOs and disable the interrupts */
	693	+ spin_lock_irqsave(
	694	+ &ioc->ioc_reset_in_progress_lock, flags);
	695	+ ioc->shost_recovery = 1;
	696	+ spin_unlock_irqrestore(
	697	+ &ioc->ioc_reset_in_progress_lock, flags);
	698	+ mpt3sas_base_mask_interrupts(ioc);
	699	+ _base_clear_outstanding_commands(ioc);
	700	+ }
	701	+
	702	+ ioc_info(ioc, "%s: CoreDump loop %d.",
	703	+ __func__, ioc->ioc_coredump_loop);
	704	+
	705	+ /* Wait until CoreDump completes or times out */
	706	+ if (ioc->ioc_coredump_loop++ < timeout) {
	707	+ spin_lock_irqsave(
	708	+ &ioc->ioc_reset_in_progress_lock, flags);
	709	+ goto rearm_timer;
	710	+ }
	711	+ }
	712	+
	713	+ if (ioc->ioc_coredump_loop) {
	714	+ if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
	715	+ ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
	716	+ __func__, ioc->ioc_coredump_loop);
	717	+ else
	718	+ ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
	719	+ __func__, ioc->ioc_coredump_loop);
	720	+ ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
	721	+ }
	722	+ ioc->non_operational_loop = 0;
615	723	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
616	724	rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
617		- pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
618		- __func__, (rc == 0) ? "success" : "failed");
	725	+ ioc_warn(ioc, "%s: hard reset: %s\n",
	726	+ __func__, rc == 0 ? "success" : "failed");
619	727	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
620		- if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
621		- mpt3sas_base_fault_info(ioc, doorbell &
	728	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	729	+ mpt3sas_print_fault_code(ioc, doorbell &
	730	+ MPI2_DOORBELL_DATA_MASK);
	731	+ } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
	732	+ MPI2_IOC_STATE_COREDUMP)
	733	+ mpt3sas_print_coredump_info(ioc, doorbell &
622	734	MPI2_DOORBELL_DATA_MASK);
623	735	if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
624	736	MPI2_IOC_STATE_OPERATIONAL)
625	737	return; /* don't rearm timer */
626	738	}
	739	+ ioc->ioc_coredump_loop = 0;
627	740
628	741	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
629	742	rearm_timer:
..	..	@@ -657,8 +770,7 @@
657	770	ioc->fault_reset_work_q =
658	771	create_singlethread_workqueue(ioc->fault_reset_work_q_name);
659	772	if (!ioc->fault_reset_work_q) {
660		- pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
661		- ioc->name, __func__, __LINE__);
	773	+ ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
662	774	return;
663	775	}
664	776	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
..	..	@@ -700,8 +812,51 @@
700	812	void
701	813	mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
702	814	{
703		- pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
704		- ioc->name, fault_code);
	815	+ ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
	816	+}
	817	+
	818	+/**
	819	+ * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
	820	+ * @ioc: per adapter object
	821	+ * @fault_code: fault code
	822	+ *
	823	+ * Return nothing.
	824	+ */
	825	+void
	826	+mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
	827	+{
	828	+ ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
	829	+}
	830	+
	831	+/**
	832	+ * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
	833	+ * completes or times out
	834	+ * @ioc: per adapter object
	835	+ * @caller: caller function name
	836	+ *
	837	+ * Returns 0 for success, non-zero for failure.
	838	+ */
	839	+int
	840	+mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
	841	+ const char *caller)
	842	+{
	843	+ u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
	844	+ ioc->manu_pg11.CoreDumpTOSec :
	845	+ MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
	846	+
	847	+ int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
	848	+ timeout);
	849	+
	850	+ if (ioc_state)
	851	+ ioc_err(ioc,
	852	+ "%s: CoreDump timed out. (ioc_state=0x%x)\n",
	853	+ caller, ioc_state);
	854	+ else
	855	+ ioc_info(ioc,
	856	+ "%s: CoreDump completed. (ioc_state=0x%x)\n",
	857	+ caller, ioc_state);
	858	+
	859	+ return ioc_state;
705	860	}
706	861
707	862	/**
..	..	@@ -723,13 +878,17 @@
723	878
724	879	dump_stack();
725	880
726		- doorbell = readl(&ioc->chip->Doorbell);
727		- if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
728		- mpt3sas_base_fault_info(ioc , doorbell);
729		- else {
	881	+ doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell);
	882	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	883	+ mpt3sas_print_fault_code(ioc, doorbell &
	884	+ MPI2_DOORBELL_DATA_MASK);
	885	+ } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
	886	+ MPI2_IOC_STATE_COREDUMP) {
	887	+ mpt3sas_print_coredump_info(ioc, doorbell &
	888	+ MPI2_DOORBELL_DATA_MASK);
	889	+ } else {
730	890	writel(0xC0FFEE00, &ioc->chip->Doorbell);
731		- pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
732		- ioc->name);
	891	+ ioc_err(ioc, "Firmware is halted due to command timeout\n");
733	892	}
734	893
735	894	if (ioc->fwfault_debug == 2)
..	..	@@ -956,8 +1115,8 @@
956	1115	break;
957	1116	}
958	1117
959		- pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
960		- ioc->name, desc, ioc_status, request_hdr, func_str);
	1118	+ ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
	1119	+ desc, ioc_status, request_hdr, func_str);
961	1120
962	1121	_debug_dump_mf(request_hdr, frame_sz/4);
963	1122	}
..	..	@@ -1003,9 +1162,9 @@
1003	1162	{
1004	1163	Mpi2EventDataSasDiscovery_t *event_data =
1005	1164	(Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1006		- pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
1007		- (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
1008		- "start" : "stop");
	1165	+ ioc_info(ioc, "Discovery: (%s)",
	1166	+ event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
	1167	+ "start" : "stop");
1009	1168	if (event_data->DiscoveryStatus)
1010	1169	pr_cont(" discovery_status(0x%08x)",
1011	1170	le32_to_cpu(event_data->DiscoveryStatus));
..	..	@@ -1059,14 +1218,13 @@
1059	1218	{
1060	1219	Mpi26EventDataPCIeEnumeration_t *event_data =
1061	1220	(Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1062		- pr_info(MPT3SAS_FMT "PCIE Enumeration: (%s)", ioc->name,
1063		- (event_data->ReasonCode ==
1064		- MPI26_EVENT_PCIE_ENUM_RC_STARTED) ?
1065		- "start" : "stop");
	1221	+ ioc_info(ioc, "PCIE Enumeration: (%s)",
	1222	+ event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
	1223	+ "start" : "stop");
1066	1224	if (event_data->EnumerationStatus)
1067		- pr_info("enumeration_status(0x%08x)",
1068		- le32_to_cpu(event_data->EnumerationStatus));
1069		- pr_info("\n");
	1225	+ pr_cont("enumeration_status(0x%08x)",
	1226	+ le32_to_cpu(event_data->EnumerationStatus));
	1227	+ pr_cont("\n");
1070	1228	return;
1071	1229	}
1072	1230	case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
..	..	@@ -1077,7 +1235,7 @@
1077	1235	if (!desc)
1078	1236	return;
1079	1237
1080		- pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
	1238	+ ioc_info(ioc, "%s\n", desc);
1081	1239	}
1082	1240
1083	1241	/**
..	..	@@ -1128,11 +1286,9 @@
1128	1286	break;
1129	1287	}
1130	1288
1131		- pr_warn(MPT3SAS_FMT
1132		- "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1133		- ioc->name, log_info,
1134		- originator_str, sas_loginfo.dw.code,
1135		- sas_loginfo.dw.subcode);
	1289	+ ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
	1290	+ log_info,
	1291	+ originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1136	1292	}
1137	1293
1138	1294	/**
..	..	@@ -1152,8 +1308,8 @@
1152	1308
1153	1309	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1154	1310	if (unlikely(!mpi_reply)) {
1155		- pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
1156		- ioc->name, __FILE__, __LINE__, __func__);
	1311	+ ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
	1312	+ __FILE__, __LINE__, __func__);
1157	1313	return;
1158	1314	}
1159	1315	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
..	..	@@ -1249,9 +1405,9 @@
1249	1405	delayed_event_ack->EventContext = mpi_reply->EventContext;
1250	1406	list_add_tail(&delayed_event_ack->list,
1251	1407	&ioc->delayed_event_ack_list);
1252		- dewtprintk(ioc, pr_info(MPT3SAS_FMT
1253		- "DELAYED: EVENT ACK: event (0x%04x)\n",
1254		- ioc->name, le16_to_cpu(mpi_reply->Event)));
	1408	+ dewtprintk(ioc,
	1409	+ ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
	1410	+ le16_to_cpu(mpi_reply->Event)));
1255	1411	goto out;
1256	1412	}
1257	1413
..	..	@@ -1262,7 +1418,7 @@
1262	1418	ack_request->EventContext = mpi_reply->EventContext;
1263	1419	ack_request->VF_ID = 0; /* TODO */
1264	1420	ack_request->VP_ID = 0;
1265		- mpt3sas_base_put_smid_default(ioc, smid);
	1421	+ ioc->put_smid_default(ioc, smid);
1266	1422
1267	1423	out:
1268	1424
..	..	@@ -1325,35 +1481,35 @@
1325	1481	}
1326	1482
1327	1483	/**
1328		- * _base_mask_interrupts - disable interrupts
	1484	+ * mpt3sas_base_mask_interrupts - disable interrupts
1329	1485	* @ioc: per adapter object
1330	1486	*
1331	1487	* Disabling ResetIRQ, Reply and Doorbell Interrupts
1332	1488	*/
1333		-static void
1334		-_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
	1489	+void
	1490	+mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1335	1491	{
1336	1492	u32 him_register;
1337	1493
1338	1494	ioc->mask_interrupts = 1;
1339		- him_register = readl(&ioc->chip->HostInterruptMask);
	1495	+ him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1340	1496	him_register \|= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1341	1497	writel(him_register, &ioc->chip->HostInterruptMask);
1342		- readl(&ioc->chip->HostInterruptMask);
	1498	+ ioc->base_readl(&ioc->chip->HostInterruptMask);
1343	1499	}
1344	1500
1345	1501	/**
1346		- * _base_unmask_interrupts - enable interrupts
	1502	+ * mpt3sas_base_unmask_interrupts - enable interrupts
1347	1503	* @ioc: per adapter object
1348	1504	*
1349	1505	* Enabling only Reply Interrupts
1350	1506	*/
1351		-static void
1352		-_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
	1507	+void
	1508	+mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1353	1509	{
1354	1510	u32 him_register;
1355	1511
1356		- him_register = readl(&ioc->chip->HostInterruptMask);
	1512	+ him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1357	1513	him_register &= ~MPI2_HIM_RIM;
1358	1514	writel(him_register, &ioc->chip->HostInterruptMask);
1359	1515	ioc->mask_interrupts = 0;
..	..	@@ -1367,20 +1523,30 @@
1367	1523	} u;
1368	1524	};
1369	1525
1370		-/**
1371		- * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1372		- * @irq: irq number (not used)
1373		- * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1374		- *
1375		- * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1376		- */
1377		-static irqreturn_t
1378		-_base_interrupt(int irq, void *bus_id)
	1526	+static u32 base_mod64(u64 dividend, u32 divisor)
1379	1527	{
1380		- struct adapter_reply_queue *reply_q = bus_id;
	1528	+ u32 remainder;
	1529	+
	1530	+ if (!divisor)
	1531	+ pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
	1532	+ remainder = do_div(dividend, divisor);
	1533	+ return remainder;
	1534	+}
	1535	+
	1536	+/**
	1537	+ * _base_process_reply_queue - Process reply descriptors from reply
	1538	+ * descriptor post queue.
	1539	+ * @reply_q: per IRQ's reply queue object.
	1540	+ *
	1541	+ * Return: number of reply descriptors processed from reply
	1542	+ * descriptor queue.
	1543	+ */
	1544	+static int
	1545	+_base_process_reply_queue(struct adapter_reply_queue *reply_q)
	1546	+{
1381	1547	union reply_descriptor rd;
1382		- u32 completed_cmds;
1383		- u8 request_desript_type;
	1548	+ u64 completed_cmds;
	1549	+ u8 request_descript_type;
1384	1550	u16 smid;
1385	1551	u8 cb_idx;
1386	1552	u32 reply;
..	..	@@ -1389,21 +1555,18 @@
1389	1555	Mpi2ReplyDescriptorsUnion_t *rpf;
1390	1556	u8 rc;
1391	1557
1392		- if (ioc->mask_interrupts)
1393		- return IRQ_NONE;
1394		-
	1558	+ completed_cmds = 0;
1395	1559	if (!atomic_add_unless(&reply_q->busy, 1, 1))
1396		- return IRQ_NONE;
	1560	+ return completed_cmds;
1397	1561
1398	1562	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1399		- request_desript_type = rpf->Default.ReplyFlags
	1563	+ request_descript_type = rpf->Default.ReplyFlags
1400	1564	& MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1401		- if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
	1565	+ if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1402	1566	atomic_dec(&reply_q->busy);
1403		- return IRQ_NONE;
	1567	+ return completed_cmds;
1404	1568	}
1405	1569
1406		- completed_cmds = 0;
1407	1570	cb_idx = 0xFF;
1408	1571	do {
1409	1572	rd.word = le64_to_cpu(rpf->Words);
..	..	@@ -1411,11 +1574,11 @@
1411	1574	goto out;
1412	1575	reply = 0;
1413	1576	smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1414		- if (request_desript_type ==
	1577	+ if (request_descript_type ==
1415	1578	MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS \|\|
1416		- request_desript_type ==
	1579	+ request_descript_type ==
1417	1580	MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS \|\|
1418		- request_desript_type ==
	1581	+ request_descript_type ==
1419	1582	MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1420	1583	cb_idx = _base_get_cb_idx(ioc, smid);
1421	1584	if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
..	..	@@ -1425,7 +1588,7 @@
1425	1588	if (rc)
1426	1589	mpt3sas_base_free_smid(ioc, smid);
1427	1590	}
1428		- } else if (request_desript_type ==
	1591	+ } else if (request_descript_type ==
1429	1592	MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1430	1593	reply = le32_to_cpu(
1431	1594	rpf->AddressReply.ReplyFrameAddress);
..	..	@@ -1471,7 +1634,7 @@
1471	1634	(reply_q->reply_post_host_index ==
1472	1635	(ioc->reply_post_queue_depth - 1)) ? 0 :
1473	1636	reply_q->reply_post_host_index + 1;
1474		- request_desript_type =
	1637	+ request_descript_type =
1475	1638	reply_q->reply_post_free[reply_q->reply_post_host_index].
1476	1639	Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1477	1640	completed_cmds++;
..	..	@@ -1480,7 +1643,7 @@
1480	1643	* So that FW can find enough entries to post the Reply
1481	1644	* Descriptors in the reply descriptor post queue.
1482	1645	*/
1483		- if (completed_cmds > ioc->hba_queue_depth/3) {
	1646	+ if (completed_cmds >= ioc->thresh_hold) {
1484	1647	if (ioc->combined_reply_queue) {
1485	1648	writel(reply_q->reply_post_host_index \|
1486	1649	((msix_index & 7) <<
..	..	@@ -1492,9 +1655,14 @@
1492	1655	MPI2_RPHI_MSIX_INDEX_SHIFT),
1493	1656	&ioc->chip->ReplyPostHostIndex);
1494	1657	}
1495		- completed_cmds = 1;
	1658	+ if (!reply_q->irq_poll_scheduled) {
	1659	+ reply_q->irq_poll_scheduled = true;
	1660	+ irq_poll_sched(&reply_q->irqpoll);
	1661	+ }
	1662	+ atomic_dec(&reply_q->busy);
	1663	+ return completed_cmds;
1496	1664	}
1497		- if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
	1665	+ if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1498	1666	goto out;
1499	1667	if (!reply_q->reply_post_host_index)
1500	1668	rpf = reply_q->reply_post_free;
..	..	@@ -1506,14 +1674,14 @@
1506	1674
1507	1675	if (!completed_cmds) {
1508	1676	atomic_dec(&reply_q->busy);
1509		- return IRQ_NONE;
	1677	+ return completed_cmds;
1510	1678	}
1511	1679
1512	1680	if (ioc->is_warpdrive) {
1513	1681	writel(reply_q->reply_post_host_index,
1514	1682	ioc->reply_post_host_index[msix_index]);
1515	1683	atomic_dec(&reply_q->busy);
1516		- return IRQ_HANDLED;
	1684	+ return completed_cmds;
1517	1685	}
1518	1686
1519	1687	/* Update Reply Post Host Index.
..	..	@@ -1540,7 +1708,89 @@
1540	1708	MPI2_RPHI_MSIX_INDEX_SHIFT),
1541	1709	&ioc->chip->ReplyPostHostIndex);
1542	1710	atomic_dec(&reply_q->busy);
1543		- return IRQ_HANDLED;
	1711	+ return completed_cmds;
	1712	+}
	1713	+
	1714	+/**
	1715	+ * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
	1716	+ * @irq: irq number (not used)
	1717	+ * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
	1718	+ *
	1719	+ * Return: IRQ_HANDLED if processed, else IRQ_NONE.
	1720	+ */
	1721	+static irqreturn_t
	1722	+_base_interrupt(int irq, void *bus_id)
	1723	+{
	1724	+ struct adapter_reply_queue *reply_q = bus_id;
	1725	+ struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
	1726	+
	1727	+ if (ioc->mask_interrupts)
	1728	+ return IRQ_NONE;
	1729	+ if (reply_q->irq_poll_scheduled)
	1730	+ return IRQ_HANDLED;
	1731	+ return ((_base_process_reply_queue(reply_q) > 0) ?
	1732	+ IRQ_HANDLED : IRQ_NONE);
	1733	+}
	1734	+
	1735	+/**
	1736	+ * _base_irqpoll - IRQ poll callback handler
	1737	+ * @irqpoll: irq_poll object
	1738	+ * @budget: irq poll weight
	1739	+ *
	1740	+ * returns number of reply descriptors processed
	1741	+ */
	1742	+static int
	1743	+_base_irqpoll(struct irq_poll *irqpoll, int budget)
	1744	+{
	1745	+ struct adapter_reply_queue *reply_q;
	1746	+ int num_entries = 0;
	1747	+
	1748	+ reply_q = container_of(irqpoll, struct adapter_reply_queue,
	1749	+ irqpoll);
	1750	+ if (reply_q->irq_line_enable) {
	1751	+ disable_irq_nosync(reply_q->os_irq);
	1752	+ reply_q->irq_line_enable = false;
	1753	+ }
	1754	+ num_entries = _base_process_reply_queue(reply_q);
	1755	+ if (num_entries < budget) {
	1756	+ irq_poll_complete(irqpoll);
	1757	+ reply_q->irq_poll_scheduled = false;
	1758	+ reply_q->irq_line_enable = true;
	1759	+ enable_irq(reply_q->os_irq);
	1760	+ /*
	1761	+ * Go for one more round of processing the
	1762	+ * reply descriptor post queue incase if HBA
	1763	+ * Firmware has posted some reply descriptors
	1764	+ * while reenabling the IRQ.
	1765	+ */
	1766	+ _base_process_reply_queue(reply_q);
	1767	+ }
	1768	+
	1769	+ return num_entries;
	1770	+}
	1771	+
	1772	+/**
	1773	+ * _base_init_irqpolls - initliaze IRQ polls
	1774	+ * @ioc: per adapter object
	1775	+ *
	1776	+ * returns nothing
	1777	+ */
	1778	+static void
	1779	+_base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
	1780	+{
	1781	+ struct adapter_reply_queue reply_q, next;
	1782	+
	1783	+ if (list_empty(&ioc->reply_queue_list))
	1784	+ return;
	1785	+
	1786	+ list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
	1787	+ irq_poll_init(&reply_q->irqpoll,
	1788	+ ioc->hba_queue_depth/4, _base_irqpoll);
	1789	+ reply_q->irq_poll_scheduled = false;
	1790	+ reply_q->irq_line_enable = true;
	1791	+ reply_q->os_irq = pci_irq_vector(ioc->pdev,
	1792	+ reply_q->msix_index);
	1793	+ }
1544	1794	}
1545	1795
1546	1796	/**
..	..	@@ -1559,12 +1809,14 @@
1559	1809	/**
1560	1810	* mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1561	1811	* @ioc: per adapter object
	1812	+ * @poll: poll over reply descriptor pools incase interrupt for
	1813	+ * timed-out SCSI command got delayed
1562	1814	* Context: non ISR conext
1563	1815	*
1564	1816	* Called when a Task Management request has completed.
1565	1817	*/
1566	1818	void
1567		-mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
	1819	+mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1568	1820	{
1569	1821	struct adapter_reply_queue *reply_q;
1570	1822
..	..	@@ -1582,6 +1834,24 @@
1582	1834	if (reply_q->msix_index == 0)
1583	1835	continue;
1584	1836	synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
	1837	+ if (reply_q->irq_poll_scheduled) {
	1838	+ /* Calling irq_poll_disable will wait for any pending
	1839	+ * callbacks to have completed.
	1840	+ */
	1841	+ irq_poll_disable(&reply_q->irqpoll);
	1842	+ irq_poll_enable(&reply_q->irqpoll);
	1843	+ /* check how the scheduled poll has ended,
	1844	+ * clean up only if necessary
	1845	+ */
	1846	+ if (reply_q->irq_poll_scheduled) {
	1847	+ reply_q->irq_poll_scheduled = false;
	1848	+ reply_q->irq_line_enable = true;
	1849	+ enable_irq(reply_q->os_irq);
	1850	+ }
	1851	+ }
	1852	+
	1853	+ if (poll)
	1854	+ _base_process_reply_queue(reply_q);
1585	1855	}
1586	1856	}
1587	1857
..	..	@@ -2122,6 +2392,11 @@
2122	2392	bool build_prp = true;
2123	2393
2124	2394	data_length = scsi_bufflen(scmd);
	2395	+ if (pcie_device &&
	2396	+ (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
	2397	+ build_prp = false;
	2398	+ return build_prp;
	2399	+ }
2125	2400
2126	2401	/* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2127	2402	* we built IEEE SGL
..	..	@@ -2270,7 +2545,7 @@
2270	2545	sges_left = scsi_dma_map(scmd);
2271	2546	if (sges_left < 0) {
2272	2547	sdev_printk(KERN_ERR, scmd->device,
2273		- "pci_map_sg failed: request for %d bytes!\n",
	2548	+ "scsi_dma_map failed: request for %d bytes!\n",
2274	2549	scsi_bufflen(scmd));
2275	2550	return -ENOMEM;
2276	2551	}
..	..	@@ -2418,7 +2693,7 @@
2418	2693	sges_left = scsi_dma_map(scmd);
2419	2694	if (sges_left < 0) {
2420	2695	sdev_printk(KERN_ERR, scmd->device,
2421		- "pci_map_sg failed: request for %d bytes!\n",
	2696	+ "scsi_dma_map failed: request for %d bytes!\n",
2422	2697	scsi_bufflen(scmd));
2423	2698	return -ENOMEM;
2424	2699	}
..	..	@@ -2564,57 +2839,39 @@
2564	2839	_base_config_dma_addressing(struct MPT3SAS_ADAPTER ioc, struct pci_dev pdev)
2565	2840	{
2566	2841	struct sysinfo s;
2567		- u64 consistent_dma_mask;
	2842	+ u64 coherent_dma_mask, dma_mask;
	2843	+
	2844	+ if (ioc->is_mcpu_endpoint \|\| sizeof(dma_addr_t) == 4) {
	2845	+ ioc->dma_mask = 32;
	2846	+ coherent_dma_mask = dma_mask = DMA_BIT_MASK(32);
2568	2847	/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
2569		- int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
2570		-
2571		- if (ioc->is_mcpu_endpoint)
2572		- goto try_32bit;
2573		-
2574		- if (ioc->dma_mask)
2575		- consistent_dma_mask = DMA_BIT_MASK(dma_mask);
2576		- else
2577		- consistent_dma_mask = DMA_BIT_MASK(32);
2578		-
2579		- if (sizeof(dma_addr_t) > 4) {
2580		- const uint64_t required_mask =
2581		- dma_get_required_mask(&pdev->dev);
2582		- if ((required_mask > DMA_BIT_MASK(32)) &&
2583		- !pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)) &&
2584		- !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
2585		- ioc->base_add_sg_single = &_base_add_sg_single_64;
2586		- ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2587		- ioc->dma_mask = dma_mask;
2588		- goto out;
2589		- }
	2848	+ } else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) {
	2849	+ ioc->dma_mask = 63;
	2850	+ coherent_dma_mask = dma_mask = DMA_BIT_MASK(63);
	2851	+ } else {
	2852	+ ioc->dma_mask = 64;
	2853	+ coherent_dma_mask = dma_mask = DMA_BIT_MASK(64);
2590	2854	}
2591	2855
2592		- try_32bit:
2593		- if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
2594		- && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2595		- ioc->base_add_sg_single = &_base_add_sg_single_32;
2596		- ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2597		- ioc->dma_mask = 32;
2598		- } else
	2856	+ if (ioc->use_32bit_dma)
	2857	+ coherent_dma_mask = DMA_BIT_MASK(32);
	2858	+
	2859	+ if (dma_set_mask(&pdev->dev, dma_mask) \|\|
	2860	+ dma_set_coherent_mask(&pdev->dev, coherent_dma_mask))
2599	2861	return -ENODEV;
2600	2862
2601		- out:
2602		- si_meminfo(&s);
2603		- pr_info(MPT3SAS_FMT
2604		- "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2605		- ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
2606		-
2607		- return 0;
2608		-}
2609		-
2610		-static int
2611		-_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
2612		- struct pci_dev *pdev)
2613		-{
2614		- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
2615		- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2616		- return -ENODEV;
	2863	+ if (ioc->dma_mask > 32) {
	2864	+ ioc->base_add_sg_single = &_base_add_sg_single_64;
	2865	+ ioc->sge_size = sizeof(Mpi2SGESimple64_t);
	2866	+ } else {
	2867	+ ioc->base_add_sg_single = &_base_add_sg_single_32;
	2868	+ ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2617	2869	}
	2870	+
	2871	+ si_meminfo(&s);
	2872	+ ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
	2873	+ ioc->dma_mask, convert_to_kb(s.totalram));
	2874	+
2618	2875	return 0;
2619	2876	}
2620	2877
..	..	@@ -2641,8 +2898,7 @@
2641	2898
2642	2899	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2643	2900	if (!base) {
2644		- dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
2645		- ioc->name));
	2901	+ dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
2646	2902	return -EINVAL;
2647	2903	}
2648	2904
..	..	@@ -2660,9 +2916,8 @@
2660	2916	pci_read_config_word(ioc->pdev, base + 2, &message_control);
2661	2917	ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2662	2918	}
2663		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
2664		- "msix is supported, vector_count(%d)\n",
2665		- ioc->name, ioc->msix_vector_count));
	2919	+ dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
	2920	+ ioc->msix_vector_count));
2666	2921	return 0;
2667	2922	}
2668	2923
..	..	@@ -2682,6 +2937,9 @@
2682	2937
2683	2938	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
2684	2939	list_del(&reply_q->list);
	2940	+ if (ioc->smp_affinity_enable)
	2941	+ irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
	2942	+ reply_q->msix_index), NULL);
2685	2943	free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
2686	2944	reply_q);
2687	2945	kfree(reply_q);
..	..	@@ -2704,8 +2962,8 @@
2704	2962
2705	2963	reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
2706	2964	if (!reply_q) {
2707		- pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
2708		- ioc->name, (int)sizeof(struct adapter_reply_queue));
	2965	+ ioc_err(ioc, "unable to allocate memory %zu!\n",
	2966	+ sizeof(struct adapter_reply_queue));
2709	2967	return -ENOMEM;
2710	2968	}
2711	2969	reply_q->ioc = ioc;
..	..	@@ -2721,7 +2979,7 @@
2721	2979	r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
2722	2980	IRQF_SHARED, reply_q->name, reply_q);
2723	2981	if (r) {
2724		- pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
	2982	+ pr_err("%s: unable to allocate interrupt %d!\n",
2725	2983	reply_q->name, pci_irq_vector(pdev, index));
2726	2984	kfree(reply_q);
2727	2985	return -EBUSY;
..	..	@@ -2746,8 +3004,12 @@
2746	3004	{
2747	3005	unsigned int cpu, nr_cpus, nr_msix, index = 0;
2748	3006	struct adapter_reply_queue *reply_q;
	3007	+ int local_numa_node;
2749	3008
2750	3009	if (!_base_is_controller_msix_enabled(ioc))
	3010	+ return;
	3011	+
	3012	+ if (ioc->msix_load_balance)
2751	3013	return;
2752	3014
2753	3015	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
..	..	@@ -2758,14 +3020,33 @@
2758	3020	if (!nr_msix)
2759	3021	return;
2760	3022
2761		- if (smp_affinity_enable) {
	3023	+ if (ioc->smp_affinity_enable) {
	3024	+
	3025	+ /*
	3026	+ * set irq affinity to local numa node for those irqs
	3027	+ * corresponding to high iops queues.
	3028	+ */
	3029	+ if (ioc->high_iops_queues) {
	3030	+ local_numa_node = dev_to_node(&ioc->pdev->dev);
	3031	+ for (index = 0; index < ioc->high_iops_queues;
	3032	+ index++) {
	3033	+ irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
	3034	+ index), cpumask_of_node(local_numa_node));
	3035	+ }
	3036	+ }
	3037	+
2762	3038	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2763		- const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev,
2764		- reply_q->msix_index);
2765		- if (!mask) {
2766		- pr_warn(MPT3SAS_FMT "no affinity for msi %x\n",
2767		- ioc->name, reply_q->msix_index);
	3039	+ const cpumask_t *mask;
	3040	+
	3041	+ if (reply_q->msix_index < ioc->high_iops_queues)
2768	3042	continue;
	3043	+
	3044	+ mask = pci_irq_get_affinity(ioc->pdev,
	3045	+ reply_q->msix_index);
	3046	+ if (!mask) {
	3047	+ ioc_warn(ioc, "no affinity for msi %x\n",
	3048	+ reply_q->msix_index);
	3049	+ goto fall_back;
2769	3050	}
2770	3051
2771	3052	for_each_cpu_and(cpu, mask, cpu_online_mask) {
..	..	@@ -2776,11 +3057,17 @@
2776	3057	}
2777	3058	return;
2778	3059	}
	3060	+
	3061	+fall_back:
2779	3062	cpu = cpumask_first(cpu_online_mask);
	3063	+ nr_msix -= ioc->high_iops_queues;
	3064	+ index = 0;
2780	3065
2781	3066	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2782		-
2783	3067	unsigned int i, group = nr_cpus / nr_msix;
	3068	+
	3069	+ if (reply_q->msix_index < ioc->high_iops_queues)
	3070	+ continue;
2784	3071
2785	3072	if (cpu >= nr_cpus)
2786	3073	break;
..	..	@@ -2797,6 +3084,52 @@
2797	3084	}
2798	3085
2799	3086	/**
	3087	+ * _base_check_and_enable_high_iops_queues - enable high iops mode
	3088	+ * @ioc: per adapter object
	3089	+ * @hba_msix_vector_count: msix vectors supported by HBA
	3090	+ *
	3091	+ * Enable high iops queues only if
	3092	+ * - HBA is a SEA/AERO controller and
	3093	+ * - MSI-Xs vector supported by the HBA is 128 and
	3094	+ * - total CPU count in the system >=16 and
	3095	+ * - loaded driver with default max_msix_vectors module parameter and
	3096	+ * - system booted in non kdump mode
	3097	+ *
	3098	+ * returns nothing.
	3099	+ */
	3100	+static void
	3101	+_base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
	3102	+ int hba_msix_vector_count)
	3103	+{
	3104	+ u16 lnksta, speed;
	3105	+
	3106	+ if (perf_mode == MPT_PERF_MODE_IOPS \|\|
	3107	+ perf_mode == MPT_PERF_MODE_LATENCY) {
	3108	+ ioc->high_iops_queues = 0;
	3109	+ return;
	3110	+ }
	3111	+
	3112	+ if (perf_mode == MPT_PERF_MODE_DEFAULT) {
	3113	+
	3114	+ pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
	3115	+ speed = lnksta & PCI_EXP_LNKSTA_CLS;
	3116	+
	3117	+ if (speed < 0x4) {
	3118	+ ioc->high_iops_queues = 0;
	3119	+ return;
	3120	+ }
	3121	+ }
	3122	+
	3123	+ if (!reset_devices && ioc->is_aero_ioc &&
	3124	+ hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
	3125	+ num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
	3126	+ max_msix_vectors == -1)
	3127	+ ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
	3128	+ else
	3129	+ ioc->high_iops_queues = 0;
	3130	+}
	3131	+
	3132	+/**
2800	3133	* _base_disable_msix - disables msix
2801	3134	* @ioc: per adapter object
2802	3135	*
..	..	@@ -2806,8 +3139,35 @@
2806	3139	{
2807	3140	if (!ioc->msix_enable)
2808	3141	return;
2809		- pci_disable_msix(ioc->pdev);
	3142	+ pci_free_irq_vectors(ioc->pdev);
2810	3143	ioc->msix_enable = 0;
	3144	+}
	3145	+
	3146	+/**
	3147	+ * _base_alloc_irq_vectors - allocate msix vectors
	3148	+ * @ioc: per adapter object
	3149	+ *
	3150	+ */
	3151	+static int
	3152	+_base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
	3153	+{
	3154	+ int i, irq_flags = PCI_IRQ_MSIX;
	3155	+ struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
	3156	+ struct irq_affinity *descp = &desc;
	3157	+
	3158	+ if (ioc->smp_affinity_enable)
	3159	+ irq_flags \|= PCI_IRQ_AFFINITY;
	3160	+ else
	3161	+ descp = NULL;
	3162	+
	3163	+ ioc_info(ioc, " %d %d\n", ioc->high_iops_queues,
	3164	+ ioc->reply_queue_count);
	3165	+
	3166	+ i = pci_alloc_irq_vectors_affinity(ioc->pdev,
	3167	+ ioc->high_iops_queues,
	3168	+ ioc->reply_queue_count, irq_flags, descp);
	3169	+
	3170	+ return i;
2811	3171	}
2812	3172
2813	3173	/**
..	..	@@ -2821,7 +3181,8 @@
2821	3181	int r;
2822	3182	int i, local_max_msix_vectors;
2823	3183	u8 try_msix = 0;
2824		- unsigned int irq_flags = PCI_IRQ_MSIX;
	3184	+
	3185	+ ioc->msix_load_balance = false;
2825	3186
2826	3187	if (msix_disable == -1 \|\| msix_disable == 0)
2827	3188	try_msix = 1;
..	..	@@ -2832,12 +3193,15 @@
2832	3193	if (_base_check_enable_msix(ioc) != 0)
2833	3194	goto try_ioapic;
2834	3195
2835		- ioc->reply_queue_count = min_t(int, ioc->cpu_count,
	3196	+ ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
	3197	+ pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
	3198	+ ioc->cpu_count, max_msix_vectors);
	3199	+ if (ioc->is_aero_ioc)
	3200	+ _base_check_and_enable_high_iops_queues(ioc,
	3201	+ ioc->msix_vector_count);
	3202	+ ioc->reply_queue_count =
	3203	+ min_t(int, ioc->cpu_count + ioc->high_iops_queues,
2836	3204	ioc->msix_vector_count);
2837		-
2838		- printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
2839		- ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
2840		- ioc->cpu_count, max_msix_vectors);
2841	3205
2842	3206	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
2843	3207	local_max_msix_vectors = (reset_devices) ? 1 : 8;
..	..	@@ -2850,18 +3214,27 @@
2850	3214	else if (local_max_msix_vectors == 0)
2851	3215	goto try_ioapic;
2852	3216
2853		- if (ioc->msix_vector_count < ioc->cpu_count)
2854		- smp_affinity_enable = 0;
	3217	+ /*
	3218	+ * Enable msix_load_balance only if combined reply queue mode is
	3219	+ * disabled on SAS3 & above generation HBA devices.
	3220	+ */
	3221	+ if (!ioc->combined_reply_queue &&
	3222	+ ioc->hba_mpi_version_belonged != MPI2_VERSION) {
	3223	+ ioc_info(ioc,
	3224	+ "combined ReplyQueue is off, Enabling msix load balance\n");
	3225	+ ioc->msix_load_balance = true;
	3226	+ }
2855	3227
2856		- if (smp_affinity_enable)
2857		- irq_flags \|= PCI_IRQ_AFFINITY;
	3228	+ /*
	3229	+ * smp affinity setting is not need when msix load balance
	3230	+ * is enabled.
	3231	+ */
	3232	+ if (ioc->msix_load_balance)
	3233	+ ioc->smp_affinity_enable = 0;
2858	3234
2859		- r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count,
2860		- irq_flags);
	3235	+ r = _base_alloc_irq_vectors(ioc);
2861	3236	if (r < 0) {
2862		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
2863		- "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2864		- ioc->name, r));
	3237	+ ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
2865	3238	goto try_ioapic;
2866	3239	}
2867	3240
..	..	@@ -2876,17 +3249,21 @@
2876	3249	}
2877	3250	}
2878	3251
	3252	+ ioc_info(ioc, "High IOPs queues : %s\n",
	3253	+ ioc->high_iops_queues ? "enabled" : "disabled");
	3254	+
2879	3255	return 0;
2880	3256
2881	3257	/* failback to io_apic interrupt routing */
2882	3258	try_ioapic:
2883		-
	3259	+ ioc->high_iops_queues = 0;
	3260	+ ioc_info(ioc, "High IOPs queues : disabled\n");
2884	3261	ioc->reply_queue_count = 1;
2885	3262	r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
2886	3263	if (r < 0) {
2887		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
2888		- "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2889		- ioc->name, r));
	3264	+ dfailprintk(ioc,
	3265	+ ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
	3266	+ r));
2890	3267	} else
2891	3268	r = _base_request_irq(ioc, 0);
2892	3269
..	..	@@ -2902,8 +3279,7 @@
2902	3279	{
2903	3280	struct pci_dev *pdev = ioc->pdev;
2904	3281
2905		- dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2906		- ioc->name, __func__));
	3282	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2907	3283
2908	3284	_base_free_irq(ioc);
2909	3285	_base_disable_msix(ioc);
..	..	@@ -2924,6 +3300,43 @@
2924	3300	}
2925	3301	}
2926	3302
	3303	+static int
	3304	+_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
	3305	+
	3306	+/**
	3307	+ * _base_check_for_fault_and_issue_reset - check if IOC is in fault state
	3308	+ * and if it is in fault state then issue diag reset.
	3309	+ * @ioc: per adapter object
	3310	+ *
	3311	+ * Returns: 0 for success, non-zero for failure.
	3312	+ */
	3313	+static int
	3314	+_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
	3315	+{
	3316	+ u32 ioc_state;
	3317	+ int rc = -EFAULT;
	3318	+
	3319	+ dinitprintk(ioc, pr_info("%s\n", __func__));
	3320	+ if (ioc->pci_error_recovery)
	3321	+ return 0;
	3322	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
	3323	+ dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
	3324	+
	3325	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	3326	+ mpt3sas_print_fault_code(ioc, ioc_state &
	3327	+ MPI2_DOORBELL_DATA_MASK);
	3328	+ rc = _base_diag_reset(ioc);
	3329	+ } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	3330	+ MPI2_IOC_STATE_COREDUMP) {
	3331	+ mpt3sas_print_coredump_info(ioc, ioc_state &
	3332	+ MPI2_DOORBELL_DATA_MASK);
	3333	+ mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
	3334	+ rc = _base_diag_reset(ioc);
	3335	+ }
	3336	+
	3337	+ return rc;
	3338	+}
	3339	+
2927	3340	/**
2928	3341	* mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2929	3342	* @ioc: per adapter object
..	..	@@ -2936,18 +3349,16 @@
2936	3349	struct pci_dev *pdev = ioc->pdev;
2937	3350	u32 memap_sz;
2938	3351	u32 pio_sz;
2939		- int i, r = 0;
	3352	+ int i, r = 0, rc;
2940	3353	u64 pio_chip = 0;
2941	3354	phys_addr_t chip_phys = 0;
2942	3355	struct adapter_reply_queue *reply_q;
2943	3356
2944		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2945		- ioc->name, __func__));
	3357	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2946	3358
2947	3359	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2948	3360	if (pci_enable_device_mem(pdev)) {
2949		- pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2950		- ioc->name);
	3361	+ ioc_warn(ioc, "pci_enable_device_mem: failed\n");
2951	3362	ioc->bars = 0;
2952	3363	return -ENODEV;
2953	3364	}
..	..	@@ -2955,8 +3366,7 @@
2955	3366
2956	3367	if (pci_request_selected_regions(pdev, ioc->bars,
2957	3368	ioc->driver_name)) {
2958		- pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2959		- ioc->name);
	3369	+ ioc_warn(ioc, "pci_request_selected_regions: failed\n");
2960	3370	ioc->bars = 0;
2961	3371	r = -ENODEV;
2962	3372	goto out_fail;
..	..	@@ -2969,8 +3379,7 @@
2969	3379
2970	3380
2971	3381	if (_base_config_dma_addressing(ioc, pdev) != 0) {
2972		- pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2973		- ioc->name, pci_name(pdev));
	3382	+ ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
2974	3383	r = -ENODEV;
2975	3384	goto out_fail;
2976	3385	}
..	..	@@ -2993,17 +3402,20 @@
2993	3402	}
2994	3403
2995	3404	if (ioc->chip == NULL) {
2996		- pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2997		- " or resource not found\n", ioc->name);
	3405	+ ioc_err(ioc,
	3406	+ "unable to map adapter memory! or resource not found\n");
2998	3407	r = -EINVAL;
2999	3408	goto out_fail;
3000	3409	}
3001	3410
3002		- _base_mask_interrupts(ioc);
	3411	+ mpt3sas_base_mask_interrupts(ioc);
3003	3412
3004	3413	r = _base_get_ioc_facts(ioc);
3005		- if (r)
3006		- goto out_fail;
	3414	+ if (r) {
	3415	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	3416	+ if (rc \|\| (_base_get_ioc_facts(ioc)))
	3417	+ goto out_fail;
	3418	+ }
3007	3419
3008	3420	if (!ioc->rdpq_array_enable_assigned) {
3009	3421	ioc->rdpq_array_enable = ioc->rdpq_array_capable;
..	..	@@ -3014,6 +3426,8 @@
3014	3426	if (r)
3015	3427	goto out_fail;
3016	3428
	3429	+ if (!ioc->is_driver_loading)
	3430	+ _base_init_irqpolls(ioc);
3017	3431	/* Use the Combined reply queue feature only for SAS3 C0 & higher
3018	3432	* revision HBAs and also only when reply queue count is greater than 8
3019	3433	*/
..	..	@@ -3028,9 +3442,8 @@
3028	3442	ioc->combined_reply_index_count,
3029	3443	sizeof(resource_size_t *), GFP_KERNEL);
3030	3444	if (!ioc->replyPostRegisterIndex) {
3031		- dfailprintk(ioc, printk(MPT3SAS_FMT
3032		- "allocation for reply Post Register Index failed!!!\n",
3033		- ioc->name));
	3445	+ ioc_err(ioc,
	3446	+ "allocation for replyPostRegisterIndex failed!\n");
3034	3447	r = -ENOMEM;
3035	3448	goto out_fail;
3036	3449	}
..	..	@@ -3055,15 +3468,15 @@
3055	3468	}
3056	3469
3057	3470	list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
3058		- pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
3059		- reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
3060		- "IO-APIC enabled"),
3061		- pci_irq_vector(ioc->pdev, reply_q->msix_index));
	3471	+ pr_info("%s: %s enabled: IRQ %d\n",
	3472	+ reply_q->name,
	3473	+ ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
	3474	+ pci_irq_vector(ioc->pdev, reply_q->msix_index));
3062	3475
3063		- pr_info(MPT3SAS_FMT "iomem(%pap), mapped(0x%p), size(%d)\n",
3064		- ioc->name, &chip_phys, ioc->chip, memap_sz);
3065		- pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
3066		- ioc->name, (unsigned long long)pio_chip, pio_sz);
	3476	+ ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
	3477	+ &chip_phys, ioc->chip, memap_sz);
	3478	+ ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
	3479	+ (unsigned long long)pio_chip, pio_sz);
3067	3480
3068	3481	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
3069	3482	pci_save_state(pdev);
..	..	@@ -3155,10 +3568,71 @@
3155	3568	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3156	3569	}
3157	3570
	3571	+/**
	3572	+ * _base_get_msix_index - get the msix index
	3573	+ * @ioc: per adapter object
	3574	+ * @scmd: scsi_cmnd object
	3575	+ *
	3576	+ * returns msix index of general reply queues,
	3577	+ * i.e. reply queue on which IO request's reply
	3578	+ * should be posted by the HBA firmware.
	3579	+ */
3158	3580	static inline u8
3159		-_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
	3581	+_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
	3582	+ struct scsi_cmnd *scmd)
3160	3583	{
	3584	+ /* Enables reply_queue load balancing */
	3585	+ if (ioc->msix_load_balance)
	3586	+ return ioc->reply_queue_count ?
	3587	+ base_mod64(atomic64_add_return(1,
	3588	+ &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
	3589	+
3161	3590	return ioc->cpu_msix_table[raw_smp_processor_id()];
	3591	+}
	3592	+
	3593	+/**
	3594	+ * _base_sdev_nr_inflight_request -get number of inflight requests
	3595	+ * of a request queue.
	3596	+ * @q: request_queue object
	3597	+ *
	3598	+ * returns number of inflight request of a request queue.
	3599	+ */
	3600	+inline unsigned long
	3601	+_base_sdev_nr_inflight_request(struct request_queue *q)
	3602	+{
	3603	+ struct blk_mq_hw_ctx *hctx = q->queue_hw_ctx[0];
	3604	+
	3605	+ return atomic_read(&hctx->nr_active);
	3606	+}
	3607	+
	3608	+
	3609	+/**
	3610	+ * _base_get_high_iops_msix_index - get the msix index of
	3611	+ * high iops queues
	3612	+ * @ioc: per adapter object
	3613	+ * @scmd: scsi_cmnd object
	3614	+ *
	3615	+ * Returns: msix index of high iops reply queues.
	3616	+ * i.e. high iops reply queue on which IO request's
	3617	+ * reply should be posted by the HBA firmware.
	3618	+ */
	3619	+static inline u8
	3620	+_base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
	3621	+ struct scsi_cmnd *scmd)
	3622	+{
	3623	+ /**
	3624	+ * Round robin the IO interrupts among the high iops
	3625	+ * reply queues in terms of batch count 16 when outstanding
	3626	+ * IOs on the target device is >=8.
	3627	+ */
	3628	+ if (_base_sdev_nr_inflight_request(scmd->device->request_queue) >
	3629	+ MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
	3630	+ return base_mod64((
	3631	+ atomic64_add_return(1, &ioc->high_iops_outstanding) /
	3632	+ MPT3SAS_HIGH_IOPS_BATCH_COUNT),
	3633	+ MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
	3634	+
	3635	+ return _base_get_msix_index(ioc, scmd);
3162	3636	}
3163	3637
3164	3638	/**
..	..	@@ -3178,8 +3652,7 @@
3178	3652	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3179	3653	if (list_empty(&ioc->internal_free_list)) {
3180	3654	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3181		- pr_err(MPT3SAS_FMT "%s: smid not available\n",
3182		- ioc->name, __func__);
	3655	+ ioc_err(ioc, "%s: smid not available\n", __func__);
3183	3656	return 0;
3184	3657	}
3185	3658
..	..	@@ -3210,8 +3683,8 @@
3210	3683
3211	3684	smid = tag + 1;
3212	3685	request->cb_idx = cb_idx;
3213		- request->msix_io = _base_get_msix_index(ioc);
3214	3686	request->smid = smid;
	3687	+ request->scmd = scmd;
3215	3688	INIT_LIST_HEAD(&request->chain_list);
3216	3689	return smid;
3217	3690	}
..	..	@@ -3265,6 +3738,7 @@
3265	3738	return;
3266	3739	st->cb_idx = 0xFF;
3267	3740	st->direct_io = 0;
	3741	+ st->scmd = NULL;
3268	3742	atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
3269	3743	st->smid = 0;
3270	3744	}
..	..	@@ -3334,7 +3808,6 @@
3334	3808	spin_lock_irqsave(writeq_lock, flags);
3335	3809	__raw_writel((u32)(b), addr);
3336	3810	__raw_writel((u32)(b >> 32), (addr + 4));
3337		- mmiowb();
3338	3811	spin_unlock_irqrestore(writeq_lock, flags);
3339	3812	}
3340	3813
..	..	@@ -3365,13 +3838,37 @@
3365	3838	#endif
3366	3839
3367	3840	/**
	3841	+ * _base_set_and_get_msix_index - get the msix index and assign to msix_io
	3842	+ * variable of scsi tracker
	3843	+ * @ioc: per adapter object
	3844	+ * @smid: system request message index
	3845	+ *
	3846	+ * returns msix index.
	3847	+ */
	3848	+static u8
	3849	+_base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	3850	+{
	3851	+ struct scsiio_tracker *st = NULL;
	3852	+
	3853	+ if (smid < ioc->hi_priority_smid)
	3854	+ st = _get_st_from_smid(ioc, smid);
	3855	+
	3856	+ if (st == NULL)
	3857	+ return _base_get_msix_index(ioc, NULL);
	3858	+
	3859	+ st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
	3860	+ return st->msix_io;
	3861	+}
	3862	+
	3863	+/**
3368	3864	* _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
3369	3865	* @ioc: per adapter object
3370	3866	* @smid: system request message index
3371	3867	* @handle: device handle
3372	3868	*/
3373	3869	static void
3374		-_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
	3870	+_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
	3871	+ u16 smid, u16 handle)
3375	3872	{
3376	3873	Mpi2RequestDescriptorUnion_t descriptor;
3377	3874	u64 request = (u64 )&descriptor;
..	..	@@ -3384,7 +3881,7 @@
3384	3881	_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3385	3882	ioc->request_sz);
3386	3883	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3387		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3884	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3388	3885	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3389	3886	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3390	3887	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3406,7 +3903,7 @@
3406	3903
3407	3904
3408	3905	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3409		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3906	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3410	3907	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3411	3908	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3412	3909	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3415,13 +3912,13 @@
3415	3912	}
3416	3913
3417	3914	/**
3418		- * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
	3915	+ * _base_put_smid_fast_path - send fast path request to firmware
3419	3916	* @ioc: per adapter object
3420	3917	* @smid: system request message index
3421	3918	* @handle: device handle
3422	3919	*/
3423		-void
3424		-mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	3920	+static void
	3921	+_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3425	3922	u16 handle)
3426	3923	{
3427	3924	Mpi2RequestDescriptorUnion_t descriptor;
..	..	@@ -3429,7 +3926,7 @@
3429	3926
3430	3927	descriptor.SCSIIO.RequestFlags =
3431	3928	MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3432		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3929	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3433	3930	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3434	3931	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3435	3932	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3438,13 +3935,13 @@
3438	3935	}
3439	3936
3440	3937	/**
3441		- * mpt3sas_base_put_smid_hi_priority - send Task Management request to firmware
	3938	+ * _base_put_smid_hi_priority - send Task Management request to firmware
3442	3939	* @ioc: per adapter object
3443	3940	* @smid: system request message index
3444	3941	* @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
3445	3942	*/
3446		-void
3447		-mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	3943	+static void
	3944	+_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3448	3945	u16 msix_task)
3449	3946	{
3450	3947	Mpi2RequestDescriptorUnion_t descriptor;
..	..	@@ -3493,7 +3990,7 @@
3493	3990
3494	3991	descriptor.Default.RequestFlags =
3495	3992	MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
3496		- descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
	3993	+ descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3497	3994	descriptor.Default.SMID = cpu_to_le16(smid);
3498	3995	descriptor.Default.LMID = 0;
3499	3996	descriptor.Default.DescriptorTypeDependent = 0;
..	..	@@ -3502,12 +3999,12 @@
3502	3999	}
3503	4000
3504	4001	/**
3505		- * mpt3sas_base_put_smid_default - Default, primarily used for config pages
	4002	+ * _base_put_smid_default - Default, primarily used for config pages
3506	4003	* @ioc: per adapter object
3507	4004	* @smid: system request message index
3508	4005	*/
3509		-void
3510		-mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	4006	+static void
	4007	+_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3511	4008	{
3512	4009	Mpi2RequestDescriptorUnion_t descriptor;
3513	4010	void *mpi_req_iomem;
..	..	@@ -3525,7 +4022,7 @@
3525	4022	}
3526	4023	request = (u64 *)&descriptor;
3527	4024	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3528		- descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
	4025	+ descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3529	4026	descriptor.Default.SMID = cpu_to_le16(smid);
3530	4027	descriptor.Default.LMID = 0;
3531	4028	descriptor.Default.DescriptorTypeDependent = 0;
..	..	@@ -3536,6 +4033,95 @@
3536	4033	else
3537	4034	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3538	4035	&ioc->scsi_lookup_lock);
	4036	+}
	4037	+
	4038	+/**
	4039	+ * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
	4040	+ * Atomic Request Descriptor
	4041	+ * @ioc: per adapter object
	4042	+ * @smid: system request message index
	4043	+ * @handle: device handle, unused in this function, for function type match
	4044	+ *
	4045	+ * Return nothing.
	4046	+ */
	4047	+static void
	4048	+_base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4049	+ u16 handle)
	4050	+{
	4051	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4052	+ u32 request = (u32 )&descriptor;
	4053	+
	4054	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
	4055	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4056	+ descriptor.SMID = cpu_to_le16(smid);
	4057	+
	4058	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4059	+}
	4060	+
	4061	+/**
	4062	+ * _base_put_smid_fast_path_atomic - send fast path request to firmware
	4063	+ * using Atomic Request Descriptor
	4064	+ * @ioc: per adapter object
	4065	+ * @smid: system request message index
	4066	+ * @handle: device handle, unused in this function, for function type match
	4067	+ * Return nothing
	4068	+ */
	4069	+static void
	4070	+_base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4071	+ u16 handle)
	4072	+{
	4073	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4074	+ u32 request = (u32 )&descriptor;
	4075	+
	4076	+ descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
	4077	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4078	+ descriptor.SMID = cpu_to_le16(smid);
	4079	+
	4080	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4081	+}
	4082	+
	4083	+/**
	4084	+ * _base_put_smid_hi_priority_atomic - send Task Management request to
	4085	+ * firmware using Atomic Request Descriptor
	4086	+ * @ioc: per adapter object
	4087	+ * @smid: system request message index
	4088	+ * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
	4089	+ *
	4090	+ * Return nothing.
	4091	+ */
	4092	+static void
	4093	+_base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4094	+ u16 msix_task)
	4095	+{
	4096	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4097	+ u32 request = (u32 )&descriptor;
	4098	+
	4099	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
	4100	+ descriptor.MSIxIndex = msix_task;
	4101	+ descriptor.SMID = cpu_to_le16(smid);
	4102	+
	4103	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4104	+}
	4105	+
	4106	+/**
	4107	+ * _base_put_smid_default - Default, primarily used for config pages
	4108	+ * use Atomic Request Descriptor
	4109	+ * @ioc: per adapter object
	4110	+ * @smid: system request message index
	4111	+ *
	4112	+ * Return nothing.
	4113	+ */
	4114	+static void
	4115	+_base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	4116	+{
	4117	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4118	+ u32 request = (u32 )&descriptor;
	4119	+
	4120	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
	4121	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4122	+ descriptor.SMID = cpu_to_le16(smid);
	4123	+
	4124	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3539	4125	}
3540	4126
3541	4127	/**
..	..	@@ -3554,89 +4140,87 @@
3554	4140	case MPI2_MFGPAGE_DEVID_SAS2008:
3555	4141	switch (ioc->pdev->subsystem_device) {
3556	4142	case MPT2SAS_INTEL_RMS2LL080_SSDID:
3557		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3558		- MPT2SAS_INTEL_RMS2LL080_BRANDING);
	4143	+ ioc_info(ioc, "%s\n",
	4144	+ MPT2SAS_INTEL_RMS2LL080_BRANDING);
3559	4145	break;
3560	4146	case MPT2SAS_INTEL_RMS2LL040_SSDID:
3561		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3562		- MPT2SAS_INTEL_RMS2LL040_BRANDING);
	4147	+ ioc_info(ioc, "%s\n",
	4148	+ MPT2SAS_INTEL_RMS2LL040_BRANDING);
3563	4149	break;
3564	4150	case MPT2SAS_INTEL_SSD910_SSDID:
3565		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3566		- MPT2SAS_INTEL_SSD910_BRANDING);
	4151	+ ioc_info(ioc, "%s\n",
	4152	+ MPT2SAS_INTEL_SSD910_BRANDING);
3567	4153	break;
3568	4154	default:
3569		- pr_info(MPT3SAS_FMT
3570		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3571		- ioc->name, ioc->pdev->subsystem_device);
	4155	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4156	+ ioc->pdev->subsystem_device);
3572	4157	break;
3573	4158	}
	4159	+ break;
3574	4160	case MPI2_MFGPAGE_DEVID_SAS2308_2:
3575	4161	switch (ioc->pdev->subsystem_device) {
3576	4162	case MPT2SAS_INTEL_RS25GB008_SSDID:
3577		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3578		- MPT2SAS_INTEL_RS25GB008_BRANDING);
	4163	+ ioc_info(ioc, "%s\n",
	4164	+ MPT2SAS_INTEL_RS25GB008_BRANDING);
3579	4165	break;
3580	4166	case MPT2SAS_INTEL_RMS25JB080_SSDID:
3581		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3582		- MPT2SAS_INTEL_RMS25JB080_BRANDING);
	4167	+ ioc_info(ioc, "%s\n",
	4168	+ MPT2SAS_INTEL_RMS25JB080_BRANDING);
3583	4169	break;
3584	4170	case MPT2SAS_INTEL_RMS25JB040_SSDID:
3585		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3586		- MPT2SAS_INTEL_RMS25JB040_BRANDING);
	4171	+ ioc_info(ioc, "%s\n",
	4172	+ MPT2SAS_INTEL_RMS25JB040_BRANDING);
3587	4173	break;
3588	4174	case MPT2SAS_INTEL_RMS25KB080_SSDID:
3589		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3590		- MPT2SAS_INTEL_RMS25KB080_BRANDING);
	4175	+ ioc_info(ioc, "%s\n",
	4176	+ MPT2SAS_INTEL_RMS25KB080_BRANDING);
3591	4177	break;
3592	4178	case MPT2SAS_INTEL_RMS25KB040_SSDID:
3593		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3594		- MPT2SAS_INTEL_RMS25KB040_BRANDING);
	4179	+ ioc_info(ioc, "%s\n",
	4180	+ MPT2SAS_INTEL_RMS25KB040_BRANDING);
3595	4181	break;
3596	4182	case MPT2SAS_INTEL_RMS25LB040_SSDID:
3597		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3598		- MPT2SAS_INTEL_RMS25LB040_BRANDING);
	4183	+ ioc_info(ioc, "%s\n",
	4184	+ MPT2SAS_INTEL_RMS25LB040_BRANDING);
3599	4185	break;
3600	4186	case MPT2SAS_INTEL_RMS25LB080_SSDID:
3601		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3602		- MPT2SAS_INTEL_RMS25LB080_BRANDING);
	4187	+ ioc_info(ioc, "%s\n",
	4188	+ MPT2SAS_INTEL_RMS25LB080_BRANDING);
3603	4189	break;
3604	4190	default:
3605		- pr_info(MPT3SAS_FMT
3606		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3607		- ioc->name, ioc->pdev->subsystem_device);
	4191	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4192	+ ioc->pdev->subsystem_device);
3608	4193	break;
3609	4194	}
	4195	+ break;
3610	4196	case MPI25_MFGPAGE_DEVID_SAS3008:
3611	4197	switch (ioc->pdev->subsystem_device) {
3612	4198	case MPT3SAS_INTEL_RMS3JC080_SSDID:
3613		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3614		- MPT3SAS_INTEL_RMS3JC080_BRANDING);
	4199	+ ioc_info(ioc, "%s\n",
	4200	+ MPT3SAS_INTEL_RMS3JC080_BRANDING);
3615	4201	break;
3616	4202
3617	4203	case MPT3SAS_INTEL_RS3GC008_SSDID:
3618		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3619		- MPT3SAS_INTEL_RS3GC008_BRANDING);
	4204	+ ioc_info(ioc, "%s\n",
	4205	+ MPT3SAS_INTEL_RS3GC008_BRANDING);
3620	4206	break;
3621	4207	case MPT3SAS_INTEL_RS3FC044_SSDID:
3622		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3623		- MPT3SAS_INTEL_RS3FC044_BRANDING);
	4208	+ ioc_info(ioc, "%s\n",
	4209	+ MPT3SAS_INTEL_RS3FC044_BRANDING);
3624	4210	break;
3625	4211	case MPT3SAS_INTEL_RS3UC080_SSDID:
3626		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3627		- MPT3SAS_INTEL_RS3UC080_BRANDING);
	4212	+ ioc_info(ioc, "%s\n",
	4213	+ MPT3SAS_INTEL_RS3UC080_BRANDING);
3628	4214	break;
3629	4215	default:
3630		- pr_info(MPT3SAS_FMT
3631		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3632		- ioc->name, ioc->pdev->subsystem_device);
	4216	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4217	+ ioc->pdev->subsystem_device);
3633	4218	break;
3634	4219	}
3635	4220	break;
3636	4221	default:
3637		- pr_info(MPT3SAS_FMT
3638		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3639		- ioc->name, ioc->pdev->subsystem_device);
	4222	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4223	+ ioc->pdev->subsystem_device);
3640	4224	break;
3641	4225	}
3642	4226	break;
..	..	@@ -3645,57 +4229,54 @@
3645	4229	case MPI2_MFGPAGE_DEVID_SAS2008:
3646	4230	switch (ioc->pdev->subsystem_device) {
3647	4231	case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
3648		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3649		- MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
	4232	+ ioc_info(ioc, "%s\n",
	4233	+ MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
3650	4234	break;
3651	4235	case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
3652		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3653		- MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
	4236	+ ioc_info(ioc, "%s\n",
	4237	+ MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
3654	4238	break;
3655	4239	case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
3656		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3657		- MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
	4240	+ ioc_info(ioc, "%s\n",
	4241	+ MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
3658	4242	break;
3659	4243	case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
3660		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3661		- MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
	4244	+ ioc_info(ioc, "%s\n",
	4245	+ MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
3662	4246	break;
3663	4247	case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
3664		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3665		- MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
	4248	+ ioc_info(ioc, "%s\n",
	4249	+ MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
3666	4250	break;
3667	4251	case MPT2SAS_DELL_PERC_H200_SSDID:
3668		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3669		- MPT2SAS_DELL_PERC_H200_BRANDING);
	4252	+ ioc_info(ioc, "%s\n",
	4253	+ MPT2SAS_DELL_PERC_H200_BRANDING);
3670	4254	break;
3671	4255	case MPT2SAS_DELL_6GBPS_SAS_SSDID:
3672		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3673		- MPT2SAS_DELL_6GBPS_SAS_BRANDING);
	4256	+ ioc_info(ioc, "%s\n",
	4257	+ MPT2SAS_DELL_6GBPS_SAS_BRANDING);
3674	4258	break;
3675	4259	default:
3676		- pr_info(MPT3SAS_FMT
3677		- "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
3678		- ioc->name, ioc->pdev->subsystem_device);
	4260	+ ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
	4261	+ ioc->pdev->subsystem_device);
3679	4262	break;
3680	4263	}
3681	4264	break;
3682	4265	case MPI25_MFGPAGE_DEVID_SAS3008:
3683	4266	switch (ioc->pdev->subsystem_device) {
3684	4267	case MPT3SAS_DELL_12G_HBA_SSDID:
3685		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3686		- MPT3SAS_DELL_12G_HBA_BRANDING);
	4268	+ ioc_info(ioc, "%s\n",
	4269	+ MPT3SAS_DELL_12G_HBA_BRANDING);
3687	4270	break;
3688	4271	default:
3689		- pr_info(MPT3SAS_FMT
3690		- "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
3691		- ioc->name, ioc->pdev->subsystem_device);
	4272	+ ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
	4273	+ ioc->pdev->subsystem_device);
3692	4274	break;
3693	4275	}
3694	4276	break;
3695	4277	default:
3696		- pr_info(MPT3SAS_FMT
3697		- "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
3698		- ioc->pdev->subsystem_device);
	4278	+ ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
	4279	+ ioc->pdev->subsystem_device);
3699	4280	break;
3700	4281	}
3701	4282	break;
..	..	@@ -3704,46 +4285,42 @@
3704	4285	case MPI25_MFGPAGE_DEVID_SAS3008:
3705	4286	switch (ioc->pdev->subsystem_device) {
3706	4287	case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
3707		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3708		- MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
	4288	+ ioc_info(ioc, "%s\n",
	4289	+ MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
3709	4290	break;
3710	4291	case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
3711		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3712		- MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
	4292	+ ioc_info(ioc, "%s\n",
	4293	+ MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
3713	4294	break;
3714	4295	case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3715		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3716		- MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
	4296	+ ioc_info(ioc, "%s\n",
	4297	+ MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3717	4298	break;
3718	4299	default:
3719		- pr_info(MPT3SAS_FMT
3720		- "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3721		- ioc->name, ioc->pdev->subsystem_device);
	4300	+ ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4301	+ ioc->pdev->subsystem_device);
3722	4302	break;
3723	4303	}
3724	4304	break;
3725	4305	case MPI25_MFGPAGE_DEVID_SAS3108_1:
3726	4306	switch (ioc->pdev->subsystem_device) {
3727	4307	case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3728		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3729		- MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
	4308	+ ioc_info(ioc, "%s\n",
	4309	+ MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3730	4310	break;
3731	4311	case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
3732		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3733		- MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
3734		- );
	4312	+ ioc_info(ioc, "%s\n",
	4313	+ MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
3735	4314	break;
3736	4315	default:
3737		- pr_info(MPT3SAS_FMT
3738		- "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3739		- ioc->name, ioc->pdev->subsystem_device);
	4316	+ ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4317	+ ioc->pdev->subsystem_device);
3740	4318	break;
3741	4319	}
3742	4320	break;
3743	4321	default:
3744		- pr_info(MPT3SAS_FMT
3745		- "Cisco SAS HBA: Subsystem ID: 0x%X\n",
3746		- ioc->name, ioc->pdev->subsystem_device);
	4322	+ ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
	4323	+ ioc->pdev->subsystem_device);
3747	4324	break;
3748	4325	}
3749	4326	break;
..	..	@@ -3752,43 +4329,42 @@
3752	4329	case MPI2_MFGPAGE_DEVID_SAS2004:
3753	4330	switch (ioc->pdev->subsystem_device) {
3754	4331	case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
3755		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3756		- MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
	4332	+ ioc_info(ioc, "%s\n",
	4333	+ MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
3757	4334	break;
3758	4335	default:
3759		- pr_info(MPT3SAS_FMT
3760		- "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3761		- ioc->name, ioc->pdev->subsystem_device);
	4336	+ ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4337	+ ioc->pdev->subsystem_device);
3762	4338	break;
3763	4339	}
	4340	+ break;
3764	4341	case MPI2_MFGPAGE_DEVID_SAS2308_2:
3765	4342	switch (ioc->pdev->subsystem_device) {
3766	4343	case MPT2SAS_HP_2_4_INTERNAL_SSDID:
3767		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3768		- MPT2SAS_HP_2_4_INTERNAL_BRANDING);
	4344	+ ioc_info(ioc, "%s\n",
	4345	+ MPT2SAS_HP_2_4_INTERNAL_BRANDING);
3769	4346	break;
3770	4347	case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
3771		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3772		- MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
	4348	+ ioc_info(ioc, "%s\n",
	4349	+ MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
3773	4350	break;
3774	4351	case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
3775		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3776		- MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
	4352	+ ioc_info(ioc, "%s\n",
	4353	+ MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
3777	4354	break;
3778	4355	case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
3779		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3780		- MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
	4356	+ ioc_info(ioc, "%s\n",
	4357	+ MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
3781	4358	break;
3782	4359	default:
3783		- pr_info(MPT3SAS_FMT
3784		- "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3785		- ioc->name, ioc->pdev->subsystem_device);
	4360	+ ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4361	+ ioc->pdev->subsystem_device);
3786	4362	break;
3787	4363	}
	4364	+ break;
3788	4365	default:
3789		- pr_info(MPT3SAS_FMT
3790		- "HP SAS HBA: Subsystem ID: 0x%X\n",
3791		- ioc->name, ioc->pdev->subsystem_device);
	4366	+ ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
	4367	+ ioc->pdev->subsystem_device);
3792	4368	break;
3793	4369	}
3794	4370	default:
..	..	@@ -3806,37 +4382,37 @@
3806	4382	static int
3807	4383	_base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
3808	4384	{
3809		- Mpi2FWImageHeader_t *FWImgHdr;
	4385	+ Mpi2FWImageHeader_t *fw_img_hdr;
	4386	+ Mpi26ComponentImageHeader_t *cmp_img_hdr;
3810	4387	Mpi25FWUploadRequest_t *mpi_request;
3811	4388	Mpi2FWUploadReply_t mpi_reply;
3812	4389	int r = 0;
	4390	+ u32 package_version = 0;
3813	4391	void *fwpkg_data = NULL;
3814	4392	dma_addr_t fwpkg_data_dma;
3815	4393	u16 smid, ioc_status;
3816	4394	size_t data_length;
3817	4395
3818		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3819		- __func__));
	4396	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3820	4397
3821	4398	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
3822		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
3823		- ioc->name, __func__);
	4399	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
3824	4400	return -EAGAIN;
3825	4401	}
3826	4402
3827	4403	data_length = sizeof(Mpi2FWImageHeader_t);
3828		- fwpkg_data = pci_alloc_consistent(ioc->pdev, data_length,
3829		- &fwpkg_data_dma);
	4404	+ fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
	4405	+ &fwpkg_data_dma, GFP_KERNEL);
3830	4406	if (!fwpkg_data) {
3831		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3832		- ioc->name, __FILE__, __LINE__, __func__);
	4407	+ ioc_err(ioc,
	4408	+ "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
	4409	+ __FILE__, __LINE__, __func__);
3833	4410	return -ENOMEM;
3834	4411	}
3835	4412
3836	4413	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3837	4414	if (!smid) {
3838		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3839		- ioc->name, __func__);
	4415	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
3840	4416	r = -EAGAIN;
3841	4417	goto out;
3842	4418	}
..	..	@@ -3851,15 +4427,13 @@
3851	4427	ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
3852	4428	data_length);
3853	4429	init_completion(&ioc->base_cmds.done);
3854		- mpt3sas_base_put_smid_default(ioc, smid);
	4430	+ ioc->put_smid_default(ioc, smid);
3855	4431	/* Wait for 15 seconds */
3856	4432	wait_for_completion_timeout(&ioc->base_cmds.done,
3857	4433	FW_IMG_HDR_READ_TIMEOUT*HZ);
3858		- pr_info(MPT3SAS_FMT "%s: complete\n",
3859		- ioc->name, __func__);
	4434	+ ioc_info(ioc, "%s: complete\n", __func__);
3860	4435	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3861		- pr_err(MPT3SAS_FMT "%s: timeout\n",
3862		- ioc->name, __func__);
	4436	+ ioc_err(ioc, "%s: timeout\n", __func__);
3863	4437	_debug_dump_mf(mpi_request,
3864	4438	sizeof(Mpi25FWUploadRequest_t)/4);
3865	4439	r = -ETIME;
..	..	@@ -3871,16 +4445,26 @@
3871	4445	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
3872	4446	MPI2_IOCSTATUS_MASK;
3873	4447	if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3874		- FWImgHdr = (Mpi2FWImageHeader_t *)fwpkg_data;
3875		- if (FWImgHdr->PackageVersion.Word) {
3876		- pr_info(MPT3SAS_FMT "FW Package Version"
3877		- "(%02d.%02d.%02d.%02d)\n",
3878		- ioc->name,
3879		- FWImgHdr->PackageVersion.Struct.Major,
3880		- FWImgHdr->PackageVersion.Struct.Minor,
3881		- FWImgHdr->PackageVersion.Struct.Unit,
3882		- FWImgHdr->PackageVersion.Struct.Dev);
3883		- }
	4448	+ fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
	4449	+ if (le32_to_cpu(fw_img_hdr->Signature) ==
	4450	+ MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
	4451	+ cmp_img_hdr =
	4452	+ (Mpi26ComponentImageHeader_t *)
	4453	+ (fwpkg_data);
	4454	+ package_version =
	4455	+ le32_to_cpu(
	4456	+ cmp_img_hdr->ApplicationSpecific);
	4457	+ } else
	4458	+ package_version =
	4459	+ le32_to_cpu(
	4460	+ fw_img_hdr->PackageVersion.Word);
	4461	+ if (package_version)
	4462	+ ioc_info(ioc,
	4463	+ "FW Package Ver(%02d.%02d.%02d.%02d)\n",
	4464	+ ((package_version) & 0xFF000000) >> 24,
	4465	+ ((package_version) & 0x00FF0000) >> 16,
	4466	+ ((package_version) & 0x0000FF00) >> 8,
	4467	+ (package_version) & 0x000000FF);
3884	4468	} else {
3885	4469	_debug_dump_mf(&mpi_reply,
3886	4470	sizeof(Mpi2FWUploadReply_t)/4);
..	..	@@ -3890,7 +4474,7 @@
3890	4474	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3891	4475	out:
3892	4476	if (fwpkg_data)
3893		- pci_free_consistent(ioc->pdev, data_length, fwpkg_data,
	4477	+ dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
3894	4478	fwpkg_data_dma);
3895	4479	return r;
3896	4480	}
..	..	@@ -3909,18 +4493,17 @@
3909	4493
3910	4494	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
3911	4495	strncpy(desc, ioc->manu_pg0.ChipName, 16);
3912		- pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
3913		- "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
3914		- ioc->name, desc,
3915		- (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
3916		- (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
3917		- (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
3918		- ioc->facts.FWVersion.Word & 0x000000FF,
3919		- ioc->pdev->revision,
3920		- (bios_version & 0xFF000000) >> 24,
3921		- (bios_version & 0x00FF0000) >> 16,
3922		- (bios_version & 0x0000FF00) >> 8,
3923		- bios_version & 0x000000FF);
	4496	+ ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
	4497	+ desc,
	4498	+ (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
	4499	+ (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
	4500	+ (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
	4501	+ ioc->facts.FWVersion.Word & 0x000000FF,
	4502	+ ioc->pdev->revision,
	4503	+ (bios_version & 0xFF000000) >> 24,
	4504	+ (bios_version & 0x00FF0000) >> 16,
	4505	+ (bios_version & 0x0000FF00) >> 8,
	4506	+ bios_version & 0x000000FF);
3924	4507
3925	4508	_base_display_OEMs_branding(ioc);
3926	4509
..	..	@@ -3929,82 +4512,81 @@
3929	4512	i++;
3930	4513	}
3931	4514
3932		- pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
	4515	+ ioc_info(ioc, "Protocol=(");
3933	4516
3934	4517	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
3935		- pr_info("Initiator");
	4518	+ pr_cont("Initiator");
3936	4519	i++;
3937	4520	}
3938	4521
3939	4522	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
3940		- pr_info("%sTarget", i ? "," : "");
	4523	+ pr_cont("%sTarget", i ? "," : "");
3941	4524	i++;
3942	4525	}
3943	4526
3944	4527	i = 0;
3945		- pr_info("), ");
3946		- pr_info("Capabilities=(");
	4528	+ pr_cont("), Capabilities=(");
3947	4529
3948	4530	if (!ioc->hide_ir_msg) {
3949	4531	if (ioc->facts.IOCCapabilities &
3950	4532	MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
3951		- pr_info("Raid");
	4533	+ pr_cont("Raid");
3952	4534	i++;
3953	4535	}
3954	4536	}
3955	4537
3956	4538	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
3957		- pr_info("%sTLR", i ? "," : "");
	4539	+ pr_cont("%sTLR", i ? "," : "");
3958	4540	i++;
3959	4541	}
3960	4542
3961	4543	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
3962		- pr_info("%sMulticast", i ? "," : "");
	4544	+ pr_cont("%sMulticast", i ? "," : "");
3963	4545	i++;
3964	4546	}
3965	4547
3966	4548	if (ioc->facts.IOCCapabilities &
3967	4549	MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
3968		- pr_info("%sBIDI Target", i ? "," : "");
	4550	+ pr_cont("%sBIDI Target", i ? "," : "");
3969	4551	i++;
3970	4552	}
3971	4553
3972	4554	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
3973		- pr_info("%sEEDP", i ? "," : "");
	4555	+ pr_cont("%sEEDP", i ? "," : "");
3974	4556	i++;
3975	4557	}
3976	4558
3977	4559	if (ioc->facts.IOCCapabilities &
3978	4560	MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
3979		- pr_info("%sSnapshot Buffer", i ? "," : "");
	4561	+ pr_cont("%sSnapshot Buffer", i ? "," : "");
3980	4562	i++;
3981	4563	}
3982	4564
3983	4565	if (ioc->facts.IOCCapabilities &
3984	4566	MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
3985		- pr_info("%sDiag Trace Buffer", i ? "," : "");
	4567	+ pr_cont("%sDiag Trace Buffer", i ? "," : "");
3986	4568	i++;
3987	4569	}
3988	4570
3989	4571	if (ioc->facts.IOCCapabilities &
3990	4572	MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
3991		- pr_info("%sDiag Extended Buffer", i ? "," : "");
	4573	+ pr_cont("%sDiag Extended Buffer", i ? "," : "");
3992	4574	i++;
3993	4575	}
3994	4576
3995	4577	if (ioc->facts.IOCCapabilities &
3996	4578	MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
3997		- pr_info("%sTask Set Full", i ? "," : "");
	4579	+ pr_cont("%sTask Set Full", i ? "," : "");
3998	4580	i++;
3999	4581	}
4000	4582
4001	4583	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4002	4584	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4003		- pr_info("%sNCQ", i ? "," : "");
	4585	+ pr_cont("%sNCQ", i ? "," : "");
4004	4586	i++;
4005	4587	}
4006	4588
4007		- pr_info(")\n");
	4589	+ pr_cont(")\n");
4008	4590	}
4009	4591
4010	4592	/**
..	..	@@ -4037,21 +4619,21 @@
4037	4619	sizeof(Mpi2SasIOUnit1PhyData_t));
4038	4620	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4039	4621	if (!sas_iounit_pg1) {
4040		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4041		- ioc->name, __FILE__, __LINE__, __func__);
	4622	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4623	+ __FILE__, __LINE__, __func__);
4042	4624	goto out;
4043	4625	}
4044	4626	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4045	4627	sas_iounit_pg1, sz))) {
4046		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4047		- ioc->name, __FILE__, __LINE__, __func__);
	4628	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4629	+ __FILE__, __LINE__, __func__);
4048	4630	goto out;
4049	4631	}
4050	4632	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4051	4633	MPI2_IOCSTATUS_MASK;
4052	4634	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4053		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4054		- ioc->name, __FILE__, __LINE__, __func__);
	4635	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4636	+ __FILE__, __LINE__, __func__);
4055	4637	goto out;
4056	4638	}
4057	4639
..	..	@@ -4083,17 +4665,82 @@
4083	4665	else
4084	4666	dmd_new =
4085	4667	dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4086		- pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
4087		- ioc->name, dmd_orignal, dmd_new);
4088		- pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
4089		- ioc->name, io_missing_delay_original,
4090		- io_missing_delay);
	4668	+ ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
	4669	+ dmd_orignal, dmd_new);
	4670	+ ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
	4671	+ io_missing_delay_original,
	4672	+ io_missing_delay);
4091	4673	ioc->device_missing_delay = dmd_new;
4092	4674	ioc->io_missing_delay = io_missing_delay;
4093	4675	}
4094	4676
4095	4677	out:
4096	4678	kfree(sas_iounit_pg1);
	4679	+}
	4680	+
	4681	+/**
	4682	+ * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
	4683	+ * according to performance mode.
	4684	+ * @ioc : per adapter object
	4685	+ *
	4686	+ * Return nothing.
	4687	+ */
	4688	+static void
	4689	+_base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
	4690	+{
	4691	+ Mpi2IOCPage1_t ioc_pg1;
	4692	+ Mpi2ConfigReply_t mpi_reply;
	4693	+
	4694	+ mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
	4695	+ memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
	4696	+
	4697	+ switch (perf_mode) {
	4698	+ case MPT_PERF_MODE_DEFAULT:
	4699	+ case MPT_PERF_MODE_BALANCED:
	4700	+ if (ioc->high_iops_queues) {
	4701	+ ioc_info(ioc,
	4702	+ "Enable interrupt coalescing only for first\t"
	4703	+ "%d reply queues\n",
	4704	+ MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
	4705	+ /*
	4706	+ * If 31st bit is zero then interrupt coalescing is
	4707	+ * enabled for all reply descriptor post queues.
	4708	+ * If 31st bit is set to one then user can
	4709	+ * enable/disable interrupt coalescing on per reply
	4710	+ * descriptor post queue group(8) basis. So to enable
	4711	+ * interrupt coalescing only on first reply descriptor
	4712	+ * post queue group 31st bit and zero th bit is enabled.
	4713	+ */
	4714	+ ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 \|
	4715	+ ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
	4716	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4717	+ ioc_info(ioc, "performance mode: balanced\n");
	4718	+ return;
	4719	+ }
	4720	+ fallthrough;
	4721	+ case MPT_PERF_MODE_LATENCY:
	4722	+ /*
	4723	+ * Enable interrupt coalescing on all reply queues
	4724	+ * with timeout value 0xA
	4725	+ */
	4726	+ ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
	4727	+ ioc_pg1.Flags \|= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
	4728	+ ioc_pg1.ProductSpecific = 0;
	4729	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4730	+ ioc_info(ioc, "performance mode: latency\n");
	4731	+ break;
	4732	+ case MPT_PERF_MODE_IOPS:
	4733	+ /*
	4734	+ * Enable interrupt coalescing on all reply queues.
	4735	+ */
	4736	+ ioc_info(ioc,
	4737	+ "performance mode: iops with coalescing timeout: 0x%x\n",
	4738	+ le32_to_cpu(ioc_pg1.CoalescingTimeout));
	4739	+ ioc_pg1.Flags \|= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
	4740	+ ioc_pg1.ProductSpecific = 0;
	4741	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4742	+ break;
	4743	+ }
4097	4744	}
4098	4745
4099	4746	/**
..	..	@@ -4163,6 +4810,8 @@
4163	4810
4164	4811	if (ioc->iounit_pg8.NumSensors)
4165	4812	ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
	4813	+ if (ioc->is_aero_ioc)
	4814	+ _base_update_ioc_page1_inlinewith_perf_mode(ioc);
4166	4815	}
4167	4816
4168	4817	/**
..	..	@@ -4195,36 +4844,36 @@
4195	4844	{
4196	4845	int i = 0;
4197	4846	int j = 0;
	4847	+ int dma_alloc_count = 0;
4198	4848	struct chain_tracker *ct;
4199		- struct reply_post_struct *rps;
	4849	+ int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
4200	4850
4201		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4202		- __func__));
	4851	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4203	4852
4204	4853	if (ioc->request) {
4205		- pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
	4854	+ dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
4206	4855	ioc->request, ioc->request_dma);
4207		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4208		- "request_pool(0x%p): free\n",
4209		- ioc->name, ioc->request));
	4856	+ dexitprintk(ioc,
	4857	+ ioc_info(ioc, "request_pool(0x%p): free\n",
	4858	+ ioc->request));
4210	4859	ioc->request = NULL;
4211	4860	}
4212	4861
4213	4862	if (ioc->sense) {
4214	4863	dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4215	4864	dma_pool_destroy(ioc->sense_dma_pool);
4216		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4217		- "sense_pool(0x%p): free\n",
4218		- ioc->name, ioc->sense));
	4865	+ dexitprintk(ioc,
	4866	+ ioc_info(ioc, "sense_pool(0x%p): free\n",
	4867	+ ioc->sense));
4219	4868	ioc->sense = NULL;
4220	4869	}
4221	4870
4222	4871	if (ioc->reply) {
4223	4872	dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
4224	4873	dma_pool_destroy(ioc->reply_dma_pool);
4225		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4226		- "reply_pool(0x%p): free\n",
4227		- ioc->name, ioc->reply));
	4874	+ dexitprintk(ioc,
	4875	+ ioc_info(ioc, "reply_pool(0x%p): free\n",
	4876	+ ioc->reply));
4228	4877	ioc->reply = NULL;
4229	4878	}
4230	4879
..	..	@@ -4232,36 +4881,41 @@
4232	4881	dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
4233	4882	ioc->reply_free_dma);
4234	4883	dma_pool_destroy(ioc->reply_free_dma_pool);
4235		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4236		- "reply_free_pool(0x%p): free\n",
4237		- ioc->name, ioc->reply_free));
	4884	+ dexitprintk(ioc,
	4885	+ ioc_info(ioc, "reply_free_pool(0x%p): free\n",
	4886	+ ioc->reply_free));
4238	4887	ioc->reply_free = NULL;
4239	4888	}
4240	4889
4241	4890	if (ioc->reply_post) {
4242		- do {
4243		- rps = &ioc->reply_post[i];
4244		- if (rps->reply_post_free) {
4245		- dma_pool_free(
4246		- ioc->reply_post_free_dma_pool,
4247		- rps->reply_post_free,
4248		- rps->reply_post_free_dma);
4249		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4250		- "reply_post_free_pool(0x%p): free\n",
4251		- ioc->name, rps->reply_post_free));
4252		- rps->reply_post_free = NULL;
	4891	+ dma_alloc_count = DIV_ROUND_UP(count,
	4892	+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
	4893	+ for (i = 0; i < count; i++) {
	4894	+ if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
	4895	+ && dma_alloc_count) {
	4896	+ if (ioc->reply_post[i].reply_post_free) {
	4897	+ dma_pool_free(
	4898	+ ioc->reply_post_free_dma_pool,
	4899	+ ioc->reply_post[i].reply_post_free,
	4900	+ ioc->reply_post[i].reply_post_free_dma);
	4901	+ dexitprintk(ioc, ioc_info(ioc,
	4902	+ "reply_post_free_pool(0x%p): free\n",
	4903	+ ioc->reply_post[i].reply_post_free));
	4904	+ ioc->reply_post[i].reply_post_free =
	4905	+ NULL;
	4906	+ }
	4907	+ --dma_alloc_count;
4253	4908	}
4254		- } while (ioc->rdpq_array_enable &&
4255		- (++i < ioc->reply_queue_count));
	4909	+ }
	4910	+ dma_pool_destroy(ioc->reply_post_free_dma_pool);
4256	4911	if (ioc->reply_post_free_array &&
4257	4912	ioc->rdpq_array_enable) {
4258	4913	dma_pool_free(ioc->reply_post_free_array_dma_pool,
4259		- ioc->reply_post_free_array,
4260		- ioc->reply_post_free_array_dma);
	4914	+ ioc->reply_post_free_array,
	4915	+ ioc->reply_post_free_array_dma);
4261	4916	ioc->reply_post_free_array = NULL;
4262	4917	}
4263	4918	dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
4264		- dma_pool_destroy(ioc->reply_post_free_dma_pool);
4265	4919	kfree(ioc->reply_post);
4266	4920	}
4267	4921
..	..	@@ -4270,16 +4924,18 @@
4270	4924	dma_pool_free(ioc->pcie_sgl_dma_pool,
4271	4925	ioc->pcie_sg_lookup[i].pcie_sgl,
4272	4926	ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	4927	+ ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
4273	4928	}
4274		- if (ioc->pcie_sgl_dma_pool)
4275		- dma_pool_destroy(ioc->pcie_sgl_dma_pool);
	4929	+ dma_pool_destroy(ioc->pcie_sgl_dma_pool);
4276	4930	}
	4931	+ kfree(ioc->pcie_sg_lookup);
	4932	+ ioc->pcie_sg_lookup = NULL;
4277	4933
4278	4934	if (ioc->config_page) {
4279		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4280		- "config_page(0x%p): free\n", ioc->name,
4281		- ioc->config_page));
4282		- pci_free_consistent(ioc->pdev, ioc->config_page_sz,
	4935	+ dexitprintk(ioc,
	4936	+ ioc_info(ioc, "config_page(0x%p): free\n",
	4937	+ ioc->config_page));
	4938	+ dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
4283	4939	ioc->config_page, ioc->config_page_dma);
4284	4940	}
4285	4941
..	..	@@ -4306,7 +4962,7 @@
4306	4962	}
4307	4963
4308	4964	/**
4309		- * is_MSB_are_same - checks whether all reply queues in a set are
	4965	+ * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
4310	4966	* having same upper 32bits in their base memory address.
4311	4967	* @reply_pool_start_address: Base address of a reply queue set
4312	4968	* @pool_sz: Size of single Reply Descriptor Post Queues pool size
..	..	@@ -4316,7 +4972,7 @@
4316	4972	*/
4317	4973
4318	4974	static int
4319		-is_MSB_are_same(long reply_pool_start_address, u32 pool_sz)
	4975	+mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
4320	4976	{
4321	4977	long reply_pool_end_address;
4322	4978
..	..	@@ -4327,6 +4983,168 @@
4327	4983	return 1;
4328	4984	else
4329	4985	return 0;
	4986	+}
	4987	+
	4988	+/**
	4989	+ * _base_reduce_hba_queue_depth- Retry with reduced queue depth
	4990	+ * @ioc: Adapter object
	4991	+ *
	4992	+ * Return: 0 for success, non-zero for failure.
	4993	+ **/
	4994	+static inline int
	4995	+_base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
	4996	+{
	4997	+ int reduce_sz = 64;
	4998	+
	4999	+ if ((ioc->hba_queue_depth - reduce_sz) >
	5000	+ (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
	5001	+ ioc->hba_queue_depth -= reduce_sz;
	5002	+ return 0;
	5003	+ } else
	5004	+ return -ENOMEM;
	5005	+}
	5006	+
	5007	+/**
	5008	+ * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
	5009	+ * for pcie sgl pools.
	5010	+ * @ioc: Adapter object
	5011	+ * @sz: DMA Pool size
	5012	+ * @ct: Chain tracker
	5013	+ * Return: 0 for success, non-zero for failure.
	5014	+ */
	5015	+
	5016	+static int
	5017	+_base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
	5018	+{
	5019	+ int i = 0, j = 0;
	5020	+ struct chain_tracker *ct;
	5021	+
	5022	+ ioc->pcie_sgl_dma_pool =
	5023	+ dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
	5024	+ ioc->page_size, 0);
	5025	+ if (!ioc->pcie_sgl_dma_pool) {
	5026	+ ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
	5027	+ return -ENOMEM;
	5028	+ }
	5029	+
	5030	+ ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
	5031	+ ioc->chains_per_prp_buffer =
	5032	+ min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
	5033	+ for (i = 0; i < ioc->scsiio_depth; i++) {
	5034	+ ioc->pcie_sg_lookup[i].pcie_sgl =
	5035	+ dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
	5036	+ &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	5037	+ if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
	5038	+ ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
	5039	+ return -EAGAIN;
	5040	+ }
	5041	+
	5042	+ if (!mpt3sas_check_same_4gb_region(
	5043	+ (long)ioc->pcie_sg_lookup[i].pcie_sgl, sz)) {
	5044	+ ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
	5045	+ ioc->pcie_sg_lookup[i].pcie_sgl,
	5046	+ (unsigned long long)
	5047	+ ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	5048	+ ioc->use_32bit_dma = true;
	5049	+ return -EAGAIN;
	5050	+ }
	5051	+
	5052	+ for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
	5053	+ ct = &ioc->chain_lookup[i].chains_per_smid[j];
	5054	+ ct->chain_buffer =
	5055	+ ioc->pcie_sg_lookup[i].pcie_sgl +
	5056	+ (j * ioc->chain_segment_sz);
	5057	+ ct->chain_buffer_dma =
	5058	+ ioc->pcie_sg_lookup[i].pcie_sgl_dma +
	5059	+ (j * ioc->chain_segment_sz);
	5060	+ }
	5061	+ }
	5062	+ dinitprintk(ioc, ioc_info(ioc,
	5063	+ "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
	5064	+ ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
	5065	+ dinitprintk(ioc, ioc_info(ioc,
	5066	+ "Number of chains can fit in a PRP page(%d)\n",
	5067	+ ioc->chains_per_prp_buffer));
	5068	+ return 0;
	5069	+}
	5070	+
	5071	+/**
	5072	+ * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
	5073	+ * for reply queues.
	5074	+ * @ioc: per adapter object
	5075	+ * @sz: DMA Pool size
	5076	+ * Return: 0 for success, non-zero for failure.
	5077	+ */
	5078	+static int
	5079	+base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
	5080	+{
	5081	+ int i = 0;
	5082	+ u32 dma_alloc_count = 0;
	5083	+ int reply_post_free_sz = ioc->reply_post_queue_depth *
	5084	+ sizeof(Mpi2DefaultReplyDescriptor_t);
	5085	+ int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
	5086	+
	5087	+ ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
	5088	+ GFP_KERNEL);
	5089	+ if (!ioc->reply_post)
	5090	+ return -ENOMEM;
	5091	+ /*
	5092	+ * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
	5093	+ * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
	5094	+ * be within 4GB boundary i.e reply queues in a set must have same
	5095	+ * upper 32-bits in their memory address. so here driver is allocating
	5096	+ * the DMA'able memory for reply queues according.
	5097	+ * Driver uses limitation of
	5098	+ * VENTURA_SERIES to manage INVADER_SERIES as well.
	5099	+ */
	5100	+ dma_alloc_count = DIV_ROUND_UP(count,
	5101	+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
	5102	+ ioc->reply_post_free_dma_pool =
	5103	+ dma_pool_create("reply_post_free pool",
	5104	+ &ioc->pdev->dev, sz, 16, 0);
	5105	+ if (!ioc->reply_post_free_dma_pool)
	5106	+ return -ENOMEM;
	5107	+ for (i = 0; i < count; i++) {
	5108	+ if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
	5109	+ ioc->reply_post[i].reply_post_free =
	5110	+ dma_pool_zalloc(ioc->reply_post_free_dma_pool,
	5111	+ GFP_KERNEL,
	5112	+ &ioc->reply_post[i].reply_post_free_dma);
	5113	+ if (!ioc->reply_post[i].reply_post_free)
	5114	+ return -ENOMEM;
	5115	+ /*
	5116	+ * Each set of RDPQ pool must satisfy 4gb boundary
	5117	+ * restriction.
	5118	+ * 1) Check if allocated resources for RDPQ pool are in
	5119	+ * the same 4GB range.
	5120	+ * 2) If #1 is true, continue with 64 bit DMA.
	5121	+ * 3) If #1 is false, return 1. which means free all the
	5122	+ * resources and set DMA mask to 32 and allocate.
	5123	+ */
	5124	+ if (!mpt3sas_check_same_4gb_region(
	5125	+ (long)ioc->reply_post[i].reply_post_free, sz)) {
	5126	+ dinitprintk(ioc,
	5127	+ ioc_err(ioc, "bad Replypost free pool(0x%p)"
	5128	+ "reply_post_free_dma = (0x%llx)\n",
	5129	+ ioc->reply_post[i].reply_post_free,
	5130	+ (unsigned long long)
	5131	+ ioc->reply_post[i].reply_post_free_dma));
	5132	+ return -EAGAIN;
	5133	+ }
	5134	+ dma_alloc_count--;
	5135	+
	5136	+ } else {
	5137	+ ioc->reply_post[i].reply_post_free =
	5138	+ (Mpi2ReplyDescriptorsUnion_t *)
	5139	+ ((long)ioc->reply_post[i-1].reply_post_free
	5140	+ + reply_post_free_sz);
	5141	+ ioc->reply_post[i].reply_post_free_dma =
	5142	+ (dma_addr_t)
	5143	+ (ioc->reply_post[i-1].reply_post_free_dma +
	5144	+ reply_post_free_sz);
	5145	+ }
	5146	+ }
	5147	+ return 0;
4330	5148	}
4331	5149
4332	5150	/**
..	..	@@ -4343,14 +5161,15 @@
4343	5161	u16 chains_needed_per_io;
4344	5162	u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
4345	5163	u32 retry_sz;
	5164	+ u32 rdpq_sz = 0;
4346	5165	u16 max_request_credit, nvme_blocks_needed;
4347	5166	unsigned short sg_tablesize;
4348	5167	u16 sge_size;
4349	5168	int i, j;
	5169	+ int ret = 0, rc = 0;
4350	5170	struct chain_tracker *ct;
4351	5171
4352		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4353		- __func__));
	5172	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4354	5173
4355	5174
4356	5175	retry_sz = 0;
..	..	@@ -4379,10 +5198,8 @@
4379	5198	else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
4380	5199	sg_tablesize = min_t(unsigned short, sg_tablesize,
4381	5200	SG_MAX_SEGMENTS);
4382		- pr_warn(MPT3SAS_FMT
4383		- "sg_tablesize(%u) is bigger than kernel "
4384		- "defined SG_CHUNK_SIZE(%u)\n", ioc->name,
4385		- sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
	5201	+ ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
	5202	+ sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
4386	5203	}
4387	5204	ioc->shost->sg_tablesize = sg_tablesize;
4388	5205	}
..	..	@@ -4392,9 +5209,8 @@
4392	5209	if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
4393	5210	if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
4394	5211	INTERNAL_SCSIIO_CMDS_COUNT)) {
4395		- pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
4396		- Credits, it has just %d number of credits\n",
4397		- ioc->name, facts->RequestCredit);
	5212	+ ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
	5213	+ facts->RequestCredit);
4398	5214	return -ENOMEM;
4399	5215	}
4400	5216	ioc->internal_depth = 10;
..	..	@@ -4493,71 +5309,39 @@
4493	5309	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
4494	5310	}
4495	5311
4496		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
4497		- "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
4498		- "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
4499		- ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
4500		- ioc->chains_needed_per_io));
	5312	+ ioc_info(ioc,
	5313	+ "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
	5314	+ "sge_per_io(%d), chains_per_io(%d)\n",
	5315	+ ioc->max_sges_in_main_message,
	5316	+ ioc->max_sges_in_chain_message,
	5317	+ ioc->shost->sg_tablesize,
	5318	+ ioc->chains_needed_per_io);
4501	5319
4502	5320	/* reply post queue, 16 byte align */
4503	5321	reply_post_free_sz = ioc->reply_post_queue_depth *
4504	5322	sizeof(Mpi2DefaultReplyDescriptor_t);
4505		-
4506		- sz = reply_post_free_sz;
	5323	+ rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
4507	5324	if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
4508		- sz *= ioc->reply_queue_count;
4509		-
4510		- ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
4511		- (ioc->reply_queue_count):1,
4512		- sizeof(struct reply_post_struct), GFP_KERNEL);
4513		-
4514		- if (!ioc->reply_post) {
4515		- pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
4516		- ioc->name);
4517		- goto out;
4518		- }
4519		- ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
4520		- &ioc->pdev->dev, sz, 16, 0);
4521		- if (!ioc->reply_post_free_dma_pool) {
4522		- pr_err(MPT3SAS_FMT
4523		- "reply_post_free pool: dma_pool_create failed\n",
4524		- ioc->name);
4525		- goto out;
4526		- }
4527		- i = 0;
4528		- do {
4529		- ioc->reply_post[i].reply_post_free =
4530		- dma_pool_alloc(ioc->reply_post_free_dma_pool,
4531		- GFP_KERNEL,
4532		- &ioc->reply_post[i].reply_post_free_dma);
4533		- if (!ioc->reply_post[i].reply_post_free) {
4534		- pr_err(MPT3SAS_FMT
4535		- "reply_post_free pool: dma_pool_alloc failed\n",
4536		- ioc->name);
4537		- goto out;
	5325	+ rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
	5326	+ ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
	5327	+ if (ret == -EAGAIN) {
	5328	+ /*
	5329	+ * Free allocated bad RDPQ memory pools.
	5330	+ * Change dma coherent mask to 32 bit and reallocate RDPQ
	5331	+ */
	5332	+ _base_release_memory_pools(ioc);
	5333	+ ioc->use_32bit_dma = true;
	5334	+ if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
	5335	+ ioc_err(ioc,
	5336	+ "32 DMA mask failed %s\n", pci_name(ioc->pdev));
	5337	+ return -ENODEV;
4538	5338	}
4539		- memset(ioc->reply_post[i].reply_post_free, 0, sz);
4540		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4541		- "reply post free pool (0x%p): depth(%d),"
4542		- "element_size(%d), pool_size(%d kB)\n", ioc->name,
4543		- ioc->reply_post[i].reply_post_free,
4544		- ioc->reply_post_queue_depth, 8, sz/1024));
4545		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4546		- "reply_post_free_dma = (0x%llx)\n", ioc->name,
4547		- (unsigned long long)
4548		- ioc->reply_post[i].reply_post_free_dma));
4549		- total_sz += sz;
4550		- } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
4551		-
4552		- if (ioc->dma_mask > 32) {
4553		- if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
4554		- pr_warn(MPT3SAS_FMT
4555		- "no suitable consistent DMA mask for %s\n",
4556		- ioc->name, pci_name(ioc->pdev));
4557		- goto out;
4558		- }
4559		- }
4560		-
	5339	+ if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
	5340	+ return -ENOMEM;
	5341	+ } else if (ret == -ENOMEM)
	5342	+ return -ENOMEM;
	5343	+ total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
	5344	+ DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
4561	5345	ioc->scsiio_depth = ioc->hba_queue_depth -
4562	5346	ioc->hi_priority_depth - ioc->internal_depth;
4563	5347
..	..	@@ -4565,10 +5349,9 @@
4565	5349	* with some internal commands that could be outstanding
4566	5350	*/
4567	5351	ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
4568		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4569		- "scsi host: can_queue depth (%d)\n",
4570		- ioc->name, ioc->shost->can_queue));
4571		-
	5352	+ dinitprintk(ioc,
	5353	+ ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
	5354	+ ioc->shost->can_queue));
4572	5355
4573	5356	/* contiguous pool for request and chains, 16 byte align, one extra "
4574	5357	* "frame for smid=0
..	..	@@ -4583,12 +5366,12 @@
4583	5366	sz += (ioc->internal_depth * ioc->request_sz);
4584	5367
4585	5368	ioc->request_dma_sz = sz;
4586		- ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
	5369	+ ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
	5370	+ &ioc->request_dma, GFP_KERNEL);
4587	5371	if (!ioc->request) {
4588		- pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4589		- "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4590		- "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
4591		- ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
	5372	+ ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
	5373	+ ioc->hba_queue_depth, ioc->chains_needed_per_io,
	5374	+ ioc->request_sz, sz / 1024);
4592	5375	if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
4593	5376	goto out;
4594	5377	retry_sz = 64;
..	..	@@ -4598,10 +5381,9 @@
4598	5381	}
4599	5382
4600	5383	if (retry_sz)
4601		- pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4602		- "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4603		- "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
4604		- ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
	5384	+ ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
	5385	+ ioc->hba_queue_depth, ioc->chains_needed_per_io,
	5386	+ ioc->request_sz, sz / 1024);
4605	5387
4606	5388	/* hi-priority queue */
4607	5389	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
..	..	@@ -4615,24 +5397,24 @@
4615	5397	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
4616	5398	ioc->request_sz);
4617	5399
4618		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4619		- "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4620		- ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
4621		- (ioc->hba_queue_depth * ioc->request_sz)/1024));
	5400	+ ioc_info(ioc,
	5401	+ "request pool(0x%p) - dma(0x%llx): "
	5402	+ "depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5403	+ ioc->request, (unsigned long long) ioc->request_dma,
	5404	+ ioc->hba_queue_depth, ioc->request_sz,
	5405	+ (ioc->hba_queue_depth * ioc->request_sz) / 1024);
4622	5406
4623		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
4624		- ioc->name, (unsigned long long) ioc->request_dma));
4625	5407	total_sz += sz;
4626	5408
4627		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
4628		- ioc->name, ioc->request, ioc->scsiio_depth));
	5409	+ dinitprintk(ioc,
	5410	+ ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
	5411	+ ioc->request, ioc->scsiio_depth));
4629	5412
4630	5413	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
4631	5414	sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
4632	5415	ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
4633	5416	if (!ioc->chain_lookup) {
4634		- pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages "
4635		- "failed\n", ioc->name);
	5417	+ ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
4636	5418	goto out;
4637	5419	}
4638	5420
..	..	@@ -4640,8 +5422,7 @@
4640	5422	for (i = 0; i < ioc->scsiio_depth; i++) {
4641	5423	ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
4642	5424	if (!ioc->chain_lookup[i].chains_per_smid) {
4643		- pr_err(MPT3SAS_FMT "chain_lookup: "
4644		- " kzalloc failed\n", ioc->name);
	5425	+ ioc_err(ioc, "chain_lookup: kzalloc failed\n");
4645	5426	goto out;
4646	5427	}
4647	5428	}
..	..	@@ -4650,29 +5431,27 @@
4650	5431	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
4651	5432	sizeof(struct request_tracker), GFP_KERNEL);
4652	5433	if (!ioc->hpr_lookup) {
4653		- pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
4654		- ioc->name);
	5434	+ ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
4655	5435	goto out;
4656	5436	}
4657	5437	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
4658		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4659		- "hi_priority(0x%p): depth(%d), start smid(%d)\n",
4660		- ioc->name, ioc->hi_priority,
4661		- ioc->hi_priority_depth, ioc->hi_priority_smid));
	5438	+ dinitprintk(ioc,
	5439	+ ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
	5440	+ ioc->hi_priority,
	5441	+ ioc->hi_priority_depth, ioc->hi_priority_smid));
4662	5442
4663	5443	/* initialize internal queue smid's */
4664	5444	ioc->internal_lookup = kcalloc(ioc->internal_depth,
4665	5445	sizeof(struct request_tracker), GFP_KERNEL);
4666	5446	if (!ioc->internal_lookup) {
4667		- pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
4668		- ioc->name);
	5447	+ ioc_err(ioc, "internal_lookup: kcalloc failed\n");
4669	5448	goto out;
4670	5449	}
4671	5450	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
4672		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4673		- "internal(0x%p): depth(%d), start smid(%d)\n",
4674		- ioc->name, ioc->internal,
4675		- ioc->internal_depth, ioc->internal_smid));
	5451	+ dinitprintk(ioc,
	5452	+ ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
	5453	+ ioc->internal,
	5454	+ ioc->internal_depth, ioc->internal_smid));
4676	5455	/*
4677	5456	* The number of NVMe page sized blocks needed is:
4678	5457	* (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
..	..	@@ -4686,6 +5465,7 @@
4686	5465	* be required for NVMe PRP's, only each set of NVMe blocks will be
4687	5466	* contiguous, so a new set is allocated for each possible I/O.
4688	5467	*/
	5468	+
4689	5469	ioc->chains_per_prp_buffer = 0;
4690	5470	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4691	5471	nvme_blocks_needed =
..	..	@@ -4696,59 +5476,22 @@
4696	5476	sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
4697	5477	ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
4698	5478	if (!ioc->pcie_sg_lookup) {
4699		- pr_info(MPT3SAS_FMT
4700		- "PCIe SGL lookup: kzalloc failed\n", ioc->name);
	5479	+ ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
4701	5480	goto out;
4702	5481	}
4703	5482	sz = nvme_blocks_needed * ioc->page_size;
4704		- ioc->pcie_sgl_dma_pool =
4705		- dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
4706		- if (!ioc->pcie_sgl_dma_pool) {
4707		- pr_info(MPT3SAS_FMT
4708		- "PCIe SGL pool: dma_pool_create failed\n",
4709		- ioc->name);
4710		- goto out;
4711		- }
4712		-
4713		- ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
4714		- ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
4715		- ioc->chains_needed_per_io);
4716		-
4717		- for (i = 0; i < ioc->scsiio_depth; i++) {
4718		- ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
4719		- ioc->pcie_sgl_dma_pool, GFP_KERNEL,
4720		- &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
4721		- if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
4722		- pr_info(MPT3SAS_FMT
4723		- "PCIe SGL pool: dma_pool_alloc failed\n",
4724		- ioc->name);
4725		- goto out;
4726		- }
4727		- for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
4728		- ct = &ioc->chain_lookup[i].chains_per_smid[j];
4729		- ct->chain_buffer =
4730		- ioc->pcie_sg_lookup[i].pcie_sgl +
4731		- (j * ioc->chain_segment_sz);
4732		- ct->chain_buffer_dma =
4733		- ioc->pcie_sg_lookup[i].pcie_sgl_dma +
4734		- (j * ioc->chain_segment_sz);
4735		- }
4736		- }
4737		-
4738		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), "
4739		- "element_size(%d), pool_size(%d kB)\n", ioc->name,
4740		- ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
4741		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can "
4742		- "fit in a PRP page(%d)\n", ioc->name,
4743		- ioc->chains_per_prp_buffer));
	5483	+ rc = _base_allocate_pcie_sgl_pool(ioc, sz);
	5484	+ if (rc == -ENOMEM)
	5485	+ return -ENOMEM;
	5486	+ else if (rc == -EAGAIN)
	5487	+ goto try_32bit_dma;
4744	5488	total_sz += sz * ioc->scsiio_depth;
4745	5489	}
4746	5490
4747	5491	ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
4748	5492	ioc->chain_segment_sz, 16, 0);
4749	5493	if (!ioc->chain_dma_pool) {
4750		- pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n",
4751		- ioc->name);
	5494	+ ioc_err(ioc, "chain_dma_pool: dma_pool_create failed\n");
4752	5495	goto out;
4753	5496	}
4754	5497	for (i = 0; i < ioc->scsiio_depth; i++) {
..	..	@@ -4759,34 +5502,30 @@
4759	5502	ioc->chain_dma_pool, GFP_KERNEL,
4760	5503	&ct->chain_buffer_dma);
4761	5504	if (!ct->chain_buffer) {
4762		- pr_err(MPT3SAS_FMT "chain_lookup: "
4763		- " pci_pool_alloc failed\n", ioc->name);
4764		- _base_release_memory_pools(ioc);
	5505	+ ioc_err(ioc, "chain_lookup: pci_pool_alloc failed\n");
4765	5506	goto out;
4766	5507	}
4767	5508	}
4768	5509	total_sz += ioc->chain_segment_sz;
4769	5510	}
4770	5511
4771		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4772		- "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
4773		- ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
4774		- ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
	5512	+ dinitprintk(ioc,
	5513	+ ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5514	+ ioc->chain_depth, ioc->chain_segment_sz,
	5515	+ (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
4775	5516
4776	5517	/* sense buffers, 4 byte align */
4777	5518	sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
4778	5519	ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4779	5520	4, 0);
4780	5521	if (!ioc->sense_dma_pool) {
4781		- pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n",
4782		- ioc->name);
	5522	+ ioc_err(ioc, "sense pool: dma_pool_create failed\n");
4783	5523	goto out;
4784	5524	}
4785	5525	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4786	5526	&ioc->sense_dma);
4787	5527	if (!ioc->sense) {
4788		- pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n",
4789		- ioc->name);
	5528	+ ioc_err(ioc, "sense pool: dma_pool_alloc failed\n");
4790	5529	goto out;
4791	5530	}
4792	5531	/* sense buffer requires to be in same 4 gb region.
..	..	@@ -4798,7 +5537,7 @@
4798	5537	* Actual requirement is not alignment, but we need start and end of
4799	5538	* DMA address must have same upper 32 bit address.
4800	5539	*/
4801		- if (!is_MSB_are_same((long)ioc->sense, sz)) {
	5540	+ if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
4802	5541	//Release Sense pool & Reallocate
4803	5542	dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4804	5543	dma_pool_destroy(ioc->sense_dma_pool);
..	..	@@ -4808,24 +5547,22 @@
4808	5547	dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4809	5548	roundup_pow_of_two(sz), 0);
4810	5549	if (!ioc->sense_dma_pool) {
4811		- pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
4812		- ioc->name);
	5550	+ ioc_err(ioc, "sense pool: pci_pool_create failed\n");
4813	5551	goto out;
4814	5552	}
4815	5553	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4816	5554	&ioc->sense_dma);
4817	5555	if (!ioc->sense) {
4818		- pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
4819		- ioc->name);
	5556	+ ioc_err(ioc, "sense pool: pci_pool_alloc failed\n");
4820	5557	goto out;
4821	5558	}
4822	5559	}
4823		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4824		- "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
4825		- "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
4826		- SCSI_SENSE_BUFFERSIZE, sz/1024));
4827		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
4828		- ioc->name, (unsigned long long)ioc->sense_dma));
	5560	+ ioc_info(ioc,
	5561	+ "sense pool(0x%p)- dma(0x%llx): depth(%d),"
	5562	+ "element_size(%d), pool_size(%d kB)\n",
	5563	+ ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
	5564	+ SCSI_SENSE_BUFFERSIZE, sz / 1024);
	5565	+
4829	5566	total_sz += sz;
4830	5567
4831	5568	/* reply pool, 4 byte align */
..	..	@@ -4833,25 +5570,24 @@
4833	5570	ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
4834	5571	4, 0);
4835	5572	if (!ioc->reply_dma_pool) {
4836		- pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n",
4837		- ioc->name);
	5573	+ ioc_err(ioc, "reply pool: dma_pool_create failed\n");
4838	5574	goto out;
4839	5575	}
4840	5576	ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
4841	5577	&ioc->reply_dma);
4842	5578	if (!ioc->reply) {
4843		- pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n",
4844		- ioc->name);
	5579	+ ioc_err(ioc, "reply pool: dma_pool_alloc failed\n");
4845	5580	goto out;
4846	5581	}
4847	5582	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
4848	5583	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
4849		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4850		- "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4851		- ioc->name, ioc->reply,
4852		- ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
4853		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
4854		- ioc->name, (unsigned long long)ioc->reply_dma));
	5584	+ dinitprintk(ioc,
	5585	+ ioc_info(ioc, "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5586	+ ioc->reply, ioc->reply_free_queue_depth,
	5587	+ ioc->reply_sz, sz / 1024));
	5588	+ dinitprintk(ioc,
	5589	+ ioc_info(ioc, "reply_dma(0x%llx)\n",
	5590	+ (unsigned long long)ioc->reply_dma));
4855	5591	total_sz += sz;
4856	5592
4857	5593	/* reply free queue, 16 byte align */
..	..	@@ -4859,24 +5595,22 @@
4859	5595	ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
4860	5596	&ioc->pdev->dev, sz, 16, 0);
4861	5597	if (!ioc->reply_free_dma_pool) {
4862		- pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n",
4863		- ioc->name);
	5598	+ ioc_err(ioc, "reply_free pool: dma_pool_create failed\n");
4864	5599	goto out;
4865	5600	}
4866		- ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL,
	5601	+ ioc->reply_free = dma_pool_zalloc(ioc->reply_free_dma_pool, GFP_KERNEL,
4867	5602	&ioc->reply_free_dma);
4868	5603	if (!ioc->reply_free) {
4869		- pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n",
4870		- ioc->name);
	5604	+ ioc_err(ioc, "reply_free pool: dma_pool_alloc failed\n");
4871	5605	goto out;
4872	5606	}
4873		- memset(ioc->reply_free, 0, sz);
4874		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
4875		- "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
4876		- ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
4877		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4878		- "reply_free_dma (0x%llx)\n",
4879		- ioc->name, (unsigned long long)ioc->reply_free_dma));
	5607	+ dinitprintk(ioc,
	5608	+ ioc_info(ioc, "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
	5609	+ ioc->reply_free, ioc->reply_free_queue_depth,
	5610	+ 4, sz / 1024));
	5611	+ dinitprintk(ioc,
	5612	+ ioc_info(ioc, "reply_free_dma (0x%llx)\n",
	5613	+ (unsigned long long)ioc->reply_free_dma));
4880	5614	total_sz += sz;
4881	5615
4882	5616	if (ioc->rdpq_array_enable) {
..	..	@@ -4887,8 +5621,7 @@
4887	5621	&ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
4888	5622	if (!ioc->reply_post_free_array_dma_pool) {
4889	5623	dinitprintk(ioc,
4890		- pr_info(MPT3SAS_FMT "reply_post_free_array pool: "
4891		- "dma_pool_create failed\n", ioc->name));
	5624	+ ioc_info(ioc, "reply_post_free_array pool: dma_pool_create failed\n"));
4892	5625	goto out;
4893	5626	}
4894	5627	ioc->reply_post_free_array =
..	..	@@ -4896,35 +5629,43 @@
4896	5629	GFP_KERNEL, &ioc->reply_post_free_array_dma);
4897	5630	if (!ioc->reply_post_free_array) {
4898	5631	dinitprintk(ioc,
4899		- pr_info(MPT3SAS_FMT "reply_post_free_array pool: "
4900		- "dma_pool_alloc failed\n", ioc->name));
	5632	+ ioc_info(ioc, "reply_post_free_array pool: dma_pool_alloc failed\n"));
4901	5633	goto out;
4902	5634	}
4903	5635	}
4904	5636	ioc->config_page_sz = 512;
4905		- ioc->config_page = pci_alloc_consistent(ioc->pdev,
4906		- ioc->config_page_sz, &ioc->config_page_dma);
	5637	+ ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
	5638	+ ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
4907	5639	if (!ioc->config_page) {
4908		- pr_err(MPT3SAS_FMT
4909		- "config page: dma_pool_alloc failed\n",
4910		- ioc->name);
	5640	+ ioc_err(ioc, "config page: dma_pool_alloc failed\n");
4911	5641	goto out;
4912	5642	}
4913		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4914		- "config page(0x%p): size(%d)\n",
4915		- ioc->name, ioc->config_page, ioc->config_page_sz));
4916		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
4917		- ioc->name, (unsigned long long)ioc->config_page_dma));
	5643	+
	5644	+ ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
	5645	+ ioc->config_page, (unsigned long long)ioc->config_page_dma,
	5646	+ ioc->config_page_sz);
4918	5647	total_sz += ioc->config_page_sz;
4919	5648
4920		- pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
4921		- ioc->name, total_sz/1024);
4922		- pr_info(MPT3SAS_FMT
4923		- "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
4924		- ioc->name, ioc->shost->can_queue, facts->RequestCredit);
4925		- pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
4926		- ioc->name, ioc->shost->sg_tablesize);
	5649	+ ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
	5650	+ total_sz / 1024);
	5651	+ ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
	5652	+ ioc->shost->can_queue, facts->RequestCredit);
	5653	+ ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
	5654	+ ioc->shost->sg_tablesize);
4927	5655	return 0;
	5656	+
	5657	+try_32bit_dma:
	5658	+ _base_release_memory_pools(ioc);
	5659	+ if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
	5660	+ /* Change dma coherent mask to 32 bit and reallocate */
	5661	+ if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
	5662	+ pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
	5663	+ pci_name(ioc->pdev));
	5664	+ return -ENODEV;
	5665	+ }
	5666	+ } else if (_base_reduce_hba_queue_depth(ioc) != 0)
	5667	+ return -ENOMEM;
	5668	+ goto retry_allocation;
4928	5669
4929	5670	out:
4930	5671	return -ENOMEM;
..	..	@@ -4943,7 +5684,7 @@
4943	5684	{
4944	5685	u32 s, sc;
4945	5686
4946		- s = readl(&ioc->chip->Doorbell);
	5687	+ s = ioc->base_readl_ext_retry(&ioc->chip->Doorbell);
4947	5688	sc = s & MPI2_IOC_STATE_MASK;
4948	5689	return cooked ? sc : s;
4949	5690	}
..	..	@@ -4970,6 +5711,8 @@
4970	5711	return 0;
4971	5712	if (count && current_state == MPI2_IOC_STATE_FAULT)
4972	5713	break;
	5714	+ if (count && current_state == MPI2_IOC_STATE_COREDUMP)
	5715	+ break;
4973	5716
4974	5717	usleep_range(1000, 1500);
4975	5718	count++;
..	..	@@ -4979,16 +5722,32 @@
4979	5722	}
4980	5723
4981	5724	/**
	5725	+ * _base_dump_reg_set - This function will print hexdump of register set.
	5726	+ * @ioc: per adapter object
	5727	+ *
	5728	+ * Returns nothing.
	5729	+ */
	5730	+static inline void
	5731	+_base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
	5732	+{
	5733	+ unsigned int i, sz = 256;
	5734	+ u32 __iomem reg = (u32 __iomem )ioc->chip;
	5735	+
	5736	+ ioc_info(ioc, "System Register set:\n");
	5737	+ for (i = 0; i < (sz / sizeof(u32)); i++)
	5738	+ pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
	5739	+}
	5740	+
	5741	+/**
4982	5742	* _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
4983	5743	* a write to the doorbell)
4984	5744	* @ioc: per adapter object
	5745	+ * @timeout: timeout in seconds
4985	5746	*
4986	5747	* Return: 0 for success, non-zero for failure.
4987	5748	*
4988	5749	* Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
4989	5750	*/
4990		-static int
4991		-_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4992	5751
4993	5752	static int
4994	5753	_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
..	..	@@ -4999,11 +5758,11 @@
4999	5758	count = 0;
5000	5759	cntdn = 1000 * timeout;
5001	5760	do {
5002		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5761	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5003	5762	if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5004		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5005		- "%s: successful count(%d), timeout(%d)\n",
5006		- ioc->name, __func__, count, timeout));
	5763	+ dhsprintk(ioc,
	5764	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5765	+ __func__, count, timeout));
5007	5766	return 0;
5008	5767	}
5009	5768
..	..	@@ -5011,9 +5770,8 @@
5011	5770	count++;
5012	5771	} while (--cntdn);
5013	5772
5014		- pr_err(MPT3SAS_FMT
5015		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5016		- ioc->name, __func__, count, int_status);
	5773	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5774	+ __func__, count, int_status);
5017	5775	return -EFAULT;
5018	5776	}
5019	5777
..	..	@@ -5026,11 +5784,11 @@
5026	5784	count = 0;
5027	5785	cntdn = 2000 * timeout;
5028	5786	do {
5029		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5787	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5030	5788	if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5031		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5032		- "%s: successful count(%d), timeout(%d)\n",
5033		- ioc->name, __func__, count, timeout));
	5789	+ dhsprintk(ioc,
	5790	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5791	+ __func__, count, timeout));
5034	5792	return 0;
5035	5793	}
5036	5794
..	..	@@ -5038,9 +5796,8 @@
5038	5796	count++;
5039	5797	} while (--cntdn);
5040	5798
5041		- pr_err(MPT3SAS_FMT
5042		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5043		- ioc->name, __func__, count, int_status);
	5799	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5800	+ __func__, count, int_status);
5044	5801	return -EFAULT;
5045	5802
5046	5803	}
..	..	@@ -5065,17 +5822,22 @@
5065	5822	count = 0;
5066	5823	cntdn = 1000 * timeout;
5067	5824	do {
5068		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5825	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5069	5826	if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
5070		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5071		- "%s: successful count(%d), timeout(%d)\n",
5072		- ioc->name, __func__, count, timeout));
	5827	+ dhsprintk(ioc,
	5828	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5829	+ __func__, count, timeout));
5073	5830	return 0;
5074	5831	} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5075		- doorbell = readl(&ioc->chip->Doorbell);
	5832	+ doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell);
5076	5833	if ((doorbell & MPI2_IOC_STATE_MASK) ==
5077	5834	MPI2_IOC_STATE_FAULT) {
5078		- mpt3sas_base_fault_info(ioc , doorbell);
	5835	+ mpt3sas_print_fault_code(ioc, doorbell);
	5836	+ return -EFAULT;
	5837	+ }
	5838	+ if ((doorbell & MPI2_IOC_STATE_MASK) ==
	5839	+ MPI2_IOC_STATE_COREDUMP) {
	5840	+ mpt3sas_print_coredump_info(ioc, doorbell);
5079	5841	return -EFAULT;
5080	5842	}
5081	5843	} else if (int_status == 0xFFFFFFFF)
..	..	@@ -5086,9 +5848,8 @@
5086	5848	} while (--cntdn);
5087	5849
5088	5850	out:
5089		- pr_err(MPT3SAS_FMT
5090		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5091		- ioc->name, __func__, count, int_status);
	5851	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5852	+ __func__, count, int_status);
5092	5853	return -EFAULT;
5093	5854	}
5094	5855
..	..	@@ -5108,11 +5869,11 @@
5108	5869	count = 0;
5109	5870	cntdn = 1000 * timeout;
5110	5871	do {
5111		- doorbell_reg = readl(&ioc->chip->Doorbell);
	5872	+ doorbell_reg = ioc->base_readl_ext_retry(&ioc->chip->Doorbell);
5112	5873	if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
5113		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5114		- "%s: successful count(%d), timeout(%d)\n",
5115		- ioc->name, __func__, count, timeout));
	5874	+ dhsprintk(ioc,
	5875	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5876	+ __func__, count, timeout));
5116	5877	return 0;
5117	5878	}
5118	5879
..	..	@@ -5120,9 +5881,8 @@
5120	5881	count++;
5121	5882	} while (--cntdn);
5122	5883
5123		- pr_err(MPT3SAS_FMT
5124		- "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
5125		- ioc->name, __func__, count, doorbell_reg);
	5884	+ ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
	5885	+ __func__, count, doorbell_reg);
5126	5886	return -EFAULT;
5127	5887	}
5128	5888
..	..	@@ -5139,10 +5899,10 @@
5139	5899	{
5140	5900	u32 ioc_state;
5141	5901	int r = 0;
	5902	+ unsigned long flags;
5142	5903
5143	5904	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
5144		- pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
5145		- ioc->name, __func__);
	5905	+ ioc_err(ioc, "%s: unknown reset_type\n", __func__);
5146	5906	return -EFAULT;
5147	5907	}
5148	5908
..	..	@@ -5150,7 +5910,7 @@
5150	5910	MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
5151	5911	return -EFAULT;
5152	5912
5153		- pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
	5913	+ ioc_info(ioc, "sending message unit reset !!\n");
5154	5914
5155	5915	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
5156	5916	&ioc->chip->Doorbell);
..	..	@@ -5158,18 +5918,71 @@
5158	5918	r = -EFAULT;
5159	5919	goto out;
5160	5920	}
	5921	+
5161	5922	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5162	5923	if (ioc_state) {
5163		- pr_err(MPT3SAS_FMT
5164		- "%s: failed going to ready state (ioc_state=0x%x)\n",
5165		- ioc->name, __func__, ioc_state);
	5924	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	5925	+ __func__, ioc_state);
5166	5926	r = -EFAULT;
5167	5927	goto out;
5168	5928	}
5169	5929	out:
5170		- pr_info(MPT3SAS_FMT "message unit reset: %s\n",
5171		- ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
	5930	+ if (r != 0) {
	5931	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
	5932	+ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
	5933	+ /*
	5934	+ * Wait for IOC state CoreDump to clear only during
	5935	+ * HBA initialization & release time.
	5936	+ */
	5937	+ if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	5938	+ MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 \|\|
	5939	+ ioc->fault_reset_work_q == NULL)) {
	5940	+ spin_unlock_irqrestore(
	5941	+ &ioc->ioc_reset_in_progress_lock, flags);
	5942	+ mpt3sas_print_coredump_info(ioc, ioc_state);
	5943	+ mpt3sas_base_wait_for_coredump_completion(ioc,
	5944	+ __func__);
	5945	+ spin_lock_irqsave(
	5946	+ &ioc->ioc_reset_in_progress_lock, flags);
	5947	+ }
	5948	+ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
	5949	+ }
	5950	+ ioc_info(ioc, "message unit reset: %s\n",
	5951	+ r == 0 ? "SUCCESS" : "FAILED");
5172	5952	return r;
	5953	+}
	5954	+
	5955	+/**
	5956	+ * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
	5957	+ * @ioc: per adapter object
	5958	+ * @timeout: timeout in seconds
	5959	+ *
	5960	+ * Return: Waits up to timeout seconds for the IOC to
	5961	+ * become operational. Returns 0 if IOC is present
	5962	+ * and operational; otherwise returns -EFAULT.
	5963	+ */
	5964	+
	5965	+int
	5966	+mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
	5967	+{
	5968	+ int wait_state_count = 0;
	5969	+ u32 ioc_state;
	5970	+
	5971	+ do {
	5972	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
	5973	+ if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
	5974	+ break;
	5975	+ ssleep(1);
	5976	+ ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
	5977	+ __func__, ++wait_state_count);
	5978	+ } while (--timeout);
	5979	+ if (!timeout) {
	5980	+ ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
	5981	+ return -EFAULT;
	5982	+ }
	5983	+ if (wait_state_count)
	5984	+ ioc_info(ioc, "ioc is operational\n");
	5985	+ return 0;
5173	5986	}
5174	5987
5175	5988	/**
..	..	@@ -5193,15 +6006,13 @@
5193	6006	__le32 *mfp;
5194	6007
5195	6008	/* make sure doorbell is not in use */
5196		- if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
5197		- pr_err(MPT3SAS_FMT
5198		- "doorbell is in use (line=%d)\n",
5199		- ioc->name, __LINE__);
	6009	+ if ((ioc->base_readl_ext_retry(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
	6010	+ ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
5200	6011	return -EFAULT;
5201	6012	}
5202	6013
5203	6014	/* clear pending doorbell interrupts from previous state changes */
5204		- if (readl(&ioc->chip->HostInterruptStatus) &
	6015	+ if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
5205	6016	MPI2_HIS_IOC2SYS_DB_STATUS)
5206	6017	writel(0, &ioc->chip->HostInterruptStatus);
5207	6018
..	..	@@ -5211,17 +6022,15 @@
5211	6022	&ioc->chip->Doorbell);
5212	6023
5213	6024	if ((_base_spin_on_doorbell_int(ioc, 5))) {
5214		- pr_err(MPT3SAS_FMT
5215		- "doorbell handshake int failed (line=%d)\n",
5216		- ioc->name, __LINE__);
	6025	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6026	+ __LINE__);
5217	6027	return -EFAULT;
5218	6028	}
5219	6029	writel(0, &ioc->chip->HostInterruptStatus);
5220	6030
5221	6031	if ((_base_wait_for_doorbell_ack(ioc, 5))) {
5222		- pr_err(MPT3SAS_FMT
5223		- "doorbell handshake ack failed (line=%d)\n",
5224		- ioc->name, __LINE__);
	6032	+ ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
	6033	+ __LINE__);
5225	6034	return -EFAULT;
5226	6035	}
5227	6036
..	..	@@ -5233,53 +6042,51 @@
5233	6042	}
5234	6043
5235	6044	if (failed) {
5236		- pr_err(MPT3SAS_FMT
5237		- "doorbell handshake sending request failed (line=%d)\n",
5238		- ioc->name, __LINE__);
	6045	+ ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
	6046	+ __LINE__);
5239	6047	return -EFAULT;
5240	6048	}
5241	6049
5242	6050	/* now wait for the reply */
5243	6051	if ((_base_wait_for_doorbell_int(ioc, timeout))) {
5244		- pr_err(MPT3SAS_FMT
5245		- "doorbell handshake int failed (line=%d)\n",
5246		- ioc->name, __LINE__);
	6052	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6053	+ __LINE__);
5247	6054	return -EFAULT;
5248	6055	}
5249	6056
5250	6057	/* read the first two 16-bits, it gives the total length of the reply */
5251		- reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6058	+ reply[0] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell)
5252	6059	& MPI2_DOORBELL_DATA_MASK);
5253	6060	writel(0, &ioc->chip->HostInterruptStatus);
5254	6061	if ((_base_wait_for_doorbell_int(ioc, 5))) {
5255		- pr_err(MPT3SAS_FMT
5256		- "doorbell handshake int failed (line=%d)\n",
5257		- ioc->name, __LINE__);
	6062	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6063	+ __LINE__);
5258	6064	return -EFAULT;
5259	6065	}
5260		- reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6066	+ reply[1] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell)
5261	6067	& MPI2_DOORBELL_DATA_MASK);
5262	6068	writel(0, &ioc->chip->HostInterruptStatus);
5263	6069
5264	6070	for (i = 2; i < default_reply->MsgLength * 2; i++) {
5265	6071	if ((_base_wait_for_doorbell_int(ioc, 5))) {
5266		- pr_err(MPT3SAS_FMT
5267		- "doorbell handshake int failed (line=%d)\n",
5268		- ioc->name, __LINE__);
	6072	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6073	+ __LINE__);
5269	6074	return -EFAULT;
5270	6075	}
5271	6076	if (i >= reply_bytes/2) /* overflow case */
5272		- readl(&ioc->chip->Doorbell);
	6077	+ ioc->base_readl_ext_retry(&ioc->chip->Doorbell);
5273	6078	else
5274		- reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6079	+ reply[i] = le16_to_cpu(
	6080	+ ioc->base_readl_ext_retry(&ioc->chip->Doorbell)
5275	6081	& MPI2_DOORBELL_DATA_MASK);
5276	6082	writel(0, &ioc->chip->HostInterruptStatus);
5277	6083	}
5278	6084
5279	6085	_base_wait_for_doorbell_int(ioc, 5);
5280	6086	if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
5281		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5282		- "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
	6087	+ dhsprintk(ioc,
	6088	+ ioc_info(ioc, "doorbell is in use (line=%d)\n",
	6089	+ __LINE__));
5283	6090	}
5284	6091	writel(0, &ioc->chip->HostInterruptStatus);
5285	6092
..	..	@@ -5287,7 +6094,7 @@
5287	6094	mfp = (__le32 *)reply;
5288	6095	pr_info("\toffset:data\n");
5289	6096	for (i = 0; i < reply_bytes/4; i++)
5290		- pr_info("\t[0x%02x]:%08x\n", i*4,
	6097	+ ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
5291	6098	le32_to_cpu(mfp[i]));
5292	6099	}
5293	6100	return 0;
..	..	@@ -5313,45 +6120,27 @@
5313	6120	Mpi2SasIoUnitControlRequest_t *mpi_request)
5314	6121	{
5315	6122	u16 smid;
5316		- u32 ioc_state;
5317	6123	u8 issue_reset = 0;
5318	6124	int rc;
5319	6125	void *request;
5320		- u16 wait_state_count;
5321	6126
5322		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5323		- __func__));
	6127	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5324	6128
5325	6129	mutex_lock(&ioc->base_cmds.mutex);
5326	6130
5327	6131	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5328		- pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
5329		- ioc->name, __func__);
	6132	+ ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5330	6133	rc = -EAGAIN;
5331	6134	goto out;
5332	6135	}
5333	6136
5334		- wait_state_count = 0;
5335		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5336		- while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
5337		- if (wait_state_count++ == 10) {
5338		- pr_err(MPT3SAS_FMT
5339		- "%s: failed due to ioc not operational\n",
5340		- ioc->name, __func__);
5341		- rc = -EFAULT;
5342		- goto out;
5343		- }
5344		- ssleep(1);
5345		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5346		- pr_info(MPT3SAS_FMT
5347		- "%s: waiting for operational state(count=%d)\n",
5348		- ioc->name, __func__, wait_state_count);
5349		- }
	6137	+ rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
	6138	+ if (rc)
	6139	+ goto out;
5350	6140
5351	6141	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5352	6142	if (!smid) {
5353		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5354		- ioc->name, __func__);
	6143	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5355	6144	rc = -EAGAIN;
5356	6145	goto out;
5357	6146	}
..	..	@@ -5365,7 +6154,7 @@
5365	6154	mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
5366	6155	ioc->ioc_link_reset_in_progress = 1;
5367	6156	init_completion(&ioc->base_cmds.done);
5368		- mpt3sas_base_put_smid_default(ioc, smid);
	6157	+ ioc->put_smid_default(ioc, smid);
5369	6158	wait_for_completion_timeout(&ioc->base_cmds.done,
5370	6159	msecs_to_jiffies(10000));
5371	6160	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET \|\|
..	..	@@ -5373,10 +6162,9 @@
5373	6162	ioc->ioc_link_reset_in_progress)
5374	6163	ioc->ioc_link_reset_in_progress = 0;
5375	6164	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5376		- issue_reset =
5377		- mpt3sas_base_check_cmd_timeout(ioc,
5378		- ioc->base_cmds.status, mpi_request,
5379		- sizeof(Mpi2SasIoUnitControlRequest_t)/4);
	6165	+ mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
	6166	+ mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
	6167	+ issue_reset);
5380	6168	goto issue_host_reset;
5381	6169	}
5382	6170	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
..	..	@@ -5413,46 +6201,27 @@
5413	6201	Mpi2SepReply_t mpi_reply, Mpi2SepRequest_t mpi_request)
5414	6202	{
5415	6203	u16 smid;
5416		- u32 ioc_state;
5417	6204	u8 issue_reset = 0;
5418	6205	int rc;
5419	6206	void *request;
5420		- u16 wait_state_count;
5421	6207
5422		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5423		- __func__));
	6208	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5424	6209
5425	6210	mutex_lock(&ioc->base_cmds.mutex);
5426	6211
5427	6212	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5428		- pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
5429		- ioc->name, __func__);
	6213	+ ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5430	6214	rc = -EAGAIN;
5431	6215	goto out;
5432	6216	}
5433	6217
5434		- wait_state_count = 0;
5435		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5436		- while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
5437		- if (wait_state_count++ == 10) {
5438		- pr_err(MPT3SAS_FMT
5439		- "%s: failed due to ioc not operational\n",
5440		- ioc->name, __func__);
5441		- rc = -EFAULT;
5442		- goto out;
5443		- }
5444		- ssleep(1);
5445		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5446		- pr_info(MPT3SAS_FMT
5447		- "%s: waiting for operational state(count=%d)\n",
5448		- ioc->name,
5449		- __func__, wait_state_count);
5450		- }
	6218	+ rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
	6219	+ if (rc)
	6220	+ goto out;
5451	6221
5452	6222	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5453	6223	if (!smid) {
5454		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5455		- ioc->name, __func__);
	6224	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5456	6225	rc = -EAGAIN;
5457	6226	goto out;
5458	6227	}
..	..	@@ -5461,16 +6230,16 @@
5461	6230	ioc->base_cmds.status = MPT3_CMD_PENDING;
5462	6231	request = mpt3sas_base_get_msg_frame(ioc, smid);
5463	6232	ioc->base_cmds.smid = smid;
	6233	+ memset(request, 0, ioc->request_sz);
5464	6234	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
5465	6235	init_completion(&ioc->base_cmds.done);
5466		- mpt3sas_base_put_smid_default(ioc, smid);
	6236	+ ioc->put_smid_default(ioc, smid);
5467	6237	wait_for_completion_timeout(&ioc->base_cmds.done,
5468	6238	msecs_to_jiffies(10000));
5469	6239	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5470		- issue_reset =
5471		- mpt3sas_base_check_cmd_timeout(ioc,
5472		- ioc->base_cmds.status, mpi_request,
5473		- sizeof(Mpi2SepRequest_t)/4);
	6240	+ mpt3sas_check_cmd_timeout(ioc,
	6241	+ ioc->base_cmds.status, mpi_request,
	6242	+ sizeof(Mpi2SepRequest_t)/4, issue_reset);
5474	6243	goto issue_host_reset;
5475	6244	}
5476	6245	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
..	..	@@ -5506,8 +6275,7 @@
5506	6275	struct mpt3sas_port_facts *pfacts;
5507	6276	int mpi_reply_sz, mpi_request_sz, r;
5508	6277
5509		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5510		- __func__));
	6278	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5511	6279
5512	6280	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
5513	6281	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
..	..	@@ -5518,8 +6286,7 @@
5518	6286	(u32 )&mpi_request, mpi_reply_sz, (u16 )&mpi_reply, 5);
5519	6287
5520	6288	if (r != 0) {
5521		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5522		- ioc->name, __func__, r);
	6289	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5523	6290	return r;
5524	6291	}
5525	6292
..	..	@@ -5547,40 +6314,46 @@
5547	6314	u32 ioc_state;
5548	6315	int rc;
5549	6316
5550		- dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
5551		- __func__));
	6317	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5552	6318
5553	6319	if (ioc->pci_error_recovery) {
5554		- dfailprintk(ioc, printk(MPT3SAS_FMT
5555		- "%s: host in pci error recovery\n", ioc->name, __func__));
	6320	+ dfailprintk(ioc,
	6321	+ ioc_info(ioc, "%s: host in pci error recovery\n",
	6322	+ __func__));
5556	6323	return -EFAULT;
5557	6324	}
5558	6325
5559	6326	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5560		- dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
5561		- ioc->name, __func__, ioc_state));
	6327	+ dhsprintk(ioc,
	6328	+ ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
	6329	+ __func__, ioc_state));
5562	6330
5563	6331	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) \|\|
5564	6332	(ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5565	6333	return 0;
5566	6334
5567	6335	if (ioc_state & MPI2_DOORBELL_USED) {
5568		- dhsprintk(ioc, printk(MPT3SAS_FMT
5569		- "unexpected doorbell active!\n", ioc->name));
	6336	+ dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
5570	6337	goto issue_diag_reset;
5571	6338	}
5572	6339
5573	6340	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5574		- mpt3sas_base_fault_info(ioc, ioc_state &
	6341	+ mpt3sas_print_fault_code(ioc, ioc_state &
5575	6342	MPI2_DOORBELL_DATA_MASK);
5576	6343	goto issue_diag_reset;
	6344	+ } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	6345	+ MPI2_IOC_STATE_COREDUMP) {
	6346	+ ioc_info(ioc,
	6347	+ "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
	6348	+ __func__, ioc_state);
	6349	+ return -EFAULT;
5577	6350	}
5578	6351
5579	6352	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5580	6353	if (ioc_state) {
5581		- dfailprintk(ioc, printk(MPT3SAS_FMT
5582		- "%s: failed going to ready state (ioc_state=0x%x)\n",
5583		- ioc->name, __func__, ioc_state));
	6354	+ dfailprintk(ioc,
	6355	+ ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	6356	+ __func__, ioc_state));
5584	6357	return -EFAULT;
5585	6358	}
5586	6359
..	..	@@ -5603,14 +6376,13 @@
5603	6376	struct mpt3sas_facts *facts;
5604	6377	int mpi_reply_sz, mpi_request_sz, r;
5605	6378
5606		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5607		- __func__));
	6379	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5608	6380
5609	6381	r = _base_wait_for_iocstate(ioc, 10);
5610	6382	if (r) {
5611		- dfailprintk(ioc, printk(MPT3SAS_FMT
5612		- "%s: failed getting to correct state\n",
5613		- ioc->name, __func__));
	6383	+ dfailprintk(ioc,
	6384	+ ioc_info(ioc, "%s: failed getting to correct state\n",
	6385	+ __func__));
5614	6386	return r;
5615	6387	}
5616	6388	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
..	..	@@ -5621,8 +6393,7 @@
5621	6393	(u32 )&mpi_request, mpi_reply_sz, (u16 )&mpi_reply, 5);
5622	6394
5623	6395	if (r != 0) {
5624		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5625		- ioc->name, __func__, r);
	6396	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5626	6397	return r;
5627	6398	}
5628	6399
..	..	@@ -5650,6 +6421,9 @@
5650	6421	if ((facts->IOCCapabilities &
5651	6422	MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
5652	6423	ioc->rdpq_array_capable = 1;
	6424	+ if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
	6425	+ && ioc->is_aero_ioc)
	6426	+ ioc->atomic_desc_capable = 1;
5653	6427	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
5654	6428	facts->IOCRequestFrameSize =
5655	6429	le16_to_cpu(mpi_reply.IOCRequestFrameSize);
..	..	@@ -5674,20 +6448,20 @@
5674	6448	*/
5675	6449	ioc->page_size = 1 << facts->CurrentHostPageSize;
5676	6450	if (ioc->page_size == 1) {
5677		- pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting "
5678		- "default host page size to 4k\n", ioc->name);
	6451	+ ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
5679	6452	ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
5680	6453	}
5681		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n",
5682		- ioc->name, facts->CurrentHostPageSize));
	6454	+ dinitprintk(ioc,
	6455	+ ioc_info(ioc, "CurrentHostPageSize(%d)\n",
	6456	+ facts->CurrentHostPageSize));
5683	6457
5684		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
5685		- "hba queue depth(%d), max chains per io(%d)\n",
5686		- ioc->name, facts->RequestCredit,
5687		- facts->MaxChainDepth));
5688		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
5689		- "request frame size(%d), reply frame size(%d)\n", ioc->name,
5690		- facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
	6458	+ dinitprintk(ioc,
	6459	+ ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
	6460	+ facts->RequestCredit, facts->MaxChainDepth));
	6461	+ dinitprintk(ioc,
	6462	+ ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
	6463	+ facts->IOCRequestFrameSize * 4,
	6464	+ facts->ReplyFrameSize * 4));
5691	6465	return 0;
5692	6466	}
5693	6467
..	..	@@ -5707,8 +6481,7 @@
5707	6481	u16 ioc_status;
5708	6482	u32 reply_post_free_array_sz = 0;
5709	6483
5710		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5711		- __func__));
	6484	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5712	6485
5713	6486	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
5714	6487	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
..	..	@@ -5752,6 +6525,12 @@
5752	6525	cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
5753	6526	}
5754	6527
	6528	+ /*
	6529	+ * Set the flag to enable CoreDump state feature in IOC firmware.
	6530	+ */
	6531	+ mpi_request.ConfigurationFlags \|=
	6532	+ cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
	6533	+
5755	6534	/* This time stamp specifies number of milliseconds
5756	6535	* since epoch ~ midnight January 1, 1970.
5757	6536	*/
..	..	@@ -5763,9 +6542,9 @@
5763	6542	int i;
5764	6543
5765	6544	mfp = (__le32 *)&mpi_request;
5766		- pr_info("\toffset:data\n");
	6545	+ ioc_info(ioc, "\toffset:data\n");
5767	6546	for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
5768		- pr_info("\t[0x%02x]:%08x\n", i*4,
	6547	+ ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
5769	6548	le32_to_cpu(mfp[i]));
5770	6549	}
5771	6550
..	..	@@ -5774,15 +6553,14 @@
5774	6553	sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
5775	6554
5776	6555	if (r != 0) {
5777		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5778		- ioc->name, __func__, r);
	6556	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5779	6557	return r;
5780	6558	}
5781	6559
5782	6560	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
5783	6561	if (ioc_status != MPI2_IOCSTATUS_SUCCESS \|\|
5784	6562	mpi_reply.IOCLogInfo) {
5785		- pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
	6563	+ ioc_err(ioc, "%s: failed\n", __func__);
5786	6564	r = -EIO;
5787	6565	}
5788	6566
..	..	@@ -5853,18 +6631,16 @@
5853	6631	u16 smid;
5854	6632	u16 ioc_status;
5855	6633
5856		- pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
	6634	+ ioc_info(ioc, "sending port enable !!\n");
5857	6635
5858	6636	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5859		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5860		- ioc->name, __func__);
	6637	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
5861	6638	return -EAGAIN;
5862	6639	}
5863	6640
5864	6641	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5865	6642	if (!smid) {
5866		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5867		- ioc->name, __func__);
	6643	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5868	6644	return -EAGAIN;
5869	6645	}
5870	6646
..	..	@@ -5875,11 +6651,10 @@
5875	6651	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5876	6652
5877	6653	init_completion(&ioc->port_enable_cmds.done);
5878		- mpt3sas_base_put_smid_default(ioc, smid);
	6654	+ ioc->put_smid_default(ioc, smid);
5879	6655	wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
5880	6656	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
5881		- pr_err(MPT3SAS_FMT "%s: timeout\n",
5882		- ioc->name, __func__);
	6657	+ ioc_err(ioc, "%s: timeout\n", __func__);
5883	6658	_debug_dump_mf(mpi_request,
5884	6659	sizeof(Mpi2PortEnableRequest_t)/4);
5885	6660	if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
..	..	@@ -5892,16 +6667,15 @@
5892	6667	mpi_reply = ioc->port_enable_cmds.reply;
5893	6668	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5894	6669	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5895		- pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
5896		- ioc->name, __func__, ioc_status);
	6670	+ ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
	6671	+ __func__, ioc_status);
5897	6672	r = -EFAULT;
5898	6673	goto out;
5899	6674	}
5900	6675
5901	6676	out:
5902	6677	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5903		- pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
5904		- "SUCCESS" : "FAILED"));
	6678	+ ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
5905	6679	return r;
5906	6680	}
5907	6681
..	..	@@ -5917,18 +6691,16 @@
5917	6691	Mpi2PortEnableRequest_t *mpi_request;
5918	6692	u16 smid;
5919	6693
5920		- pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
	6694	+ ioc_info(ioc, "sending port enable !!\n");
5921	6695
5922	6696	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5923		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5924		- ioc->name, __func__);
	6697	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
5925	6698	return -EAGAIN;
5926	6699	}
5927	6700
5928	6701	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5929	6702	if (!smid) {
5930		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5931		- ioc->name, __func__);
	6703	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5932	6704	return -EAGAIN;
5933	6705	}
5934	6706
..	..	@@ -5938,7 +6710,7 @@
5938	6710	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5939	6711	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5940	6712
5941		- mpt3sas_base_put_smid_default(ioc, smid);
	6713	+ ioc->put_smid_default(ioc, smid);
5942	6714	return 0;
5943	6715	}
5944	6716
..	..	@@ -6031,19 +6803,16 @@
6031	6803	int r = 0;
6032	6804	int i;
6033	6805
6034		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6035		- __func__));
	6806	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6036	6807
6037	6808	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
6038		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
6039		- ioc->name, __func__);
	6809	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
6040	6810	return -EAGAIN;
6041	6811	}
6042	6812
6043	6813	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
6044	6814	if (!smid) {
6045		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
6046		- ioc->name, __func__);
	6815	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
6047	6816	return -EAGAIN;
6048	6817	}
6049	6818	ioc->base_cmds.status = MPT3_CMD_PENDING;
..	..	@@ -6057,11 +6826,10 @@
6057	6826	mpi_request->EventMasks[i] =
6058	6827	cpu_to_le32(ioc->event_masks[i]);
6059	6828	init_completion(&ioc->base_cmds.done);
6060		- mpt3sas_base_put_smid_default(ioc, smid);
	6829	+ ioc->put_smid_default(ioc, smid);
6061	6830	wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
6062	6831	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
6063		- pr_err(MPT3SAS_FMT "%s: timeout\n",
6064		- ioc->name, __func__);
	6832	+ ioc_err(ioc, "%s: timeout\n", __func__);
6065	6833	_debug_dump_mf(mpi_request,
6066	6834	sizeof(Mpi2EventNotificationRequest_t)/4);
6067	6835	if (ioc->base_cmds.status & MPT3_CMD_RESET)
..	..	@@ -6069,8 +6837,7 @@
6069	6837	else
6070	6838	r = -ETIME;
6071	6839	} else
6072		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
6073		- ioc->name, __func__));
	6840	+ dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
6074	6841	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6075	6842	return r;
6076	6843	}
..	..	@@ -6126,18 +6893,18 @@
6126	6893	u32 count;
6127	6894	u32 hcb_size;
6128	6895
6129		- pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
	6896	+ ioc_info(ioc, "sending diag reset !!\n");
6130	6897
6131		- drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
6132		- ioc->name));
	6898	+ pci_cfg_access_lock(ioc->pdev);
	6899	+
	6900	+ drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
6133	6901
6134	6902	count = 0;
6135	6903	do {
6136	6904	/* Write magic sequence to WriteSequence register
6137	6905	* Loop until in diagnostic mode
6138	6906	*/
6139		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6140		- "write magic sequence\n", ioc->name));
	6907	+ drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
6141	6908	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6142	6909	writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
6143	6910	writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
..	..	@@ -6149,20 +6916,23 @@
6149	6916	/* wait 100 msec */
6150	6917	msleep(100);
6151	6918
6152		- if (count++ > 20)
	6919	+ if (count++ > 20) {
	6920	+ ioc_info(ioc,
	6921	+ "Stop writing magic sequence after 20 retries\n");
	6922	+ _base_dump_reg_set(ioc);
6153	6923	goto out;
	6924	+ }
6154	6925
6155		- host_diagnostic = readl(&ioc->chip->HostDiagnostic);
6156		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6157		- "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
6158		- ioc->name, count, host_diagnostic));
	6926	+ host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
	6927	+ drsprintk(ioc,
	6928	+ ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
	6929	+ count, host_diagnostic));
6159	6930
6160	6931	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
6161	6932
6162		- hcb_size = readl(&ioc->chip->HCBSize);
	6933	+ hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
6163	6934
6164		- drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
6165		- ioc->name));
	6935	+ drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
6166	6936	writel(host_diagnostic \| MPI2_DIAG_RESET_ADAPTER,
6167	6937	&ioc->chip->HostDiagnostic);
6168	6938
..	..	@@ -6173,10 +6943,14 @@
6173	6943	for (count = 0; count < (300000000 /
6174	6944	MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
6175	6945
6176		- host_diagnostic = readl(&ioc->chip->HostDiagnostic);
	6946	+ host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
6177	6947
6178		- if (host_diagnostic == 0xFFFFFFFF)
	6948	+ if (host_diagnostic == 0xFFFFFFFF) {
	6949	+ ioc_info(ioc,
	6950	+ "Invalid host diagnostic register value\n");
	6951	+ _base_dump_reg_set(ioc);
6179	6952	goto out;
	6953	+ }
6180	6954	if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
6181	6955	break;
6182	6956
..	..	@@ -6185,43 +6959,41 @@
6185	6959
6186	6960	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
6187	6961
6188		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6189		- "restart the adapter assuming the HCB Address points to good F/W\n",
6190		- ioc->name));
	6962	+ drsprintk(ioc,
	6963	+ ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
6191	6964	host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
6192	6965	host_diagnostic \|= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
6193	6966	writel(host_diagnostic, &ioc->chip->HostDiagnostic);
6194	6967
6195		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6196		- "re-enable the HCDW\n", ioc->name));
	6968	+ drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
6197	6969	writel(hcb_size \| MPI2_HCB_SIZE_HCB_ENABLE,
6198	6970	&ioc->chip->HCBSize);
6199	6971	}
6200	6972
6201		- drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
6202		- ioc->name));
	6973	+ drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
6203	6974	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
6204	6975	&ioc->chip->HostDiagnostic);
6205	6976
6206		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6207		- "disable writes to the diagnostic register\n", ioc->name));
	6977	+ drsprintk(ioc,
	6978	+ ioc_info(ioc, "disable writes to the diagnostic register\n"));
6208	6979	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6209	6980
6210		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6211		- "Wait for FW to go to the READY state\n", ioc->name));
	6981	+ drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
6212	6982	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
6213	6983	if (ioc_state) {
6214		- pr_err(MPT3SAS_FMT
6215		- "%s: failed going to ready state (ioc_state=0x%x)\n",
6216		- ioc->name, __func__, ioc_state);
	6984	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	6985	+ __func__, ioc_state);
	6986	+ _base_dump_reg_set(ioc);
6217	6987	goto out;
6218	6988	}
6219	6989
6220		- pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
	6990	+ pci_cfg_access_unlock(ioc->pdev);
	6991	+ ioc_info(ioc, "diag reset: SUCCESS\n");
6221	6992	return 0;
6222	6993
6223	6994	out:
6224		- pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
	6995	+ pci_cfg_access_unlock(ioc->pdev);
	6996	+ ioc_err(ioc, "diag reset: FAILED\n");
6225	6997	return -EFAULT;
6226	6998	}
6227	6999
..	..	@@ -6239,15 +7011,15 @@
6239	7011	int rc;
6240	7012	int count;
6241	7013
6242		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6243		- __func__));
	7014	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6244	7015
6245	7016	if (ioc->pci_error_recovery)
6246	7017	return 0;
6247	7018
6248	7019	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6249		- dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
6250		- ioc->name, __func__, ioc_state));
	7020	+ dhsprintk(ioc,
	7021	+ ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
	7022	+ __func__, ioc_state));
6251	7023
6252	7024	/* if in RESET state, it should move to READY state shortly */
6253	7025	count = 0;
..	..	@@ -6255,9 +7027,8 @@
6255	7027	while ((ioc_state & MPI2_IOC_STATE_MASK) !=
6256	7028	MPI2_IOC_STATE_READY) {
6257	7029	if (count++ == 10) {
6258		- pr_err(MPT3SAS_FMT
6259		- "%s: failed going to ready state (ioc_state=0x%x)\n",
6260		- ioc->name, __func__, ioc_state);
	7030	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	7031	+ __func__, ioc_state);
6261	7032	return -EFAULT;
6262	7033	}
6263	7034	ssleep(1);
..	..	@@ -6269,15 +7040,30 @@
6269	7040	return 0;
6270	7041
6271	7042	if (ioc_state & MPI2_DOORBELL_USED) {
6272		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
6273		- "unexpected doorbell active!\n",
6274		- ioc->name));
	7043	+ ioc_info(ioc, "unexpected doorbell active!\n");
6275	7044	goto issue_diag_reset;
6276	7045	}
6277	7046
6278	7047	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
6279		- mpt3sas_base_fault_info(ioc, ioc_state &
	7048	+ mpt3sas_print_fault_code(ioc, ioc_state &
6280	7049	MPI2_DOORBELL_DATA_MASK);
	7050	+ goto issue_diag_reset;
	7051	+ }
	7052	+
	7053	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
	7054	+ /*
	7055	+ * if host reset is invoked while watch dog thread is waiting
	7056	+ * for IOC state to be changed to Fault state then driver has
	7057	+ * to wait here for CoreDump state to clear otherwise reset
	7058	+ * will be issued to the FW and FW move the IOC state to
	7059	+ * reset state without copying the FW logs to coredump region.
	7060	+ */
	7061	+ if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
	7062	+ mpt3sas_print_coredump_info(ioc, ioc_state &
	7063	+ MPI2_DOORBELL_DATA_MASK);
	7064	+ mpt3sas_base_wait_for_coredump_completion(ioc,
	7065	+ __func__);
	7066	+ }
6281	7067	goto issue_diag_reset;
6282	7068	}
6283	7069
..	..	@@ -6304,7 +7090,7 @@
6304	7090	static int
6305	7091	_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
6306	7092	{
6307		- int r, i, index;
	7093	+ int r, i, index, rc;
6308	7094	unsigned long flags;
6309	7095	u32 reply_address;
6310	7096	u16 smid;
..	..	@@ -6315,8 +7101,7 @@
6315	7101	struct adapter_reply_queue *reply_q;
6316	7102	Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
6317	7103
6318		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6319		- __func__));
	7104	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6320	7105
6321	7106	/* clean the delayed target reset list */
6322	7107	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
..	..	@@ -6408,8 +7193,19 @@
6408	7193	skip_init_reply_post_free_queue:
6409	7194
6410	7195	r = _base_send_ioc_init(ioc);
6411		- if (r)
6412		- return r;
	7196	+ if (r) {
	7197	+ /*
	7198	+ * No need to check IOC state for fault state & issue
	7199	+ * diag reset during host reset. This check is need
	7200	+ * only during driver load time.
	7201	+ */
	7202	+ if (!ioc->is_driver_loading)
	7203	+ return r;
	7204	+
	7205	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7206	+ if (rc \|\| (_base_send_ioc_init(ioc)))
	7207	+ return r;
	7208	+ }
6413	7209
6414	7210	/* initialize reply free host index */
6415	7211	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
..	..	@@ -6432,7 +7228,7 @@
6432	7228
6433	7229	skip_init_reply_post_host_index:
6434	7230
6435		- _base_unmask_interrupts(ioc);
	7231	+ mpt3sas_base_unmask_interrupts(ioc);
6436	7232
6437	7233	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6438	7234	r = _base_display_fwpkg_version(ioc);
..	..	@@ -6476,13 +7272,12 @@
6476	7272	void
6477	7273	mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
6478	7274	{
6479		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6480		- __func__));
	7275	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6481	7276
6482	7277	/* synchronizing freeing resource with pci_access_mutex lock */
6483	7278	mutex_lock(&ioc->pci_access_mutex);
6484	7279	if (ioc->chip_phys && ioc->chip) {
6485		- _base_mask_interrupts(ioc);
	7280	+ mpt3sas_base_mask_interrupts(ioc);
6486	7281	ioc->shost_recovery = 1;
6487	7282	_base_make_ioc_ready(ioc, SOFT_RESET);
6488	7283	ioc->shost_recovery = 0;
..	..	@@ -6502,11 +7297,10 @@
6502	7297	int
6503	7298	mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
6504	7299	{
6505		- int r, i;
	7300	+ int r, i, rc;
6506	7301	int cpu_id, last_cpu_id = 0;
6507	7302
6508		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6509		- __func__));
	7303	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6510	7304
6511	7305	/* setup cpu_msix_table */
6512	7306	ioc->cpu_count = num_online_cpus();
..	..	@@ -6516,9 +7310,7 @@
6516	7310	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
6517	7311	ioc->reply_queue_count = 1;
6518	7312	if (!ioc->cpu_msix_table) {
6519		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
6520		- "allocation for cpu_msix_table failed!!!\n",
6521		- ioc->name));
	7313	+ ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
6522	7314	r = -ENOMEM;
6523	7315	goto out_free_resources;
6524	7316	}
..	..	@@ -6527,30 +7319,42 @@
6527	7319	ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
6528	7320	sizeof(resource_size_t *), GFP_KERNEL);
6529	7321	if (!ioc->reply_post_host_index) {
6530		- dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
6531		- "for reply_post_host_index failed!!!\n",
6532		- ioc->name));
	7322	+ ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
6533	7323	r = -ENOMEM;
6534	7324	goto out_free_resources;
6535	7325	}
6536	7326	}
6537	7327
	7328	+ ioc->smp_affinity_enable = smp_affinity_enable;
	7329	+
6538	7330	ioc->rdpq_array_enable_assigned = 0;
6539		- ioc->dma_mask = 0;
	7331	+ ioc->use_32bit_dma = false;
	7332	+ ioc->dma_mask = 64;
	7333	+ if (ioc->is_aero_ioc) {
	7334	+ ioc->base_readl = &_base_readl_aero;
	7335	+ ioc->base_readl_ext_retry = &_base_readl_ext_retry;
	7336	+ } else {
	7337	+ ioc->base_readl = &_base_readl;
	7338	+ ioc->base_readl_ext_retry = &_base_readl;
	7339	+ }
6540	7340	r = mpt3sas_base_map_resources(ioc);
6541	7341	if (r)
6542	7342	goto out_free_resources;
6543	7343
6544	7344	pci_set_drvdata(ioc->pdev, ioc->shost);
6545	7345	r = _base_get_ioc_facts(ioc);
6546		- if (r)
6547		- goto out_free_resources;
	7346	+ if (r) {
	7347	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7348	+ if (rc \|\| (_base_get_ioc_facts(ioc)))
	7349	+ goto out_free_resources;
	7350	+ }
6548	7351
6549	7352	switch (ioc->hba_mpi_version_belonged) {
6550	7353	case MPI2_VERSION:
6551	7354	ioc->build_sg_scmd = &_base_build_sg_scmd;
6552	7355	ioc->build_sg = &_base_build_sg;
6553	7356	ioc->build_zero_len_sge = &_base_build_zero_len_sge;
	7357	+ ioc->get_msix_index_for_smlio = &_base_get_msix_index;
6554	7358	break;
6555	7359	case MPI25_VERSION:
6556	7360	case MPI26_VERSION:
..	..	@@ -6565,15 +7369,30 @@
6565	7369	ioc->build_nvme_prp = &_base_build_nvme_prp;
6566	7370	ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
6567	7371	ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
6568		-
	7372	+ if (ioc->high_iops_queues)
	7373	+ ioc->get_msix_index_for_smlio =
	7374	+ &_base_get_high_iops_msix_index;
	7375	+ else
	7376	+ ioc->get_msix_index_for_smlio = &_base_get_msix_index;
6569	7377	break;
6570	7378	}
6571		-
6572		- if (ioc->is_mcpu_endpoint)
6573		- ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io;
6574		- else
6575		- ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
6576		-
	7379	+ if (ioc->atomic_desc_capable) {
	7380	+ ioc->put_smid_default = &_base_put_smid_default_atomic;
	7381	+ ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
	7382	+ ioc->put_smid_fast_path =
	7383	+ &_base_put_smid_fast_path_atomic;
	7384	+ ioc->put_smid_hi_priority =
	7385	+ &_base_put_smid_hi_priority_atomic;
	7386	+ } else {
	7387	+ ioc->put_smid_default = &_base_put_smid_default;
	7388	+ ioc->put_smid_fast_path = &_base_put_smid_fast_path;
	7389	+ ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
	7390	+ if (ioc->is_mcpu_endpoint)
	7391	+ ioc->put_smid_scsi_io =
	7392	+ &_base_put_smid_mpi_ep_scsi_io;
	7393	+ else
	7394	+ ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
	7395	+ }
6577	7396	/*
6578	7397	* These function pointers for other requests that don't
6579	7398	* the require IEEE scatter gather elements.
..	..	@@ -6596,14 +7415,23 @@
6596	7415
6597	7416	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
6598	7417	r = _base_get_port_facts(ioc, i);
6599		- if (r)
6600		- goto out_free_resources;
	7418	+ if (r) {
	7419	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7420	+ if (rc \|\| (_base_get_port_facts(ioc, i)))
	7421	+ goto out_free_resources;
	7422	+ }
6601	7423	}
6602	7424
6603	7425	r = _base_allocate_memory_pools(ioc);
6604	7426	if (r)
6605	7427	goto out_free_resources;
6606	7428
	7429	+ if (irqpoll_weight > 0)
	7430	+ ioc->thresh_hold = irqpoll_weight;
	7431	+ else
	7432	+ ioc->thresh_hold = ioc->hba_queue_depth/4;
	7433	+
	7434	+ _base_init_irqpolls(ioc);
6607	7435	init_waitqueue_head(&ioc->reset_wq);
6608	7436
6609	7437	/* allocate memory pd handle bitmask list */
..	..	@@ -6717,7 +7545,15 @@
6717	7545	if (r)
6718	7546	goto out_free_resources;
6719	7547
	7548	+ /*
	7549	+ * Copy current copy of IOCFacts in prev_fw_facts
	7550	+ * and it will be used during online firmware upgrade.
	7551	+ */
	7552	+ memcpy(&ioc->prev_fw_facts, &ioc->facts,
	7553	+ sizeof(struct mpt3sas_facts));
	7554	+
6720	7555	ioc->non_operational_loop = 0;
	7556	+ ioc->ioc_coredump_loop = 0;
6721	7557	ioc->got_task_abort_from_ioctl = 0;
6722	7558	return 0;
6723	7559
..	..	@@ -6762,8 +7598,7 @@
6762	7598	void
6763	7599	mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
6764	7600	{
6765		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6766		- __func__));
	7601	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6767	7602
6768	7603	mpt3sas_base_stop_watchdog(ioc);
6769	7604	mpt3sas_base_free_resources(ioc);
..	..	@@ -6796,20 +7631,18 @@
6796	7631	{
6797	7632	mpt3sas_scsih_pre_reset_handler(ioc);
6798	7633	mpt3sas_ctl_pre_reset_handler(ioc);
6799		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6800		- "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
	7634	+ dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
6801	7635	}
6802	7636
6803	7637	/**
6804		- * _base_after_reset_handler - after reset handler
	7638	+ * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
6805	7639	* @ioc: per adapter object
6806	7640	*/
6807		-static void _base_after_reset_handler(struct MPT3SAS_ADAPTER *ioc)
	7641	+static void
	7642	+_base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
6808	7643	{
6809		- mpt3sas_scsih_after_reset_handler(ioc);
6810		- mpt3sas_ctl_after_reset_handler(ioc);
6811		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6812		- "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
	7644	+ dtmprintk(ioc,
	7645	+ ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
6813	7646	if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
6814	7647	ioc->transport_cmds.status \|= MPT3_CMD_RESET;
6815	7648	mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
..	..	@@ -6843,6 +7676,17 @@
6843	7676	}
6844	7677
6845	7678	/**
	7679	+ * _base_clear_outstanding_commands - clear all outstanding commands
	7680	+ * @ioc: per adapter object
	7681	+ */
	7682	+static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
	7683	+{
	7684	+ mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
	7685	+ mpt3sas_ctl_clear_outstanding_ioctls(ioc);
	7686	+ _base_clear_outstanding_mpt_commands(ioc);
	7687	+}
	7688	+
	7689	+/**
6846	7690	* _base_reset_done_handler - reset done handler
6847	7691	* @ioc: per adapter object
6848	7692	*/
..	..	@@ -6850,8 +7694,7 @@
6850	7694	{
6851	7695	mpt3sas_scsih_reset_done_handler(ioc);
6852	7696	mpt3sas_ctl_reset_done_handler(ioc);
6853		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6854		- "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
	7697	+ dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
6855	7698	}
6856	7699
6857	7700	/**
..	..	@@ -6883,6 +7726,85 @@
6883	7726	}
6884	7727
6885	7728	/**
	7729	+ * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
	7730	+ * attributes during online firmware upgrade and update the corresponding
	7731	+ * IOC variables accordingly.
	7732	+ *
	7733	+ * @ioc: Pointer to MPT_ADAPTER structure
	7734	+ */
	7735	+static int
	7736	+_base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
	7737	+{
	7738	+ u16 pd_handles_sz;
	7739	+ void pd_handles = NULL, blocking_handles = NULL;
	7740	+ void pend_os_device_add = NULL, device_remove_in_progress = NULL;
	7741	+ struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
	7742	+
	7743	+ if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
	7744	+ pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
	7745	+ if (ioc->facts.MaxDevHandle % 8)
	7746	+ pd_handles_sz++;
	7747	+
	7748	+ pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
	7749	+ GFP_KERNEL);
	7750	+ if (!pd_handles) {
	7751	+ ioc_info(ioc,
	7752	+ "Unable to allocate the memory for pd_handles of sz: %d\n",
	7753	+ pd_handles_sz);
	7754	+ return -ENOMEM;
	7755	+ }
	7756	+ memset(pd_handles + ioc->pd_handles_sz, 0,
	7757	+ (pd_handles_sz - ioc->pd_handles_sz));
	7758	+ ioc->pd_handles = pd_handles;
	7759	+
	7760	+ blocking_handles = krealloc(ioc->blocking_handles,
	7761	+ pd_handles_sz, GFP_KERNEL);
	7762	+ if (!blocking_handles) {
	7763	+ ioc_info(ioc,
	7764	+ "Unable to allocate the memory for "
	7765	+ "blocking_handles of sz: %d\n",
	7766	+ pd_handles_sz);
	7767	+ return -ENOMEM;
	7768	+ }
	7769	+ memset(blocking_handles + ioc->pd_handles_sz, 0,
	7770	+ (pd_handles_sz - ioc->pd_handles_sz));
	7771	+ ioc->blocking_handles = blocking_handles;
	7772	+ ioc->pd_handles_sz = pd_handles_sz;
	7773	+
	7774	+ pend_os_device_add = krealloc(ioc->pend_os_device_add,
	7775	+ pd_handles_sz, GFP_KERNEL);
	7776	+ if (!pend_os_device_add) {
	7777	+ ioc_info(ioc,
	7778	+ "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
	7779	+ pd_handles_sz);
	7780	+ return -ENOMEM;
	7781	+ }
	7782	+ memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
	7783	+ (pd_handles_sz - ioc->pend_os_device_add_sz));
	7784	+ ioc->pend_os_device_add = pend_os_device_add;
	7785	+ ioc->pend_os_device_add_sz = pd_handles_sz;
	7786	+
	7787	+ device_remove_in_progress = krealloc(
	7788	+ ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
	7789	+ if (!device_remove_in_progress) {
	7790	+ ioc_info(ioc,
	7791	+ "Unable to allocate the memory for "
	7792	+ "device_remove_in_progress of sz: %d\n "
	7793	+ , pd_handles_sz);
	7794	+ return -ENOMEM;
	7795	+ }
	7796	+ memset(device_remove_in_progress +
	7797	+ ioc->device_remove_in_progress_sz, 0,
	7798	+ (pd_handles_sz - ioc->device_remove_in_progress_sz));
	7799	+ ioc->device_remove_in_progress = device_remove_in_progress;
	7800	+ ioc->device_remove_in_progress_sz = pd_handles_sz;
	7801	+ }
	7802	+
	7803	+ memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
	7804	+ return 0;
	7805	+}
	7806	+
	7807	+/**
6886	7808	* mpt3sas_base_hard_reset_handler - reset controller
6887	7809	* @ioc: Pointer to MPT_ADAPTER structure
6888	7810	* @type: FORCE_BIG_HAMMER or SOFT_RESET
..	..	@@ -6898,12 +7820,10 @@
6898	7820	u32 ioc_state;
6899	7821	u8 is_fault = 0, is_trigger = 0;
6900	7822
6901		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
6902		- __func__));
	7823	+ dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
6903	7824
6904	7825	if (ioc->pci_error_recovery) {
6905		- pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
6906		- ioc->name, __func__);
	7826	+ ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
6907	7827	r = 0;
6908	7828	goto out_unlocked;
6909	7829	}
..	..	@@ -6924,16 +7844,18 @@
6924	7844	MPT3_DIAG_BUFFER_IS_RELEASED))) {
6925	7845	is_trigger = 1;
6926	7846	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6927		- if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
	7847	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT \|\|
	7848	+ (ioc_state & MPI2_IOC_STATE_MASK) ==
	7849	+ MPI2_IOC_STATE_COREDUMP)
6928	7850	is_fault = 1;
6929	7851	}
6930	7852	_base_pre_reset_handler(ioc);
6931	7853	mpt3sas_wait_for_commands_to_complete(ioc);
6932		- _base_mask_interrupts(ioc);
	7854	+ mpt3sas_base_mask_interrupts(ioc);
6933	7855	r = _base_make_ioc_ready(ioc, type);
6934	7856	if (r)
6935	7857	goto out;
6936		- _base_after_reset_handler(ioc);
	7858	+ _base_clear_outstanding_commands(ioc);
6937	7859
6938	7860	/* If this hard reset is called while port enable is active, then
6939	7861	* there is no reason to call make_ioc_operational
..	..	@@ -6947,6 +7869,13 @@
6947	7869	if (r)
6948	7870	goto out;
6949	7871
	7872	+ r = _base_check_ioc_facts_changes(ioc);
	7873	+ if (r) {
	7874	+ ioc_info(ioc,
	7875	+ "Some of the parameters got changed in this new firmware"
	7876	+ " image and it requires system reboot\n");
	7877	+ goto out;
	7878	+ }
6950	7879	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
6951	7880	panic("%s: Issue occurred with flashing controller firmware."
6952	7881	"Please reboot the system and ensure that the correct"
..	..	@@ -6957,8 +7886,7 @@
6957	7886	_base_reset_done_handler(ioc);
6958	7887
6959	7888	out:
6960		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
6961		- ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
	7889	+ ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
6962	7890
6963	7891	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6964	7892	ioc->shost_recovery = 0;
..	..	@@ -6974,7 +7902,6 @@
6974	7902	mpt3sas_trigger_master(ioc,
6975	7903	MASTER_TRIGGER_ADAPTER_RESET);
6976	7904	}
6977		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
6978		- __func__));
	7905	+ dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
6979	7906	return r;
6980	7907	}