forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/phy/mediatek/phy-mtk-tphy.c
....@@ -43,6 +43,8 @@
4343 #define PA0_RG_USB20_INTR_EN		BIT(5)
4444 
4545 #define U3P_USBPHYACR1		0x004
46
+#define PA1_RG_INTR_CAL		GENMASK(23, 19)
47
+#define PA1_RG_INTR_CAL_VAL(x)	((0x1f & (x)) << 19)
4648 #define PA1_RG_VRT_SEL			GENMASK(14, 12)
4749 #define PA1_RG_VRT_SEL_VAL(x)	((0x7 & (x)) << 12)
4850 #define PA1_RG_TERM_SEL		GENMASK(10, 8)
....@@ -60,6 +62,8 @@
6062 #define U3P_USBPHYACR6		0x018
6163 #define PA6_RG_U2_BC11_SW_EN		BIT(23)
6264 #define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
65
+#define PA6_RG_U2_DISCTH		GENMASK(7, 4)
66
+#define PA6_RG_U2_DISCTH_VAL(x)	((0xf & (x)) << 4)
6367 #define PA6_RG_U2_SQTH		GENMASK(3, 0)
6468 #define PA6_RG_U2_SQTH_VAL(x)	(0xf & (x))
6569 
....@@ -294,20 +298,21 @@
294298 		struct u2phy_banks u2_banks;
295299 		struct u3phy_banks u3_banks;
296300 	};
297
-	struct clk *ref_clk;	/* reference clock of anolog phy */
301
+	struct clk *ref_clk;	/* reference clock of (digital) phy */
302
+	struct clk *da_ref_clk;	/* reference clock of analog phy */
298303 	u32 index;
299304 	u8 type;
300305 	int eye_src;
301306 	int eye_vrt;
302307 	int eye_term;
308
+	int intr;
309
+	int discth;
303310 	bool bc12_en;
304311 };
305312 
306313 struct mtk_tphy {
307314 	struct device *dev;
308315 	void __iomem *sif_base;	/* only shared sif */
309
-	/* deprecated, use @ref_clk instead in phy instance */
310
-	struct clk *u3phya_ref;	/* reference clock of usb3 anolog phy */
311316 	const struct mtk_phy_pdata *pdata;
312317 	struct mtk_phy_instance **phys;
313318 	int nphys;
....@@ -850,9 +855,14 @@
850855 				 &instance->eye_vrt);
851856 	device_property_read_u32(dev, "mediatek,eye-term",
852857 				 &instance->eye_term);
853
-	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n",
858
+	device_property_read_u32(dev, "mediatek,intr",
859
+				 &instance->intr);
860
+	device_property_read_u32(dev, "mediatek,discth",
861
+				 &instance->discth);
862
+	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
854863 		instance->bc12_en, instance->eye_src,
855
-		instance->eye_vrt, instance->eye_term);
864
+		instance->eye_vrt, instance->eye_term,
865
+		instance->intr, instance->discth);
856866 }
857867 
858868 static void u2_phy_props_set(struct mtk_tphy *tphy,
....@@ -888,6 +898,20 @@
888898 		tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
889899 		writel(tmp, com + U3P_USBPHYACR1);
890900 	}
901
+
902
+	if (instance->intr) {
903
+		tmp = readl(com + U3P_USBPHYACR1);
904
+		tmp &= ~PA1_RG_INTR_CAL;
905
+		tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
906
+		writel(tmp, com + U3P_USBPHYACR1);
907
+	}
908
+
909
+	if (instance->discth) {
910
+		tmp = readl(com + U3P_USBPHYACR6);
911
+		tmp &= ~PA6_RG_U2_DISCTH;
912
+		tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
913
+		writel(tmp, com + U3P_USBPHYACR6);
914
+	}
891915 }
892916 
893917 static int mtk_phy_init(struct phy *phy)
....@@ -896,15 +920,16 @@
896920 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
897921 	int ret;
898922 
899
-	ret = clk_prepare_enable(tphy->u3phya_ref);
900
-	if (ret) {
901
-		dev_err(tphy->dev, "failed to enable u3phya_ref\n");
902
-		return ret;
903
-	}
904
-
905923 	ret = clk_prepare_enable(instance->ref_clk);
906924 	if (ret) {
907925 		dev_err(tphy->dev, "failed to enable ref_clk\n");
926
+		return ret;
927
+	}
928
+
929
+	ret = clk_prepare_enable(instance->da_ref_clk);
930
+	if (ret) {
931
+		dev_err(tphy->dev, "failed to enable da_ref\n");
932
+		clk_disable_unprepare(instance->ref_clk);
908933 		return ret;
909934 	}
910935 
....@@ -924,6 +949,8 @@
924949 		break;
925950 	default:
926951 		dev_err(tphy->dev, "incompatible PHY type\n");
952
+		clk_disable_unprepare(instance->ref_clk);
953
+		clk_disable_unprepare(instance->da_ref_clk);
927954 		return -EINVAL;
928955 	}
929956 
....@@ -967,11 +994,11 @@
967994 		u2_phy_instance_exit(tphy, instance);
968995 
969996 	clk_disable_unprepare(instance->ref_clk);
970
-	clk_disable_unprepare(tphy->u3phya_ref);
997
+	clk_disable_unprepare(instance->da_ref_clk);
971998 	return 0;
972999 }
9731000 
974
-static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
1001
+static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
9751002 {
9761003 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
9771004 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
....@@ -1102,15 +1129,6 @@
11021129 		}
11031130 	}
11041131 
1105
-	/* it's deprecated, make it optional for backward compatibility */
1106
-	tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
1107
-	if (IS_ERR(tphy->u3phya_ref)) {
1108
-		if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER)
1109
-			return -EPROBE_DEFER;
1110
-
1111
-		tphy->u3phya_ref = NULL;
1112
-	}
1113
-
11141132 	tphy->src_ref_clk = U3P_REF_CLK;
11151133 	tphy->src_coef = U3P_SLEW_RATE_COEF;
11161134 	/* update parameters of slew rate calibrate if exist */
....@@ -1157,16 +1175,20 @@
11571175 		phy_set_drvdata(phy, instance);
11581176 		port++;
11591177 
1160
-		/* if deprecated clock is provided, ignore instance's one */
1161
-		if (tphy->u3phya_ref)
1162
-			continue;
1163
-
1164
-		instance->ref_clk = devm_clk_get(&phy->dev, "ref");
1178
+		instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref");
11651179 		if (IS_ERR(instance->ref_clk)) {
11661180 			dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
11671181 			retval = PTR_ERR(instance->ref_clk);
11681182 			goto put_child;
11691183 		}
1184
+
1185
+		instance->da_ref_clk =
1186
+			devm_clk_get_optional(&phy->dev, "da_ref");
1187
+		if (IS_ERR(instance->da_ref_clk)) {
1188
+			dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port);
1189
+			retval = PTR_ERR(instance->da_ref_clk);
1190
+			goto put_child;
1191
+		}
11701192 	}
11711193 
11721194 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);