hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2
kernel/drivers/net/phy/marvell10g.c
....@@ -263,6 +263,13 @@
263263 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
264264 MV_V2_PORT_CTRL_PWRDOWN);
265265
266
+ /* Sometimes, the power down bit doesn't clear immediately, and
267
+ * a read of this register causes the bit not to clear. Delay
268
+ * 100us to allow the PHY to come out of power down mode before
269
+ * the next access.
270
+ */
271
+ udelay(100);
272
+
266273 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
267274 priv->firmware_ver < 0x00030000)
268275 return ret;