add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3
4
  * DWC Ether MAC version 4.xx  has been used for  developing this code.
..
..
@@ -5,10 +6,6 @@
5
6
  * This contains the functions to handle the dma.
6
7
  *
7
8
  * Copyright (C) 2015  STMicroelectronics Ltd
8
- *
9
- * This program is free software; you can redistribute it and/or modify it
10
- * under the terms and conditions of the GNU General Public License,
11
- * version 2, as published by the Free Software Foundation.
12
9
  *
13
10
  * Author: Alexandre Torgue <alexandre.torgue@st.com>
14
11
  */
..
..
@@ -73,7 +70,7 @@
73
70
 
74
71
 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
75
72
 				    struct stmmac_dma_cfg *dma_cfg,
76
-				    u32 dma_rx_phy, u32 chan)
73
+				    dma_addr_t dma_rx_phy, u32 chan)
77
74
 {
78
75
 	u32 value;
79
76
 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
..
..
@@ -82,12 +79,16 @@
82
79
 	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
83
80
 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
84
81
 
85
-	writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
82
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
83
+		writel(upper_32_bits(dma_rx_phy),
84
+		       ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
85
+
86
+	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
86
87
 }
87
88
 
88
89
 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
89
90
 				    struct stmmac_dma_cfg *dma_cfg,
90
-				    u32 dma_tx_phy, u32 chan)
91
+				    dma_addr_t dma_tx_phy, u32 chan)
91
92
 {
92
93
 	u32 value;
93
94
 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
..
..
@@ -100,7 +101,11 @@
100
101
 
101
102
 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
102
103
 
103
-	writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
104
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
105
+		writel(upper_32_bits(dma_tx_phy),
106
+		       ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
107
+
108
+	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
104
109
 }
105
110
 
106
111
 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
..
..
@@ -151,6 +156,9 @@
151
156
 
152
157
 	if (dma_cfg->aal)
153
158
 		value |= DMA_SYS_BUS_AAL;
159
+
160
+	if (dma_cfg->eame)
161
+		value |= DMA_SYS_BUS_EAME;
154
162
 
155
163
 	writel(value, ioaddr + DMA_SYS_BUS_MODE);
156
164
 }
..
..
@@ -261,19 +269,9 @@
261
269
 			rfa = 0x01; /* Full-1.5K */
262
270
 			break;
263
271
 
264
-		case 8192:
265
-			rfd = 0x06; /* Full-4K */
266
-			rfa = 0x0a; /* Full-6K */
267
-			break;
268
-
269
-		case 16384:
270
-			rfd = 0x06; /* Full-4K */
271
-			rfa = 0x12; /* Full-10K */
272
-			break;
273
-
274
272
 		default:
275
-			rfd = 0x06; /* Full-4K */
276
-			rfa = 0x1e; /* Full-16K */
273
+			rfd = 0x07; /* Full-4.5K */
274
+			rfa = 0x04; /* Full-3K */
277
275
 			break;
278
276
 		}
279
277
 
..
..
@@ -339,8 +337,8 @@
339
337
 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
340
338
 }
341
339
 
342
-static void dwmac4_get_hw_feature(void __iomem *ioaddr,
343
-				  struct dma_features *dma_cap)
340
+static int dwmac4_get_hw_feature(void __iomem *ioaddr,
341
+				 struct dma_features *dma_cap)
344
342
 {
345
343
 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
346
344
 
..
..
@@ -348,7 +346,7 @@
348
346
 	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
349
347
 	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
350
348
 	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
351
-	dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
349
+	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
352
350
 	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
353
351
 	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
354
352
 	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
..
..
@@ -363,11 +361,33 @@
363
361
 	/* TX and RX csum */
364
362
 	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
365
363
 	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
364
+	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
365
+	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
366
366
 
367
367
 	/* MAC HW feature1 */
368
368
 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
369
+	dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
370
+	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
369
371
 	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
370
372
 	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
373
+	dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
374
+
375
+	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
376
+	switch (dma_cap->addr64) {
377
+	case 0:
378
+		dma_cap->addr64 = 32;
379
+		break;
380
+	case 1:
381
+		dma_cap->addr64 = 40;
382
+		break;
383
+	case 2:
384
+		dma_cap->addr64 = 48;
385
+		break;
386
+	default:
387
+		dma_cap->addr64 = 32;
388
+		break;
389
+	}
390
+
371
391
 	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
372
392
 	 * shifting and store the sizes in bytes.
373
393
 	 */
..
..
@@ -396,9 +416,17 @@
396
416
 
397
417
 	/* 5.10 Features */
398
418
 	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
419
+	dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
420
+	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
421
+	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
422
+	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
423
+	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
399
424
 	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
400
425
 	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
401
426
 	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
427
+	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
428
+
429
+	return 0;
402
430
 }
403
431
 
404
432
 /* Enable/disable TSO feature and set MSS */
..
..
@@ -442,6 +470,41 @@
442
470
 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
443
471
 }
444
472
 
473
+static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
474
+{
475
+	u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
476
+
477
+	value &= ~GMAC_CONFIG_HDSMS;
478
+	value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
479
+	writel(value, ioaddr + GMAC_EXT_CONFIG);
480
+
481
+	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
482
+	if (en)
483
+		value |= DMA_CONTROL_SPH;
484
+	else
485
+		value &= ~DMA_CONTROL_SPH;
486
+	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
487
+}
488
+
489
+static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
490
+{
491
+	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
492
+
493
+	if (en)
494
+		value |= DMA_CONTROL_EDSE;
495
+	else
496
+		value &= ~DMA_CONTROL_EDSE;
497
+
498
+	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
499
+
500
+	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
501
+	if (en && !value)
502
+		return -EIO;
503
+
504
+	writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
505
+	return 0;
506
+}
507
+
445
508
 const struct stmmac_dma_ops dwmac4_dma_ops = {
446
509
 	.reset = dwmac4_dma_reset,
447
510
 	.init = dwmac4_dma_init,
..
..
@@ -468,6 +531,7 @@
468
531
 	.enable_tso = dwmac4_enable_tso,
469
532
 	.qmode = dwmac4_qmode,
470
533
 	.set_bfsize = dwmac4_set_bfsize,
534
+	.enable_sph = dwmac4_enable_sph,
471
535
 };
472
536
 
473
537
 const struct stmmac_dma_ops dwmac410_dma_ops = {
..
..
@@ -496,4 +560,6 @@
496
560
 	.enable_tso = dwmac4_enable_tso,
497
561
 	.qmode = dwmac4_qmode,
498
562
 	.set_bfsize = dwmac4_set_bfsize,
563
+	.enable_sph = dwmac4_enable_sph,
564
+	.enable_tbs = dwmac4_enable_tbs,
499
565
 };