.. | .. |
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3 | 3 | * OMAP mailbox driver |
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4 | 4 | * |
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5 | 5 | * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
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6 | | - * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com |
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| 6 | + * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com |
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7 | 7 | * |
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8 | 8 | * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
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9 | 9 | * Suman Anna <s-anna@ti.com> |
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.. | .. |
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141 | 141 | } |
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142 | 142 | |
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143 | 143 | /* Mailbox FIFO handle functions */ |
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144 | | -static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) |
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| 144 | +static u32 mbox_fifo_read(struct omap_mbox *mbox) |
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145 | 145 | { |
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146 | 146 | struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
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147 | 147 | |
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148 | | - return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg); |
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| 148 | + return mbox_read_reg(mbox->parent, fifo->msg); |
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149 | 149 | } |
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150 | 150 | |
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151 | | -static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) |
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| 151 | +static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) |
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152 | 152 | { |
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153 | 153 | struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
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154 | 154 | |
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.. | .. |
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256 | 256 | { |
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257 | 257 | struct omap_mbox_queue *mq = |
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258 | 258 | container_of(work, struct omap_mbox_queue, work); |
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259 | | - mbox_msg_t msg; |
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| 259 | + mbox_msg_t data; |
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| 260 | + u32 msg; |
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260 | 261 | int len; |
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261 | 262 | |
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262 | 263 | while (kfifo_len(&mq->fifo) >= sizeof(msg)) { |
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263 | 264 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
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264 | 265 | WARN_ON(len != sizeof(msg)); |
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| 266 | + data = msg; |
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265 | 267 | |
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266 | | - mbox_chan_received_data(mq->mbox->chan, (void *)msg); |
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| 268 | + mbox_chan_received_data(mq->mbox->chan, (void *)data); |
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267 | 269 | spin_lock_irq(&mq->lock); |
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268 | 270 | if (mq->full) { |
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269 | 271 | mq->full = false; |
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.. | .. |
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286 | 288 | static void __mbox_rx_interrupt(struct omap_mbox *mbox) |
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287 | 289 | { |
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288 | 290 | struct omap_mbox_queue *mq = mbox->rxq; |
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289 | | - mbox_msg_t msg; |
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| 291 | + u32 msg; |
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290 | 292 | int len; |
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291 | 293 | |
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292 | 294 | while (!mbox_fifo_empty(mbox)) { |
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.. | .. |
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486 | 488 | list_add(&mdev->elem, &omap_mbox_devices); |
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487 | 489 | mutex_unlock(&omap_mbox_devices_lock); |
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488 | 490 | |
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489 | | - ret = mbox_controller_register(&mdev->controller); |
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| 491 | + ret = devm_mbox_controller_register(mdev->dev, &mdev->controller); |
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490 | 492 | |
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491 | 493 | err_out: |
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492 | 494 | if (ret) { |
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.. | .. |
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507 | 509 | mutex_lock(&omap_mbox_devices_lock); |
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508 | 510 | list_del(&mdev->elem); |
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509 | 511 | mutex_unlock(&omap_mbox_devices_lock); |
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510 | | - |
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511 | | - mbox_controller_unregister(&mdev->controller); |
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512 | 512 | |
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513 | 513 | mboxes = mdev->mboxes; |
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514 | 514 | for (i = 0; mboxes[i]; i++) |
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.. | .. |
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542 | 542 | mutex_unlock(&mdev->cfg_lock); |
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543 | 543 | } |
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544 | 544 | |
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545 | | -static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) |
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| 545 | +static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg) |
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546 | 546 | { |
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547 | 547 | int ret = -EBUSY; |
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548 | 548 | |
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549 | 549 | if (!mbox_fifo_full(mbox)) { |
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550 | 550 | _omap_mbox_enable_irq(mbox, IRQ_RX); |
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551 | | - mbox_fifo_write(mbox, (mbox_msg_t)data); |
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| 551 | + mbox_fifo_write(mbox, msg); |
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552 | 552 | ret = 0; |
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553 | 553 | _omap_mbox_disable_irq(mbox, IRQ_RX); |
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554 | 554 | |
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.. | .. |
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560 | 560 | return ret; |
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561 | 561 | } |
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562 | 562 | |
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563 | | -static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data) |
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| 563 | +static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg) |
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564 | 564 | { |
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565 | 565 | int ret = -EBUSY; |
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566 | 566 | |
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567 | 567 | if (!mbox_fifo_full(mbox)) { |
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568 | | - mbox_fifo_write(mbox, (mbox_msg_t)data); |
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| 568 | + mbox_fifo_write(mbox, msg); |
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569 | 569 | ret = 0; |
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570 | 570 | } |
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571 | 571 | |
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.. | .. |
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578 | 578 | { |
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579 | 579 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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580 | 580 | int ret; |
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| 581 | + u32 msg = omap_mbox_message(data); |
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581 | 582 | |
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582 | 583 | if (!mbox) |
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583 | 584 | return -EINVAL; |
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584 | 585 | |
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585 | 586 | if (mbox->send_no_irq) |
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586 | | - ret = omap_mbox_chan_send_noirq(mbox, data); |
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| 587 | + ret = omap_mbox_chan_send_noirq(mbox, msg); |
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587 | 588 | else |
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588 | | - ret = omap_mbox_chan_send(mbox, data); |
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| 589 | + ret = omap_mbox_chan_send(mbox, msg); |
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589 | 590 | |
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590 | 591 | return ret; |
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591 | 592 | } |
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.. | .. |
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656 | 657 | }, |
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657 | 658 | { |
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658 | 659 | .compatible = "ti,omap4-mailbox", |
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| 660 | + .data = &omap4_data, |
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| 661 | + }, |
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| 662 | + { |
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| 663 | + .compatible = "ti,am654-mailbox", |
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659 | 664 | .data = &omap4_data, |
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660 | 665 | }, |
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661 | 666 | { |
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.. | .. |
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832 | 837 | mdev->intr_type = intr_type; |
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833 | 838 | mdev->mboxes = list; |
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834 | 839 | |
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835 | | - /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */ |
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| 840 | + /* |
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| 841 | + * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready |
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| 842 | + * IRQ and is needed to run the Tx state machine |
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| 843 | + */ |
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836 | 844 | mdev->controller.txdone_irq = true; |
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837 | 845 | mdev->controller.dev = mdev->dev; |
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838 | 846 | mdev->controller.ops = &omap_mbox_chan_ops; |
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.. | .. |
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860 | 868 | dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); |
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861 | 869 | |
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862 | 870 | ret = pm_runtime_put_sync(mdev->dev); |
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863 | | - if (ret < 0) |
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| 871 | + if (ret < 0 && ret != -ENOSYS) |
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864 | 872 | goto unregister; |
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865 | 873 | |
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866 | 874 | devm_kfree(&pdev->dev, finfoblk); |
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.. | .. |
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901 | 909 | return err; |
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902 | 910 | |
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903 | 911 | /* kfifo size sanity check: alignment and minimal size */ |
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904 | | - mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); |
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905 | | - mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, |
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906 | | - sizeof(mbox_msg_t)); |
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| 912 | + mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32)); |
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| 913 | + mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32)); |
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907 | 914 | |
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908 | 915 | err = platform_driver_register(&omap_mbox_driver); |
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909 | 916 | if (err) |
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