add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/irqchip/irq-mips-gic.c
..
..
@@ -46,17 +46,19 @@
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46
 
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 void __iomem *mips_gic_base;
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48
 
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-DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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+static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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50
 
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-static DEFINE_SPINLOCK(gic_lock);
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+static DEFINE_RAW_SPINLOCK(gic_lock);
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 static struct irq_domain *gic_irq_domain;
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-static struct irq_domain *gic_ipi_domain;
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 static int gic_shared_intrs;
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 static unsigned int gic_cpu_pin;
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 static unsigned int timer_cpu_pin;
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 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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+
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
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+#endif /* CONFIG_GENERIC_IRQ_IPI */
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62
 
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 static struct gic_all_vpes_chip_data {
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 	u32	map;
..
..
@@ -207,7 +209,7 @@
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 	irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	switch (type & IRQ_TYPE_SENSE_MASK) {
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 	case IRQ_TYPE_EDGE_FALLING:
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 		pol = GIC_POL_FALLING_EDGE;
..
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@@ -247,7 +249,7 @@
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 	else
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 		irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
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 						 handle_level_irq, NULL);
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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253
 
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 	return 0;
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 }
..
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@@ -265,7 +267,7 @@
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 		return -EINVAL;
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 	/* Assumption : cpumask refers to a single CPU */
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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271
 
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 	/* Re-route this IRQ */
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 	write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
..
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@@ -276,7 +278,7 @@
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 		set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
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279
 
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 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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282
 
281
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 	return IRQ_SET_MASK_OK;
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 }
..
..
@@ -354,12 +356,12 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = false;
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358
 
357
-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_rmask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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366
 
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 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
..
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@@ -372,32 +374,43 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = true;
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376
 
375
-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_smask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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384
 
383
-static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
385
+static void gic_all_vpes_irq_cpu_online(void)
384
386
 {
385
-	struct gic_all_vpes_chip_data *cd;
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-	unsigned int intr;
387
+	static const unsigned int local_intrs[] = {
388
+		GIC_LOCAL_INT_TIMER,
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+		GIC_LOCAL_INT_PERFCTR,
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+		GIC_LOCAL_INT_FDC,
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+	};
392
+	unsigned long flags;
393
+	int i;
387
394
 
388
-	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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-	cd = irq_data_get_irq_chip_data(d);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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396
 
391
-	write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
392
-	if (cd->mask)
393
-		write_gic_vl_smask(BIT(intr));
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+	for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
398
+		unsigned int intr = local_intrs[i];
399
+		struct gic_all_vpes_chip_data *cd;
400
+
401
+		cd = &gic_all_vpes_chip_data[intr];
402
+		write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
403
+		if (cd->mask)
404
+			write_gic_vl_smask(BIT(intr));
405
+	}
406
+
407
+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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408
 }
395
409
 
396
410
 static struct irq_chip gic_all_vpes_local_irq_controller = {
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 	.name			= "MIPS GIC Local",
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 	.irq_mask		= gic_mask_local_irq_all_vpes,
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 	.irq_unmask		= gic_unmask_local_irq_all_vpes,
400
-	.irq_cpu_online		= gic_all_vpes_irq_cpu_online,
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414
 };
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415
 
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 static void __gic_irq_dispatch(void)
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@@ -421,11 +434,11 @@
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434
 
422
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 	data = irq_get_irq_data(virq);
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436
 
424
-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
426
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 	write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
427
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 	irq_data_update_effective_affinity(data, cpumask_of(cpu));
428
-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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442
 
430
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 	return 0;
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 }
..
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@@ -459,9 +472,11 @@
459
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 	u32 map;
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473
 
461
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 	if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
475
+#ifdef CONFIG_GENERIC_IRQ_IPI
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 		/* verify that shared irqs don't conflict with an IPI irq */
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477
 		if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
464
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 			return -EBUSY;
479
+#endif /* CONFIG_GENERIC_IRQ_IPI */
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480
 
466
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 		err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
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482
 						    &gic_level_irq_controller,
..
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@@ -476,11 +491,15 @@
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491
 	intr = GIC_HWIRQ_TO_LOCAL(hwirq);
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 	map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
478
493
 
494
+	/*
495
+	 * If adding support for more per-cpu interrupts, keep the the
496
+	 * array in gic_all_vpes_irq_cpu_online() in sync.
497
+	 */
479
498
 	switch (intr) {
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 	case GIC_LOCAL_INT_TIMER:
481
500
 		/* CONFIG_MIPS_CMP workaround (see __gic_init) */
482
501
 		map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
483
-		/* fall-through */
502
+		fallthrough;
484
503
 	case GIC_LOCAL_INT_PERFCTR:
485
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 	case GIC_LOCAL_INT_FDC:
486
505
 		/*
..
..
@@ -514,12 +533,12 @@
514
533
 	if (!gic_local_irq_is_routable(intr))
515
534
 		return -EPERM;
516
535
 
517
-	spin_lock_irqsave(&gic_lock, flags);
536
+	raw_spin_lock_irqsave(&gic_lock, flags);
518
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 	for_each_online_cpu(cpu) {
519
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
520
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 		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
521
540
 	}
522
-	spin_unlock_irqrestore(&gic_lock, flags);
541
+	raw_spin_unlock_irqrestore(&gic_lock, flags);
523
542
 
524
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 	return 0;
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544
 }
..
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@@ -549,6 +568,8 @@
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 	.free = gic_irq_domain_free,
550
569
 	.map = gic_irq_domain_map,
551
570
 };
571
+
572
+#ifdef CONFIG_GENERIC_IRQ_IPI
552
573
 
553
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 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
554
575
 				const u32 *intspec, unsigned int intsize,
..
..
@@ -617,8 +638,8 @@
617
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 	return ret;
618
639
 }
619
640
 
620
-void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
621
-			 unsigned int nr_irqs)
641
+static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
642
+				unsigned int nr_irqs)
622
643
 {
623
644
 	irq_hw_number_t base_hwirq;
624
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 	struct irq_data *data;
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@@ -631,8 +652,8 @@
631
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 	bitmap_set(ipi_available, base_hwirq, nr_irqs);
632
653
 }
633
654
 
634
-int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
635
-			 enum irq_domain_bus_token bus_token)
655
+static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
656
+				enum irq_domain_bus_token bus_token)
636
657
 {
637
658
 	bool is_ipi;
638
659
 
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@@ -653,6 +674,48 @@
653
674
 	.match = gic_ipi_domain_match,
654
675
 };
655
676
 
677
+static int gic_register_ipi_domain(struct device_node *node)
678
+{
679
+	struct irq_domain *gic_ipi_domain;
680
+	unsigned int v[2], num_ipis;
681
+
682
+	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
683
+						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
684
+						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
685
+						  node, &gic_ipi_domain_ops, NULL);
686
+	if (!gic_ipi_domain) {
687
+		pr_err("Failed to add IPI domain");
688
+		return -ENXIO;
689
+	}
690
+
691
+	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
692
+
693
+	if (node &&
694
+	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
695
+		bitmap_set(ipi_resrv, v[0], v[1]);
696
+	} else {
697
+		/*
698
+		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
699
+		 * meeting the requirements of arch/mips SMP.
700
+		 */
701
+		num_ipis = 2 * num_possible_cpus();
702
+		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
703
+	}
704
+
705
+	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
706
+
707
+	return 0;
708
+}
709
+
710
+#else /* !CONFIG_GENERIC_IRQ_IPI */
711
+
712
+static inline int gic_register_ipi_domain(struct device_node *node)
713
+{
714
+	return 0;
715
+}
716
+
717
+#endif /* !CONFIG_GENERIC_IRQ_IPI */
718
+
656
719
 static int gic_cpu_startup(unsigned int cpu)
657
720
 {
658
721
 	/* Enable or disable EIC */
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@@ -662,8 +725,8 @@
662
725
 	/* Clear all local IRQ masks (ie. disable all local interrupts) */
663
726
 	write_gic_vl_rmask(~0);
664
727
 
665
-	/* Invoke irq_cpu_online callbacks to enable desired interrupts */
666
-	irq_cpu_online();
728
+	/* Enable desired interrupts */
729
+	gic_all_vpes_irq_cpu_online();
667
730
 
668
731
 	return 0;
669
732
 }
..
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@@ -671,11 +734,12 @@
671
734
 static int __init gic_of_init(struct device_node *node,
672
735
 			      struct device_node *parent)
673
736
 {
674
-	unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
737
+	unsigned int cpu_vec, i, gicconfig;
675
738
 	unsigned long reserved;
676
739
 	phys_addr_t gic_base;
677
740
 	struct resource res;
678
741
 	size_t gic_len;
742
+	int ret;
679
743
 
680
744
 	/* Find the first available CPU vector. */
681
745
 	i = 0;
..
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@@ -716,7 +780,11 @@
716
780
 		__sync();
717
781
 	}
718
782
 
719
-	mips_gic_base = ioremap_nocache(gic_base, gic_len);
783
+	mips_gic_base = ioremap(gic_base, gic_len);
784
+	if (!mips_gic_base) {
785
+		pr_err("Failed to ioremap gic_base\n");
786
+		return -ENOMEM;
787
+	}
720
788
 
721
789
 	gicconfig = read_gic_config();
722
790
 	gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
..
..
@@ -764,30 +832,9 @@
764
832
 		return -ENXIO;
765
833
 	}
766
834
 
767
-	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
768
-						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
769
-						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
770
-						  node, &gic_ipi_domain_ops, NULL);
771
-	if (!gic_ipi_domain) {
772
-		pr_err("Failed to add IPI domain");
773
-		return -ENXIO;
774
-	}
775
-
776
-	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
777
-
778
-	if (node &&
779
-	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
780
-		bitmap_set(ipi_resrv, v[0], v[1]);
781
-	} else {
782
-		/*
783
-		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
784
-		 * meeting the requirements of arch/mips SMP.
785
-		 */
786
-		num_ipis = 2 * num_possible_cpus();
787
-		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
788
-	}
789
-
790
-	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
835
+	ret = gic_register_ipi_domain(node);
836
+	if (ret)
837
+		return ret;
791
838
 
792
839
 	board_bind_eic_interrupt = &gic_bind_eic_interrupt;
793
840