forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/i2c/busses/i2c-rk3x.c
....@@ -18,6 +18,7 @@
1818 #include <linux/io.h>
1919 #include <linux/of_address.h>
2020 #include <linux/of_irq.h>
21
+#include <linux/reset.h>
2122 #include <linux/spinlock.h>
2223 #include <linux/clk.h>
2324 #include <linux/wait.h>
....@@ -39,6 +40,7 @@
3940 #define REG_IEN        0x18 /* interrupt enable */
4041 #define REG_IPD        0x1c /* interrupt pending */
4142 #define REG_FCNT       0x20 /* finished count */
43
+#define REG_SCL_OE_DB  0x24 /* Slave hold scl debounce */
4244 #define REG_CON1       0x228 /* control register1 */
4345 
4446 /* Data buffer offsets */
....@@ -87,6 +89,7 @@
8789 #define REG_INT_START     BIT(4) /* START condition generated */
8890 #define REG_INT_STOP      BIT(5) /* STOP condition generated */
8991 #define REG_INT_NAKRCV    BIT(6) /* NACK received */
92
+#define REG_INT_SLV_HDSCL BIT(7) /* slave hold scl */
9093 #define REG_INT_ALL       0xff
9194 
9295 /* Disable i2c all irqs */
....@@ -97,11 +100,11 @@
97100 #define REG_CON1_NACK_AUTO_STOP BIT(2)
98101 
99102 /* Constants */
100
-#define WAIT_TIMEOUT      1000 /* ms */
103
+#define WAIT_TIMEOUT      200 /* ms */
101104 #define DEFAULT_SCL_RATE  (100 * 1000) /* Hz */
102105 
103106 /**
104
- * struct i2c_spec_values:
107
+ * struct i2c_spec_values - I2C specification values for various modes
105108  * @min_hold_start_ns: min hold time (repeated) START condition
106109  * @min_low_ns: min LOW period of the SCL clock
107110  * @min_high_ns: min HIGH period of the SCL cloc
....@@ -157,7 +160,7 @@
157160 };
158161 
159162 /**
160
- * struct rk3x_i2c_calced_timings:
163
+ * struct rk3x_i2c_calced_timings - calculated V1 timings
161164  * @div_low: Divider output for low
162165  * @div_high: Divider output for high
163166  * @tuning: Used to adjust setup/hold data time,
....@@ -179,7 +182,7 @@
179182 };
180183 
181184 /**
182
- * struct rk3x_i2c_soc_data:
185
+ * struct rk3x_i2c_soc_data - SOC-specific data
183186  * @grf_offset: offset inside the grf regmap for setting the i2c type
184187  * @calc_timings: Callback function for i2c timing information calculated
185188  */
....@@ -224,6 +227,9 @@
224227 	struct clk *pclk;
225228 	struct notifier_block clk_rate_nb;
226229 	bool autostop_supported;
230
+
231
+	struct reset_control *reset;
232
+	struct reset_control *reset_apb;
227233 
228234 	/* Settings */
229235 	struct i2c_timings t;
....@@ -307,6 +313,13 @@
307313 	if (len > 32)
308314 		goto out;
309315 
316
+	/* For tx mode, one byte of the device address also needs to be counted,
317
+	 * if the data length is equal to 32, which is actually 33 bytes, it would
318
+	 * need to be divided into two parts, and needs to jump out of autostop.
319
+	 */
320
+	if (i2c->msg->len == 32 && i2c->mode == REG_CON_MOD_TX && !i2c->processed)
321
+		goto out;
322
+
310323 	i2c->state = STATE_STOP;
311324 
312325 	con1 |= REG_CON1_TRANSFER_AUTO_STOP | REG_CON1_AUTO_STOP;
....@@ -324,7 +337,8 @@
324337 }
325338 
326339 /**
327
- * Generate a START condition, which triggers a REG_INT_START interrupt.
340
+ * rk3x_i2c_start - Generate a START condition, which triggers a REG_INT_START interrupt.
341
+ * @i2c: target controller data
328342  */
329343 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
330344 {
....@@ -364,8 +378,8 @@
364378 }
365379 
366380 /**
367
- * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
368
- *
381
+ * rk3x_i2c_stop - Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
382
+ * @i2c: target controller data
369383  * @error: Error code to return in rk3x_i2c_xfer
370384  */
371385 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
....@@ -373,7 +387,6 @@
373387 	unsigned int ctrl;
374388 
375389 	i2c->processed = 0;
376
-	i2c->msg = NULL;
377390 	i2c->error = error;
378391 
379392 	if (i2c->is_last_msg) {
....@@ -390,6 +403,7 @@
390403 		/* Signal rk3x_i2c_xfer to start the next message. */
391404 		i2c->busy = false;
392405 		i2c->state = STATE_IDLE;
406
+		i2c->msg = NULL;
393407 
394408 		/*
395409 		 * The HW is actually not capable of REPEATED START. But we can
....@@ -405,7 +419,8 @@
405419 }
406420 
407421 /**
408
- * Setup a read according to i2c->msg
422
+ * rk3x_i2c_prepare_read - Setup a read according to i2c->msg
423
+ * @i2c: target controller data
409424  */
410425 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
411426 {
....@@ -438,7 +453,8 @@
438453 }
439454 
440455 /**
441
- * Fill the transmit buffer with data from i2c->msg
456
+ * rk3x_i2c_fill_transmit_buf - Fill the transmit buffer with data from i2c->msg
457
+ * @i2c: target controller data
442458  */
443459 static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sendend)
444460 {
....@@ -556,7 +572,6 @@
556572 		}
557573 
558574 		i2c->processed = 0;
559
-		i2c->msg = NULL;
560575 	}
561576 
562577 	/* ack interrupt */
....@@ -571,6 +586,7 @@
571586 
572587 	i2c->busy = false;
573588 	i2c->state = STATE_IDLE;
589
+	i2c->msg = NULL;
574590 
575591 	/* signal rk3x_i2c_xfer that we are finished */
576592 	rk3x_i2c_wake_up(i2c);
....@@ -595,7 +611,7 @@
595611 	dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
596612 
597613 	/* Clean interrupt bits we don't care about */
598
-	ipd &= ~(REG_INT_BRF | REG_INT_BTF);
614
+	ipd &= ~(REG_INT_BRF | REG_INT_BTF | REG_INT_START);
599615 
600616 	if (ipd & REG_INT_NAKRCV) {
601617 		/*
....@@ -642,11 +658,10 @@
642658 }
643659 
644660 /**
645
- * Get timing values of I2C specification
646
- *
661
+ * rk3x_i2c_get_spec - Get timing values of I2C specification
647662  * @speed: Desired SCL frequency
648663  *
649
- * Returns: Matched i2c spec values.
664
+ * Return: Matched i2c_spec_values.
650665  */
651666 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
652667 {
....@@ -659,13 +674,12 @@
659674 }
660675 
661676 /**
662
- * Calculate divider values for desired SCL frequency
663
- *
677
+ * rk3x_i2c_v0_calc_timings - Calculate divider values for desired SCL frequency
664678  * @clk_rate: I2C input clock rate
665679  * @t: Known I2C timing information
666680  * @t_calc: Caculated rk3x private timings that would be written into regs
667681  *
668
- * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
682
+ * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
669683  * a best-effort divider value is returned in divs. If the target rate is
670684  * too high, we silently use the highest possible rate.
671685  */
....@@ -820,13 +834,12 @@
820834 }
821835 
822836 /**
823
- * Calculate timing values for desired SCL frequency
824
- *
837
+ * rk3x_i2c_v1_calc_timings - Calculate timing values for desired SCL frequency
825838  * @clk_rate: I2C input clock rate
826839  * @t: Known I2C timing information
827840  * @t_calc: Caculated rk3x private timings that would be written into regs
828841  *
829
- * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
842
+ * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
830843  * a best-effort divider value is returned in divs. If the target rate is
831844  * too high, we silently use the highest possible rate.
832845  * The following formulas are v1's method to calculate timings.
....@@ -983,9 +996,10 @@
983996 {
984997 	struct i2c_timings *t = &i2c->t;
985998 	struct rk3x_i2c_calced_timings calc;
999
+	unsigned long period, time_hold = (WAIT_TIMEOUT / 2) * 1000000;
9861000 	u64 t_low_ns, t_high_ns;
9871001 	unsigned long flags;
988
-	u32 val;
1002
+	u32 val, cnt;
9891003 	int ret;
9901004 
9911005 	ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
....@@ -1000,6 +1014,10 @@
10001014 	i2c_writel(i2c, val, REG_CON);
10011015 	i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
10021016 		   REG_CLKDIV);
1017
+
1018
+	period = DIV_ROUND_UP(1000000000, clk_rate);
1019
+	cnt = DIV_ROUND_UP(time_hold, period);
1020
+	i2c_writel(i2c, cnt, REG_SCL_OE_DB);
10031021 	spin_unlock_irqrestore(&i2c->lock, flags);
10041022 
10051023 	clk_disable(i2c->pclk);
....@@ -1070,14 +1088,14 @@
10701088 }
10711089 
10721090 /**
1073
- * Setup I2C registers for an I2C operation specified by msgs, num.
1074
- *
1075
- * Must be called with i2c->lock held.
1076
- *
1091
+ * rk3x_i2c_setup - Setup I2C registers for an I2C operation specified by msgs, num.
1092
+ * @i2c: target controller data
10771093  * @msgs: I2C msgs to process
10781094  * @num: Number of msgs
10791095  *
1080
- * returns: Number of I2C msgs processed or negative in case of error
1096
+ * Must be called with i2c->lock held.
1097
+ *
1098
+ * Return: Number of I2C msgs processed or negative in case of error
10811099  */
10821100 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
10831101 {
....@@ -1165,12 +1183,30 @@
11651183 	return !i2c->busy;
11661184 }
11671185 
1186
+/*
1187
+ * Reset i2c controller, reset all i2c registers.
1188
+ */
1189
+static void rk3x_i2c_reset_controller(struct rk3x_i2c *i2c)
1190
+{
1191
+	if (!IS_ERR_OR_NULL(i2c->reset)) {
1192
+		reset_control_assert(i2c->reset);
1193
+		udelay(10);
1194
+		reset_control_deassert(i2c->reset);
1195
+	}
1196
+
1197
+	if (!IS_ERR_OR_NULL(i2c->reset_apb)) {
1198
+		reset_control_assert(i2c->reset_apb);
1199
+		udelay(10);
1200
+		reset_control_deassert(i2c->reset_apb);
1201
+	}
1202
+}
1203
+
11681204 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
11691205 				struct i2c_msg *msgs, int num, bool polling)
11701206 {
11711207 	struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
11721208 	unsigned long timeout, flags;
1173
-	u32 val;
1209
+	u32 val, ipd = 0;
11741210 	int ret = 0;
11751211 	int i;
11761212 
....@@ -1189,7 +1225,7 @@
11891225 	 * rk3x_i2c_setup()).
11901226 	 */
11911227 	for (i = 0; i < num; i += ret) {
1192
-		unsigned long xfer_time = 100;
1228
+		unsigned long xfer_time = WAIT_TIMEOUT;
11931229 		int len;
11941230 
11951231 		ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
....@@ -1227,8 +1263,9 @@
12271263 		spin_lock_irqsave(&i2c->lock, flags);
12281264 
12291265 		if (timeout == 0) {
1266
+			ipd = i2c_readl(i2c, REG_IPD);
12301267 			dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1231
-				i2c_readl(i2c, REG_IPD), i2c->state);
1268
+				ipd, i2c->state);
12321269 
12331270 			/* Force a STOP condition without interrupt */
12341271 			rk3x_i2c_disable_irq(i2c);
....@@ -1255,6 +1292,12 @@
12551292 	clk_disable(i2c->clk);
12561293 
12571294 	spin_unlock_irqrestore(&i2c->lock, flags);
1295
+
1296
+	if ((ret == -ETIMEDOUT) && (ipd & REG_INT_SLV_HDSCL)) {
1297
+		rk3x_i2c_reset_controller(i2c);
1298
+		dev_err(i2c->dev, "SCL hold by slave, check your device.\n");
1299
+		rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1300
+	}
12581301 
12591302 	return ret < 0 ? ret : num;
12601303 }
....@@ -1602,6 +1645,7 @@
16021645 
16031646 	platform_set_drvdata(pdev, i2c);
16041647 
1648
+	i2c->reset = devm_reset_control_get(&pdev->dev, "i2c");
16051649 	if (!has_acpi_companion(&pdev->dev)) {
16061650 		if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
16071651 			/* Only one clock to use for bus clock and peripheral clock */
....@@ -1610,6 +1654,7 @@
16101654 		} else {
16111655 			i2c->clk = devm_clk_get(&pdev->dev, "i2c");
16121656 			i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1657
+			i2c->reset_apb = devm_reset_control_get(&pdev->dev, "apb");
16131658 		}
16141659 
16151660 		if (IS_ERR(i2c->clk))