~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* i2c_adap_pxa.c
3	4	*
..	..	@@ -5,10 +6,6 @@
5	6	*
6	7	* Copyright (C) 2002 Intrinsyc Software Inc.
7	8	* Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8		- *
9		- * This program is free software; you can redistribute it and/or modify
10		- * it under the terms of the GNU General Public License version 2 as
11		- * published by the Free Software Foundation.
12	9	*
13	10	* History:
14	11	* Apr 2002: Initial version [CS]
..	..	@@ -19,26 +16,120 @@
19	16	* Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20	17	* Feb 2005: Rework slave mode handling [RMK]
21	18	*/
22		-#include <linux/kernel.h>
23		-#include <linux/module.h>
	19	+#include <linux/clk.h>
	20	+#include <linux/delay.h>
	21	+#include <linux/err.h>
	22	+#include <linux/errno.h>
	23	+#include <linux/gpio/consumer.h>
24	24	#include <linux/i2c.h>
25	25	#include <linux/init.h>
26		-#include <linux/time.h>
27		-#include <linux/sched.h>
28		-#include <linux/delay.h>
29		-#include <linux/errno.h>
30	26	#include <linux/interrupt.h>
31		-#include <linux/i2c-pxa.h>
	27	+#include <linux/io.h>
	28	+#include <linux/kernel.h>
	29	+#include <linux/module.h>
32	30	#include <linux/of.h>
33	31	#include <linux/of_device.h>
	32	+#include <linux/pinctrl/consumer.h>
34	33	#include <linux/platform_device.h>
35		-#include <linux/err.h>
36		-#include <linux/clk.h>
37		-#include <linux/slab.h>
38		-#include <linux/io.h>
39	34	#include <linux/platform_data/i2c-pxa.h>
	35	+#include <linux/slab.h>
40	36
41		-#include <asm/irq.h>
	37	+/* I2C register field definitions */
	38	+#define IBMR_SDAS (1 << 0)
	39	+#define IBMR_SCLS (1 << 1)
	40	+
	41	+#define ICR_START (1 << 0) /* start bit */
	42	+#define ICR_STOP (1 << 1) /* stop bit */
	43	+#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
	44	+#define ICR_TB (1 << 3) /* transfer byte bit */
	45	+#define ICR_MA (1 << 4) /* master abort */
	46	+#define ICR_SCLE (1 << 5) /* master clock enable */
	47	+#define ICR_IUE (1 << 6) /* unit enable */
	48	+#define ICR_GCD (1 << 7) /* general call disable */
	49	+#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
	50	+#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
	51	+#define ICR_BEIE (1 << 10) /* enable bus error ints */
	52	+#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
	53	+#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
	54	+#define ICR_SADIE (1 << 13) /* slave address detected int enable */
	55	+#define ICR_UR (1 << 14) /* unit reset */
	56	+#define ICR_FM (1 << 15) /* fast mode */
	57	+#define ICR_HS (1 << 16) /* High Speed mode */
	58	+#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
	59	+#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
	60	+#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
	61	+
	62	+#define ISR_RWM (1 << 0) /* read/write mode */
	63	+#define ISR_ACKNAK (1 << 1) /* ack/nak status */
	64	+#define ISR_UB (1 << 2) /* unit busy */
	65	+#define ISR_IBB (1 << 3) /* bus busy */
	66	+#define ISR_SSD (1 << 4) /* slave stop detected */
	67	+#define ISR_ALD (1 << 5) /* arbitration loss detected */
	68	+#define ISR_ITE (1 << 6) /* tx buffer empty */
	69	+#define ISR_IRF (1 << 7) /* rx buffer full */
	70	+#define ISR_GCAD (1 << 8) /* general call address detected */
	71	+#define ISR_SAD (1 << 9) /* slave address detected */
	72	+#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
	73	+
	74	+#define ILCR_SLV_SHIFT 0
	75	+#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
	76	+#define ILCR_FLV_SHIFT 9
	77	+#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
	78	+#define ILCR_HLVL_SHIFT 18
	79	+#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
	80	+#define ILCR_HLVH_SHIFT 27
	81	+#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
	82	+
	83	+#define IWCR_CNT_SHIFT 0
	84	+#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
	85	+#define IWCR_HS_CNT1_SHIFT 5
	86	+#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
	87	+#define IWCR_HS_CNT2_SHIFT 10
	88	+#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
	89	+
	90	+/* need a longer timeout if we're dealing with the fact we may well be
	91	+ * looking at a multi-master environment
	92	+ */
	93	+#define DEF_TIMEOUT 32
	94	+
	95	+#define NO_SLAVE (-ENXIO)
	96	+#define BUS_ERROR (-EREMOTEIO)
	97	+#define XFER_NAKED (-ECONNREFUSED)
	98	+#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
	99	+
	100	+/* ICR initialize bit values
	101	+ *
	102	+ * 15 FM 0 (100 kHz operation)
	103	+ * 14 UR 0 (No unit reset)
	104	+ * 13 SADIE 0 (Disables the unit from interrupting on slave addresses
	105	+ * matching its slave address)
	106	+ * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
	107	+ * in master mode)
	108	+ * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
	109	+ * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
	110	+ * 9 IRFIE 1 (Enable interrupts from full buffer received)
	111	+ * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
	112	+ * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
	113	+ * 6 IUE 0 (Disable unit until we change settings)
	114	+ * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
	115	+ * 4 MA 0 (Only send stop with the ICR stop bit)
	116	+ * 3 TB 0 (We are not transmitting a byte initially)
	117	+ * 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
	118	+ * 1 STOP 0 (Do not send a STOP)
	119	+ * 0 START 0 (Do not send a START)
	120	+ */
	121	+#define I2C_ICR_INIT (ICR_BEIE \| ICR_IRFIE \| ICR_ITEIE \| ICR_GCD \| ICR_SCLE)
	122	+
	123	+/* I2C status register init values
	124	+ *
	125	+ * 10 BED 1 (Clear bus error detected)
	126	+ * 9 SAD 1 (Clear slave address detected)
	127	+ * 7 IRF 1 (Clear IDBR Receive Full)
	128	+ * 6 ITE 1 (Clear IDBR Transmit Empty)
	129	+ * 5 ALD 1 (Clear Arbitration Loss Detected)
	130	+ * 4 SSD 1 (Clear Slave Stop Detected)
	131	+ */
	132	+#define I2C_ISR_INIT 0x7FF /* status register init */
42	133
43	134	struct pxa_reg_layout {
44	135	u32 ibmr;
..	..	@@ -60,12 +151,7 @@
60	151	REGS_A3700,
61	152	};
62	153
63		-#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
64		-#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
65		-
66		-/*
67		- * I2C registers definitions
68		- */
	154	+/* I2C register layout definitions */
69	155	static struct pxa_reg_layout pxa_reg_layout[] = {
70	156	[REGS_PXA2XX] = {
71	157	.ibmr = 0x00,
..	..	@@ -73,6 +159,8 @@
73	159	.icr = 0x10,
74	160	.isr = 0x18,
75	161	.isar = 0x20,
	162	+ .fm = ICR_FM,
	163	+ .hs = ICR_HS,
76	164	},
77	165	[REGS_PXA3XX] = {
78	166	.ibmr = 0x00,
..	..	@@ -80,6 +168,8 @@
80	168	.icr = 0x08,
81	169	.isr = 0x0c,
82	170	.isar = 0x10,
	171	+ .fm = ICR_FM,
	172	+ .hs = ICR_HS,
83	173	},
84	174	[REGS_CE4100] = {
85	175	.ibmr = 0x14,
..	..	@@ -87,6 +177,8 @@
87	177	.icr = 0x00,
88	178	.isr = 0x04,
89	179	/* no isar register */
	180	+ .fm = ICR_FM,
	181	+ .hs = ICR_HS,
90	182	},
91	183	[REGS_PXA910] = {
92	184	.ibmr = 0x00,
..	..	@@ -96,6 +188,8 @@
96	188	.isar = 0x20,
97	189	.ilcr = 0x28,
98	190	.iwcr = 0x30,
	191	+ .fm = ICR_FM,
	192	+ .hs = ICR_HS,
99	193	},
100	194	[REGS_A3700] = {
101	195	.ibmr = 0x00,
..	..	@@ -103,10 +197,19 @@
103	197	.icr = 0x08,
104	198	.isr = 0x0c,
105	199	.isar = 0x10,
106		- .fm = ICR_BUSMODE_FM,
107		- .hs = ICR_BUSMODE_HS,
	200	+ .fm = ICR_A3700_FM,
	201	+ .hs = ICR_A3700_HS,
108	202	},
109	203	};
	204	+
	205	+static const struct of_device_id i2c_pxa_dt_ids[] = {
	206	+ { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
	207	+ { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
	208	+ { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
	209	+ { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
	210	+ {}
	211	+};
	212	+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
110	213
111	214	static const struct platform_device_id i2c_pxa_id_table[] = {
112	215	{ "pxa2xx-i2c", REGS_PXA2XX },
..	..	@@ -117,58 +220,6 @@
117	220	{ },
118	221	};
119	222	MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
120		-
121		-/*
122		- * I2C bit definitions
123		- */
124		-
125		-#define ICR_START (1 << 0) /* start bit */
126		-#define ICR_STOP (1 << 1) /* stop bit */
127		-#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
128		-#define ICR_TB (1 << 3) /* transfer byte bit */
129		-#define ICR_MA (1 << 4) /* master abort */
130		-#define ICR_SCLE (1 << 5) /* master clock enable */
131		-#define ICR_IUE (1 << 6) /* unit enable */
132		-#define ICR_GCD (1 << 7) /* general call disable */
133		-#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
134		-#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
135		-#define ICR_BEIE (1 << 10) /* enable bus error ints */
136		-#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
137		-#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
138		-#define ICR_SADIE (1 << 13) /* slave address detected int enable */
139		-#define ICR_UR (1 << 14) /* unit reset */
140		-#define ICR_FM (1 << 15) /* fast mode */
141		-#define ICR_HS (1 << 16) /* High Speed mode */
142		-#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
143		-
144		-#define ISR_RWM (1 << 0) /* read/write mode */
145		-#define ISR_ACKNAK (1 << 1) /* ack/nak status */
146		-#define ISR_UB (1 << 2) /* unit busy */
147		-#define ISR_IBB (1 << 3) /* bus busy */
148		-#define ISR_SSD (1 << 4) /* slave stop detected */
149		-#define ISR_ALD (1 << 5) /* arbitration loss detected */
150		-#define ISR_ITE (1 << 6) /* tx buffer empty */
151		-#define ISR_IRF (1 << 7) /* rx buffer full */
152		-#define ISR_GCAD (1 << 8) /* general call address detected */
153		-#define ISR_SAD (1 << 9) /* slave address detected */
154		-#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
155		-
156		-/* bit field shift & mask */
157		-#define ILCR_SLV_SHIFT 0
158		-#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
159		-#define ILCR_FLV_SHIFT 9
160		-#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
161		-#define ILCR_HLVL_SHIFT 18
162		-#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
163		-#define ILCR_HLVH_SHIFT 27
164		-#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
165		-
166		-#define IWCR_CNT_SHIFT 0
167		-#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
168		-#define IWCR_HS_CNT1_SHIFT 5
169		-#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
170		-#define IWCR_HS_CNT2_SHIFT 10
171		-#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
172	223
173	224	struct pxa_i2c {
174	225	spinlock_t lock;
..	..	@@ -183,7 +234,7 @@
183	234	struct i2c_adapter adap;
184	235	struct clk *clk;
185	236	#ifdef CONFIG_I2C_PXA_SLAVE
186		- struct i2c_slave_client *slave;
	237	+ struct i2c_client *slave;
187	238	#endif
188	239
189	240	unsigned int irqlogidx;
..	..	@@ -211,6 +262,11 @@
211	262	bool highmode_enter;
212	263	u32 fm_mask;
213	264	u32 hs_mask;
	265	+
	266	+ struct i2c_bus_recovery_info recovery;
	267	+ struct pinctrl *pinctrl;
	268	+ struct pinctrl_state *pinctrl_default;
	269	+ struct pinctrl_state *pinctrl_recovery;
214	270	};
215	271
216	272	#define _IBMR(i2c) ((i2c)->reg_ibmr)
..	..	@@ -238,13 +294,14 @@
238	294	static inline void
239	295	decode_bits(const char prefix, const struct bits bits, int num, u32 val)
240	296	{
241		- printk("%s %08x: ", prefix, val);
	297	+ printk("%s %08x:", prefix, val);
242	298	while (num--) {
243	299	const char *str = val & bits->mask ? bits->set : bits->unset;
244	300	if (str)
245		- printk("%s ", str);
	301	+ pr_cont(" %s", str);
246	302	bits++;
247	303	}
	304	+ pr_cont("\n");
248	305	}
249	306
250	307	static const struct bits isr_bits[] = {
..	..	@@ -264,7 +321,6 @@
264	321	static void decode_ISR(unsigned int val)
265	322	{
266	323	decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
267		- printk("\n");
268	324	}
269	325
270	326	static const struct bits icr_bits[] = {
..	..	@@ -289,7 +345,6 @@
289	345	static void decode_ICR(unsigned int val)
290	346	{
291	347	decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
292		- printk("\n");
293	348	}
294	349	#endif
295	350
..	..	@@ -333,7 +388,6 @@
333	388	#endif /* ifdef DEBUG / else */
334	389
335	390	static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
336		-static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
337	391
338	392	static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
339	393	{
..	..	@@ -349,7 +403,7 @@
349	403	return;
350	404	}
351	405
352		- while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
	406	+ while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
353	407	unsigned long icr = readl(_ICR(i2c));
354	408
355	409	icr &= ~ICR_START;
..	..	@@ -370,19 +424,26 @@
370	424	static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
371	425	{
372	426	int timeout = DEF_TIMEOUT;
	427	+ u32 isr;
373	428
374		- while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB \| ISR_UB)) {
375		- if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
	429	+ while (1) {
	430	+ isr = readl(_ISR(i2c));
	431	+ if (!(isr & (ISR_IBB \| ISR_UB)))
	432	+ return 0;
	433	+
	434	+ if (isr & ISR_SAD)
376	435	timeout += 4;
	436	+
	437	+ if (!timeout--)
	438	+ break;
377	439
378	440	msleep(2);
379	441	show_state(i2c);
380	442	}
381	443
382		- if (timeout < 0)
383		- show_state(i2c);
	444	+ show_state(i2c);
384	445
385		- return timeout < 0 ? I2C_RETRY : 0;
	446	+ return I2C_RETRY;
386	447	}
387	448
388	449	static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
..	..	@@ -404,7 +465,8 @@
404	465	* quick check of the i2c lines themselves to ensure they've
405	466	* gone high...
406	467	*/
407		- if ((readl(_ISR(i2c)) & (ISR_UB \| ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
	468	+ if ((readl(_ISR(i2c)) & (ISR_UB \| ISR_IBB)) == 0 &&
	469	+ readl(_IBMR(i2c)) == (IBMR_SCLS \| IBMR_SDAS)) {
408	470	if (i2c_debug > 0)
409	471	dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
410	472	return 1;
..	..	@@ -504,13 +566,8 @@
504	566	#define i2c_pxa_set_slave(i2c, err) do { } while (0)
505	567	#endif
506	568
507		-static void i2c_pxa_reset(struct pxa_i2c *i2c)
	569	+static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
508	570	{
509		- pr_debug("Resetting I2C Controller Unit\n");
510		-
511		- /* abort any transfer currently under way */
512		- i2c_pxa_abort(i2c);
513		-
514	571	/* reset according to 9.8 */
515	572	writel(ICR_UR, _ICR(i2c));
516	573	writel(I2C_ISR_INIT, _ISR(i2c));
..	..	@@ -529,10 +586,23 @@
529	586	#endif
530	587
531	588	i2c_pxa_set_slave(i2c, 0);
	589	+}
532	590
	591	+static void i2c_pxa_enable(struct pxa_i2c *i2c)
	592	+{
533	593	/* enable unit */
534	594	writel(readl(_ICR(i2c)) \| ICR_IUE, _ICR(i2c));
535	595	udelay(100);
	596	+}
	597	+
	598	+static void i2c_pxa_reset(struct pxa_i2c *i2c)
	599	+{
	600	+ pr_debug("Resetting I2C Controller Unit\n");
	601	+
	602	+ /* abort any transfer currently under way */
	603	+ i2c_pxa_abort(i2c);
	604	+ i2c_pxa_do_reset(i2c);
	605	+ i2c_pxa_enable(i2c);
536	606	}
537	607
538	608
..	..	@@ -546,22 +616,23 @@
546	616	if (isr & ISR_BED) {
547	617	/* what should we do here? */
548	618	} else {
549		- int ret = 0;
	619	+ u8 byte = 0;
550	620
551	621	if (i2c->slave != NULL)
552		- ret = i2c->slave->read(i2c->slave->data);
	622	+ i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
	623	+ &byte);
553	624
554		- writel(ret, _IDBR(i2c));
	625	+ writel(byte, _IDBR(i2c));
555	626	writel(readl(_ICR(i2c)) \| ICR_TB, _ICR(i2c)); /* allow next byte */
556	627	}
557	628	}
558	629
559	630	static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
560	631	{
561		- unsigned int byte = readl(_IDBR(i2c));
	632	+ u8 byte = readl(_IDBR(i2c));
562	633
563	634	if (i2c->slave != NULL)
564		- i2c->slave->write(i2c->slave->data, byte);
	635	+ i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
565	636
566	637	writel(readl(_ICR(i2c)) \| ICR_TB, _ICR(i2c));
567	638	}
..	..	@@ -574,9 +645,18 @@
574	645	dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
575	646	(isr & ISR_RWM) ? 'r' : 't');
576	647
577		- if (i2c->slave != NULL)
578		- i2c->slave->event(i2c->slave->data,
579		- (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
	648	+ if (i2c->slave != NULL) {
	649	+ if (isr & ISR_RWM) {
	650	+ u8 byte = 0;
	651	+
	652	+ i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
	653	+ &byte);
	654	+ writel(byte, _IDBR(i2c));
	655	+ } else {
	656	+ i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
	657	+ NULL);
	658	+ }
	659	+ }
580	660
581	661	/*
582	662	* slave could interrupt in the middle of us generating a
..	..	@@ -589,7 +669,7 @@
589	669	timeout = 0x10000;
590	670
591	671	while (1) {
592		- if ((readl(_IBMR(i2c)) & 2) == 2)
	672	+ if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
593	673	break;
594	674
595	675	timeout--;
..	..	@@ -609,7 +689,7 @@
609	689	dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
610	690
611	691	if (i2c->slave != NULL)
612		- i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
	692	+ i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
613	693
614	694	if (i2c_debug > 2)
615	695	dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
..	..	@@ -620,6 +700,38 @@
620	700	*/
621	701	if (i2c->msg)
622	702	i2c_pxa_master_complete(i2c, I2C_RETRY);
	703	+}
	704	+
	705	+static int i2c_pxa_slave_reg(struct i2c_client *slave)
	706	+{
	707	+ struct pxa_i2c *i2c = slave->adapter->algo_data;
	708	+
	709	+ if (i2c->slave)
	710	+ return -EBUSY;
	711	+
	712	+ if (!i2c->reg_isar)
	713	+ return -EAFNOSUPPORT;
	714	+
	715	+ i2c->slave = slave;
	716	+ i2c->slave_addr = slave->addr;
	717	+
	718	+ writel(i2c->slave_addr, _ISAR(i2c));
	719	+
	720	+ return 0;
	721	+}
	722	+
	723	+static int i2c_pxa_slave_unreg(struct i2c_client *slave)
	724	+{
	725	+ struct pxa_i2c *i2c = slave->adapter->algo_data;
	726	+
	727	+ WARN_ON(!i2c->slave);
	728	+
	729	+ i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
	730	+ writel(i2c->slave_addr, _ISAR(i2c));
	731	+
	732	+ i2c->slave = NULL;
	733	+
	734	+ return 0;
623	735	}
624	736	#else
625	737	static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
..	..	@@ -652,7 +764,7 @@
652	764	timeout = 0x10000;
653	765
654	766	while (1) {
655		- if ((readl(_IBMR(i2c)) & 2) == 2)
	767	+ if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
656	768	break;
657	769
658	770	timeout--;
..	..	@@ -677,16 +789,6 @@
677	789	* PXA I2C Master mode
678	790	*/
679	791
680		-static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
681		-{
682		- unsigned int addr = (msg->addr & 0x7f) << 1;
683		-
684		- if (msg->flags & I2C_M_RD)
685		- addr \|= 1;
686		-
687		- return addr;
688		-}
689		-
690	792	static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
691	793	{
692	794	u32 icr;
..	..	@@ -694,8 +796,8 @@
694	796	/*
695	797	* Step 1: target slave address into IDBR
696	798	*/
697		- writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
698		- i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
	799	+ i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
	800	+ writel(i2c->req_slave_addr, _IDBR(i2c));
699	801
700	802	/*
701	803	* Step 2: initiate the write.
..	..	@@ -712,34 +814,6 @@
712	814	icr = readl(_ICR(i2c));
713	815	icr &= ~(ICR_START \| ICR_STOP \| ICR_ACKNAK \| ICR_TB \| ICR_MA);
714	816	writel(icr, _ICR(i2c));
715		-}
716		-
717		-static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
718		-{
719		- /* make timeout the same as for interrupt based functions */
720		- long timeout = 2 * DEF_TIMEOUT;
721		-
722		- /*
723		- * Wait for the bus to become free.
724		- */
725		- while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB \| ISR_UB)) {
726		- udelay(1000);
727		- show_state(i2c);
728		- }
729		-
730		- if (timeout < 0) {
731		- show_state(i2c);
732		- dev_err(&i2c->adap.dev,
733		- "i2c_pxa: timeout waiting for bus free\n");
734		- return I2C_RETRY;
735		- }
736		-
737		- /*
738		- * Set master mode.
739		- */
740		- writel(readl(_ICR(i2c)) \| ICR_SCLE, _ICR(i2c));
741		-
742		- return 0;
743	817	}
744	818
745	819	/*
..	..	@@ -768,140 +842,6 @@
768	842	i2c->highmode_enter = false;
769	843
770	844	return (timeout == 0) ? I2C_RETRY : 0;
771		-}
772		-
773		-static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
774		- struct i2c_msg *msg, int num)
775		-{
776		- unsigned long timeout = 500000; /* 5 seconds */
777		- int ret = 0;
778		-
779		- ret = i2c_pxa_pio_set_master(i2c);
780		- if (ret)
781		- goto out;
782		-
783		- i2c->msg = msg;
784		- i2c->msg_num = num;
785		- i2c->msg_idx = 0;
786		- i2c->msg_ptr = 0;
787		- i2c->irqlogidx = 0;
788		-
789		- i2c_pxa_start_message(i2c);
790		-
791		- while (i2c->msg_num > 0 && --timeout) {
792		- i2c_pxa_handler(0, i2c);
793		- udelay(10);
794		- }
795		-
796		- i2c_pxa_stop_message(i2c);
797		-
798		- /*
799		- * We place the return code in i2c->msg_idx.
800		- */
801		- ret = i2c->msg_idx;
802		-
803		-out:
804		- if (timeout == 0) {
805		- i2c_pxa_scream_blue_murder(i2c, "timeout");
806		- ret = I2C_RETRY;
807		- }
808		-
809		- return ret;
810		-}
811		-
812		-/*
813		- * We are protected by the adapter bus mutex.
814		- */
815		-static int i2c_pxa_do_xfer(struct pxa_i2c i2c, struct i2c_msg msg, int num)
816		-{
817		- long timeout;
818		- int ret;
819		-
820		- /*
821		- * Wait for the bus to become free.
822		- */
823		- ret = i2c_pxa_wait_bus_not_busy(i2c);
824		- if (ret) {
825		- dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
826		- goto out;
827		- }
828		-
829		- /*
830		- * Set master mode.
831		- */
832		- ret = i2c_pxa_set_master(i2c);
833		- if (ret) {
834		- dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
835		- goto out;
836		- }
837		-
838		- if (i2c->high_mode) {
839		- ret = i2c_pxa_send_mastercode(i2c);
840		- if (ret) {
841		- dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
842		- goto out;
843		- }
844		- }
845		-
846		- spin_lock_irq(&i2c->lock);
847		-
848		- i2c->msg = msg;
849		- i2c->msg_num = num;
850		- i2c->msg_idx = 0;
851		- i2c->msg_ptr = 0;
852		- i2c->irqlogidx = 0;
853		-
854		- i2c_pxa_start_message(i2c);
855		-
856		- spin_unlock_irq(&i2c->lock);
857		-
858		- /*
859		- * The rest of the processing occurs in the interrupt handler.
860		- */
861		- timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
862		- i2c_pxa_stop_message(i2c);
863		-
864		- /*
865		- * We place the return code in i2c->msg_idx.
866		- */
867		- ret = i2c->msg_idx;
868		-
869		- if (!timeout && i2c->msg_num) {
870		- i2c_pxa_scream_blue_murder(i2c, "timeout");
871		- ret = I2C_RETRY;
872		- }
873		-
874		- out:
875		- return ret;
876		-}
877		-
878		-static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
879		- struct i2c_msg msgs[], int num)
880		-{
881		- struct pxa_i2c *i2c = adap->algo_data;
882		- int ret, i;
883		-
884		- /* If the I2C controller is disabled we need to reset it
885		- (probably due to a suspend/resume destroying state). We do
886		- this here as we can then avoid worrying about resuming the
887		- controller before its users. */
888		- if (!(readl(_ICR(i2c)) & ICR_IUE))
889		- i2c_pxa_reset(i2c);
890		-
891		- for (i = adap->retries; i >= 0; i--) {
892		- ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
893		- if (ret != I2C_RETRY)
894		- goto out;
895		-
896		- if (i2c_debug)
897		- dev_dbg(&adap->dev, "Retrying transmission\n");
898		- udelay(100);
899		- }
900		- i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
901		- ret = -EREMOTEIO;
902		- out:
903		- i2c_pxa_set_slave(i2c, ret);
904		- return ret;
905	845	}
906	846
907	847	/*
..	..	@@ -955,7 +895,7 @@
955	895	*/
956	896	if (isr & ISR_ACKNAK) {
957	897	if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
958		- ret = I2C_RETRY;
	898	+ ret = NO_SLAVE;
959	899	else
960	900	ret = XFER_NAKED;
961	901	}
..	..	@@ -1006,8 +946,8 @@
1006	946	/*
1007	947	* Write the next address.
1008	948	*/
1009		- writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
1010		- i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
	949	+ i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
	950	+ writel(i2c->req_slave_addr, _IDBR(i2c));
1011	951
1012	952	/*
1013	953	* And trigger a repeated start, and send the byte.
..	..	@@ -1015,14 +955,8 @@
1015	955	icr &= ~ICR_ALDIE;
1016	956	icr \|= ICR_START \| ICR_TB;
1017	957	} else {
1018		- if (i2c->msg->len == 0) {
1019		- /*
1020		- * Device probes have a message length of zero
1021		- * and need the bus to be reset before it can
1022		- * be used again.
1023		- */
1024		- i2c_pxa_reset(i2c);
1025		- }
	958	+ if (i2c->msg->len == 0)
	959	+ icr \|= ICR_MA;
1026	960	i2c_pxa_master_complete(i2c, 0);
1027	961	}
1028	962
..	..	@@ -1110,26 +1044,106 @@
1110	1044	return IRQ_HANDLED;
1111	1045	}
1112	1046
1113		-
1114		-static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
	1047	+/*
	1048	+ * We are protected by the adapter bus mutex.
	1049	+ */
	1050	+static int i2c_pxa_do_xfer(struct pxa_i2c i2c, struct i2c_msg msg, int num)
1115	1051	{
1116		- struct pxa_i2c *i2c = adap->algo_data;
	1052	+ long timeout;
	1053	+ int ret;
	1054	+
	1055	+ /*
	1056	+ * Wait for the bus to become free.
	1057	+ */
	1058	+ ret = i2c_pxa_wait_bus_not_busy(i2c);
	1059	+ if (ret) {
	1060	+ dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
	1061	+ i2c_recover_bus(&i2c->adap);
	1062	+ goto out;
	1063	+ }
	1064	+
	1065	+ /*
	1066	+ * Set master mode.
	1067	+ */
	1068	+ ret = i2c_pxa_set_master(i2c);
	1069	+ if (ret) {
	1070	+ dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
	1071	+ goto out;
	1072	+ }
	1073	+
	1074	+ if (i2c->high_mode) {
	1075	+ ret = i2c_pxa_send_mastercode(i2c);
	1076	+ if (ret) {
	1077	+ dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
	1078	+ goto out;
	1079	+ }
	1080	+ }
	1081	+
	1082	+ spin_lock_irq(&i2c->lock);
	1083	+
	1084	+ i2c->msg = msg;
	1085	+ i2c->msg_num = num;
	1086	+ i2c->msg_idx = 0;
	1087	+ i2c->msg_ptr = 0;
	1088	+ i2c->irqlogidx = 0;
	1089	+
	1090	+ i2c_pxa_start_message(i2c);
	1091	+
	1092	+ spin_unlock_irq(&i2c->lock);
	1093	+
	1094	+ /*
	1095	+ * The rest of the processing occurs in the interrupt handler.
	1096	+ */
	1097	+ timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
	1098	+ i2c_pxa_stop_message(i2c);
	1099	+
	1100	+ /*
	1101	+ * We place the return code in i2c->msg_idx.
	1102	+ */
	1103	+ ret = i2c->msg_idx;
	1104	+
	1105	+ if (!timeout && i2c->msg_num) {
	1106	+ i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
	1107	+ i2c_recover_bus(&i2c->adap);
	1108	+ ret = I2C_RETRY;
	1109	+ }
	1110	+
	1111	+ out:
	1112	+ return ret;
	1113	+}
	1114	+
	1115	+static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
	1116	+ struct i2c_msg *msgs, int num,
	1117	+ int (xfer)(struct pxa_i2c ,
	1118	+ struct i2c_msg *, int num))
	1119	+{
1117	1120	int ret, i;
1118	1121
1119		- for (i = adap->retries; i >= 0; i--) {
1120		- ret = i2c_pxa_do_xfer(i2c, msgs, num);
1121		- if (ret != I2C_RETRY)
	1122	+ for (i = 0; ; ) {
	1123	+ ret = xfer(i2c, msgs, num);
	1124	+ if (ret != I2C_RETRY && ret != NO_SLAVE)
1122	1125	goto out;
	1126	+ if (++i >= i2c->adap.retries)
	1127	+ break;
1123	1128
1124	1129	if (i2c_debug)
1125		- dev_dbg(&adap->dev, "Retrying transmission\n");
	1130	+ dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1126	1131	udelay(100);
1127	1132	}
1128		- i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
	1133	+ if (ret != NO_SLAVE)
	1134	+ i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1129	1135	ret = -EREMOTEIO;
1130	1136	out:
1131	1137	i2c_pxa_set_slave(i2c, ret);
1132	1138	return ret;
	1139	+}
	1140	+
	1141	+static int i2c_pxa_xfer(struct i2c_adapter *adap,
	1142	+ struct i2c_msg msgs[], int num)
	1143	+{
	1144	+ struct pxa_i2c *i2c = adap->algo_data;
	1145	+
	1146	+ return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1133	1147	}
1134	1148
1135	1149	static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
..	..	@@ -1141,21 +1155,101 @@
1141	1155	static const struct i2c_algorithm i2c_pxa_algorithm = {
1142	1156	.master_xfer = i2c_pxa_xfer,
1143	1157	.functionality = i2c_pxa_functionality,
	1158	+#ifdef CONFIG_I2C_PXA_SLAVE
	1159	+ .reg_slave = i2c_pxa_slave_reg,
	1160	+ .unreg_slave = i2c_pxa_slave_unreg,
	1161	+#endif
1144	1162	};
	1163	+
	1164	+/* Non-interrupt mode support */
	1165	+static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
	1166	+{
	1167	+ /* make timeout the same as for interrupt based functions */
	1168	+ long timeout = 2 * DEF_TIMEOUT;
	1169	+
	1170	+ /*
	1171	+ * Wait for the bus to become free.
	1172	+ */
	1173	+ while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB \| ISR_UB))
	1174	+ udelay(1000);
	1175	+
	1176	+ if (timeout < 0) {
	1177	+ show_state(i2c);
	1178	+ dev_err(&i2c->adap.dev,
	1179	+ "i2c_pxa: timeout waiting for bus free (set_master)\n");
	1180	+ return I2C_RETRY;
	1181	+ }
	1182	+
	1183	+ /*
	1184	+ * Set master mode.
	1185	+ */
	1186	+ writel(readl(_ICR(i2c)) \| ICR_SCLE, _ICR(i2c));
	1187	+
	1188	+ return 0;
	1189	+}
	1190	+
	1191	+static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
	1192	+ struct i2c_msg *msg, int num)
	1193	+{
	1194	+ unsigned long timeout = 500000; /* 5 seconds */
	1195	+ int ret = 0;
	1196	+
	1197	+ ret = i2c_pxa_pio_set_master(i2c);
	1198	+ if (ret)
	1199	+ goto out;
	1200	+
	1201	+ i2c->msg = msg;
	1202	+ i2c->msg_num = num;
	1203	+ i2c->msg_idx = 0;
	1204	+ i2c->msg_ptr = 0;
	1205	+ i2c->irqlogidx = 0;
	1206	+
	1207	+ i2c_pxa_start_message(i2c);
	1208	+
	1209	+ while (i2c->msg_num > 0 && --timeout) {
	1210	+ i2c_pxa_handler(0, i2c);
	1211	+ udelay(10);
	1212	+ }
	1213	+
	1214	+ i2c_pxa_stop_message(i2c);
	1215	+
	1216	+ /*
	1217	+ * We place the return code in i2c->msg_idx.
	1218	+ */
	1219	+ ret = i2c->msg_idx;
	1220	+
	1221	+out:
	1222	+ if (timeout == 0) {
	1223	+ i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
	1224	+ ret = I2C_RETRY;
	1225	+ }
	1226	+
	1227	+ return ret;
	1228	+}
	1229	+
	1230	+static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
	1231	+ struct i2c_msg msgs[], int num)
	1232	+{
	1233	+ struct pxa_i2c *i2c = adap->algo_data;
	1234	+
	1235	+ /* If the I2C controller is disabled we need to reset it
	1236	+ (probably due to a suspend/resume destroying state). We do
	1237	+ this here as we can then avoid worrying about resuming the
	1238	+ controller before its users. */
	1239	+ if (!(readl(_ICR(i2c)) & ICR_IUE))
	1240	+ i2c_pxa_reset(i2c);
	1241	+
	1242	+ return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
	1243	+}
1145	1244
1146	1245	static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1147	1246	.master_xfer = i2c_pxa_pio_xfer,
1148	1247	.functionality = i2c_pxa_functionality,
	1248	+#ifdef CONFIG_I2C_PXA_SLAVE
	1249	+ .reg_slave = i2c_pxa_slave_reg,
	1250	+ .unreg_slave = i2c_pxa_slave_unreg,
	1251	+#endif
1149	1252	};
1150		-
1151		-static const struct of_device_id i2c_pxa_dt_ids[] = {
1152		- { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1153		- { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1154		- { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1155		- { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
1156		- {}
1157		-};
1158		-MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1159	1253
1160	1254	static int i2c_pxa_probe_dt(struct platform_device pdev, struct pxa_i2c i2c,
1161	1255	enum pxa_i2c_types *i2c_types)
..	..	@@ -1200,6 +1294,131 @@
1200	1294	return 0;
1201	1295	}
1202	1296
	1297	+static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
	1298	+{
	1299	+ struct pxa_i2c *i2c = adap->algo_data;
	1300	+ u32 ibmr = readl(_IBMR(i2c));
	1301	+
	1302	+ /*
	1303	+ * Program the GPIOs to reflect the current I2C bus state while
	1304	+ * we transition to recovery; this avoids glitching the bus.
	1305	+ */
	1306	+ gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
	1307	+ gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
	1308	+
	1309	+ WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
	1310	+}
	1311	+
	1312	+static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
	1313	+{
	1314	+ struct pxa_i2c *i2c = adap->algo_data;
	1315	+ u32 isr;
	1316	+
	1317	+ /*
	1318	+ * The bus should now be free. Clear up the I2C controller before
	1319	+ * handing control of the bus back to avoid the bus changing state.
	1320	+ */
	1321	+ isr = readl(_ISR(i2c));
	1322	+ if (isr & (ISR_UB \| ISR_IBB)) {
	1323	+ dev_dbg(&i2c->adap.dev,
	1324	+ "recovery: resetting controller, ISR=0x%08x\n", isr);
	1325	+ i2c_pxa_do_reset(i2c);
	1326	+ }
	1327	+
	1328	+ WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
	1329	+
	1330	+ dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
	1331	+ readl(_IBMR(i2c)), readl(_ISR(i2c)));
	1332	+
	1333	+ i2c_pxa_enable(i2c);
	1334	+}
	1335	+
	1336	+static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
	1337	+{
	1338	+ struct i2c_bus_recovery_info *bri = &i2c->recovery;
	1339	+ struct device *dev = i2c->adap.dev.parent;
	1340	+
	1341	+ /*
	1342	+ * When slave mode is enabled, we are not the only master on the bus.
	1343	+ * Bus recovery can only be performed when we are the master, which
	1344	+ * we can't be certain of. Therefore, when slave mode is enabled, do
	1345	+ * not configure bus recovery.
	1346	+ */
	1347	+ if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
	1348	+ return 0;
	1349	+
	1350	+ i2c->pinctrl = devm_pinctrl_get(dev);
	1351	+ if (PTR_ERR(i2c->pinctrl) == -ENODEV)
	1352	+ i2c->pinctrl = NULL;
	1353	+ if (IS_ERR(i2c->pinctrl))
	1354	+ return PTR_ERR(i2c->pinctrl);
	1355	+
	1356	+ if (!i2c->pinctrl)
	1357	+ return 0;
	1358	+
	1359	+ i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
	1360	+ PINCTRL_STATE_DEFAULT);
	1361	+ i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
	1362	+
	1363	+ if (IS_ERR(i2c->pinctrl_default) \|\| IS_ERR(i2c->pinctrl_recovery)) {
	1364	+ dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
	1365	+ PTR_ERR(i2c->pinctrl_default),
	1366	+ PTR_ERR(i2c->pinctrl_recovery));
	1367	+ return 0;
	1368	+ }
	1369	+
	1370	+ /*
	1371	+ * Claiming GPIOs can influence the pinmux state, and may glitch the
	1372	+ * I2C bus. Do this carefully.
	1373	+ */
	1374	+ bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
	1375	+ if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
	1376	+ return -EPROBE_DEFER;
	1377	+ if (IS_ERR(bri->scl_gpiod)) {
	1378	+ dev_info(dev, "missing scl gpio recovery information: %pe\n",
	1379	+ bri->scl_gpiod);
	1380	+ return 0;
	1381	+ }
	1382	+
	1383	+ /*
	1384	+ * We have SCL. Pull SCL low and wait a bit so that SDA glitches
	1385	+ * have no effect.
	1386	+ */
	1387	+ gpiod_direction_output(bri->scl_gpiod, 0);
	1388	+ udelay(10);
	1389	+ bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
	1390	+
	1391	+ /* Wait a bit in case of a SDA glitch, and then release SCL. */
	1392	+ udelay(10);
	1393	+ gpiod_direction_output(bri->scl_gpiod, 1);
	1394	+
	1395	+ if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
	1396	+ return -EPROBE_DEFER;
	1397	+
	1398	+ if (IS_ERR(bri->sda_gpiod)) {
	1399	+ dev_info(dev, "missing sda gpio recovery information: %pe\n",
	1400	+ bri->sda_gpiod);
	1401	+ return 0;
	1402	+ }
	1403	+
	1404	+ bri->prepare_recovery = i2c_pxa_prepare_recovery;
	1405	+ bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
	1406	+ bri->recover_bus = i2c_generic_scl_recovery;
	1407	+
	1408	+ i2c->adap.bus_recovery_info = bri;
	1409	+
	1410	+ /*
	1411	+ * Claiming GPIOs can change the pinmux state, which confuses the
	1412	+ * pinctrl since pinctrl's idea of the current setting is unaffected
	1413	+ * by the pinmux change caused by claiming the GPIO. Work around that
	1414	+ * by switching pinctrl to the GPIO state here. We do it this way to
	1415	+ * avoid glitching the I2C bus.
	1416	+ */
	1417	+ pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
	1418	+
	1419	+ return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
	1420	+}
	1421	+
1203	1422	static int i2c_pxa_probe(struct platform_device *dev)
1204	1423	{
1205	1424	struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
..	..	@@ -1212,28 +1431,34 @@
1212	1431	if (!i2c)
1213	1432	return -ENOMEM;
1214	1433
	1434	+ /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
	1435	+ i2c->adap.nr = dev->id;
	1436	+ i2c->adap.owner = THIS_MODULE;
	1437	+ i2c->adap.retries = 5;
	1438	+ i2c->adap.algo_data = i2c;
	1439	+ i2c->adap.dev.parent = &dev->dev;
	1440	+#ifdef CONFIG_OF
	1441	+ i2c->adap.dev.of_node = dev->dev.of_node;
	1442	+#endif
	1443	+
1215	1444	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1216	1445	i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1217	1446	if (IS_ERR(i2c->reg_base))
1218	1447	return PTR_ERR(i2c->reg_base);
1219	1448
1220	1449	irq = platform_get_irq(dev, 0);
1221		- if (irq < 0) {
1222		- dev_err(&dev->dev, "no irq resource: %d\n", irq);
	1450	+ if (irq < 0)
1223	1451	return irq;
1224		- }
1225	1452
1226		- /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1227		- i2c->adap.nr = dev->id;
	1453	+ ret = i2c_pxa_init_recovery(i2c);
	1454	+ if (ret)
	1455	+ return ret;
1228	1456
1229	1457	ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1230	1458	if (ret > 0)
1231	1459	ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1232	1460	if (ret < 0)
1233	1461	return ret;
1234		-
1235		- i2c->adap.owner = THIS_MODULE;
1236		- i2c->adap.retries = 5;
1237	1462
1238	1463	spin_lock_init(&i2c->lock);
1239	1464	init_waitqueue_head(&i2c->wait);
..	..	@@ -1250,8 +1475,8 @@
1250	1475	i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1251	1476	i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1252	1477	i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1253		- i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM;
1254		- i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS;
	1478	+ i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
	1479	+ i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1255	1480
1256	1481	if (i2c_type != REGS_CE4100)
1257	1482	i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
..	..	@@ -1270,10 +1495,6 @@
1270	1495	i2c->highmode_enter = false;
1271	1496
1272	1497	if (plat) {
1273		-#ifdef CONFIG_I2C_PXA_SLAVE
1274		- i2c->slave_addr = plat->slave_addr;
1275		- i2c->slave = plat->slave;
1276		-#endif
1277	1498	i2c->adap.class = plat->class;
1278	1499	}
1279	1500
..	..	@@ -1303,12 +1524,6 @@
1303	1524	}
1304	1525
1305	1526	i2c_pxa_reset(i2c);
1306		-
1307		- i2c->adap.algo_data = i2c;
1308		- i2c->adap.dev.parent = &dev->dev;
1309		-#ifdef CONFIG_OF
1310		- i2c->adap.dev.of_node = dev->dev.of_node;
1311		-#endif
1312	1527
1313	1528	ret = i2c_add_numbered_adapter(&i2c->adap);
1314	1529	if (ret < 0)