forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/i2c/busses/i2c-designware-master.c
....@@ -18,6 +18,7 @@
1818 #include <linux/io.h>
1919 #include <linux/module.h>
2020 #include <linux/pm_runtime.h>
21
+#include <linux/regmap.h>
2122 #include <linux/reset.h>
2223 
2324 #include "i2c-designware-core.h"
....@@ -25,11 +26,11 @@
2526 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
2627 {
2728 	/* Configure Tx/Rx FIFO threshold levels */
28
-	dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
29
-	dw_writel(dev, 0, DW_IC_RX_TL);
29
+	regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
30
+	regmap_write(dev->map, DW_IC_RX_TL, 0);
3031 
3132 	/* Configure the I2C master */
32
-	dw_writel(dev, dev->master_cfg, DW_IC_CON);
33
+	regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
3334 }
3435 
3536 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
....@@ -44,8 +45,11 @@
4445 	ret = i2c_dw_acquire_lock(dev);
4546 	if (ret)
4647 		return ret;
47
-	comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
48
+
49
+	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
4850 	i2c_dw_release_lock(dev);
51
+	if (ret)
52
+		return ret;
4953 
5054 	/* Set standard and fast speed dividers for high/low periods */
5155 	sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
....@@ -76,14 +80,27 @@
7680 	 */
7781 	if (t->bus_freq_hz == 1000000) {
7882 		/*
79
-		 * Check are fast mode plus parameters available and use
80
-		 * fast mode if not.
83
+		 * Check are Fast Mode Plus parameters available. Calculate
84
+		 * SCL timing parameters for Fast Mode Plus if not set.
8185 		 */
8286 		if (dev->fp_hcnt && dev->fp_lcnt) {
8387 			dev->fs_hcnt = dev->fp_hcnt;
8488 			dev->fs_lcnt = dev->fp_lcnt;
85
-			fp_str = " Plus";
89
+		} else {
90
+			ic_clk = i2c_dw_clk_rate(dev);
91
+			dev->fs_hcnt =
92
+				i2c_dw_scl_hcnt(ic_clk,
93
+						260,	/* tHIGH = 260 ns */
94
+						sda_falling_time,
95
+						0,	/* DW default */
96
+						0);	/* No offset */
97
+			dev->fs_lcnt =
98
+				i2c_dw_scl_lcnt(ic_clk,
99
+						500,	/* tLOW = 500 ns */
100
+						scl_falling_time,
101
+						0);	/* No offset */
86102 		}
103
+		fp_str = " Plus";
87104 	}
88105 	/*
89106 	 * Calculate SCL timing parameters for fast mode if not set. They are
....@@ -112,14 +129,27 @@
112129 		if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
113130 			!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
114131 			dev_err(dev->dev, "High Speed not supported!\n");
132
+			t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
115133 			dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
116134 			dev->master_cfg |= DW_IC_CON_SPEED_FAST;
117135 			dev->hs_hcnt = 0;
118136 			dev->hs_lcnt = 0;
119
-		} else if (dev->hs_hcnt && dev->hs_lcnt) {
120
-			dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
121
-				dev->hs_hcnt, dev->hs_lcnt);
137
+		} else if (!dev->hs_hcnt || !dev->hs_lcnt) {
138
+			ic_clk = i2c_dw_clk_rate(dev);
139
+			dev->hs_hcnt =
140
+				i2c_dw_scl_hcnt(ic_clk,
141
+						160,	/* tHIGH = 160 ns */
142
+						sda_falling_time,
143
+						0,	/* DW default */
144
+						0);	/* No offset */
145
+			dev->hs_lcnt =
146
+				i2c_dw_scl_lcnt(ic_clk,
147
+						320,	/* tLOW = 320 ns */
148
+						scl_falling_time,
149
+						0);	/* No offset */
122150 		}
151
+		dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
152
+			dev->hs_hcnt, dev->hs_lcnt);
123153 	}
124154 
125155 	ret = i2c_dw_set_sda_hold(dev);
....@@ -162,22 +192,22 @@
162192 	__i2c_dw_disable(dev);
163193 
164194 	/* Write standard speed timing parameters */
165
-	dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
166
-	dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
195
+	regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
196
+	regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
167197 
168198 	/* Write fast mode/fast mode plus timing parameters */
169
-	dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
170
-	dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
199
+	regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
200
+	regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
171201 
172202 	/* Write high speed timing parameters if supported */
173203 	if (dev->hs_hcnt && dev->hs_lcnt) {
174
-		dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
175
-		dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
204
+		regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
205
+		regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
176206 	}
177207 
178208 	/* Write SDA hold time if supported */
179209 	if (dev->sda_hold_time)
180
-		dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
210
+		regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
181211 
182212 	i2c_dw_configure_fifo_master(dev);
183213 	i2c_dw_release_lock(dev);
....@@ -188,15 +218,15 @@
188218 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
189219 {
190220 	struct i2c_msg *msgs = dev->msgs;
191
-	u32 ic_con, ic_tar = 0;
221
+	u32 ic_con = 0, ic_tar = 0;
222
+	u32 dummy;
192223 
193224 	/* Disable the adapter */
194225 	__i2c_dw_disable(dev);
195226 
196227 	/* If the slave address is ten bit address, enable 10BITADDR */
197
-	ic_con = dw_readl(dev, DW_IC_CON);
198228 	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
199
-		ic_con |= DW_IC_CON_10BITADDR_MASTER;
229
+		ic_con = DW_IC_CON_10BITADDR_MASTER;
200230 		/*
201231 		 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
202232 		 * mode has to be enabled via bit 12 of IC_TAR register.
....@@ -204,17 +234,17 @@
204234 		 * detected from registers.
205235 		 */
206236 		ic_tar = DW_IC_TAR_10BITADDR_MASTER;
207
-	} else {
208
-		ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
209237 	}
210238 
211
-	dw_writel(dev, ic_con, DW_IC_CON);
239
+	regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
240
+			   ic_con);
212241 
213242 	/*
214243 	 * Set the slave (target) address and enable 10-bit addressing mode
215244 	 * if applicable.
216245 	 */
217
-	dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
246
+	regmap_write(dev->map, DW_IC_TAR,
247
+		     msgs[dev->msg_write_idx].addr | ic_tar);
218248 
219249 	/* Enforce disabled interrupts (due to HW issues) */
220250 	i2c_dw_disable_int(dev);
....@@ -223,11 +253,11 @@
223253 	__i2c_dw_enable(dev);
224254 
225255 	/* Dummy read to avoid the register getting stuck on Bay Trail */
226
-	dw_readl(dev, DW_IC_ENABLE_STATUS);
256
+	regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
227257 
228258 	/* Clear and enable interrupts */
229
-	dw_readl(dev, DW_IC_CLR_INTR);
230
-	dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
259
+	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
260
+	regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
231261 }
232262 
233263 /*
....@@ -246,6 +276,7 @@
246276 	u32 buf_len = dev->tx_buf_len;
247277 	u8 *buf = dev->tx_buf;
248278 	bool need_restart = false;
279
+	unsigned int flr;
249280 
250281 	intr_mask = DW_IC_INTR_MASTER_MASK;
251282 
....@@ -278,8 +309,11 @@
278309 				need_restart = true;
279310 		}
280311 
281
-		tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
282
-		rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
312
+		regmap_read(dev->map, DW_IC_TXFLR, &flr);
313
+		tx_limit = dev->tx_fifo_depth - flr;
314
+
315
+		regmap_read(dev->map, DW_IC_RXFLR, &flr);
316
+		rx_limit = dev->rx_fifo_depth - flr;
283317 
284318 		while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
285319 			u32 cmd = 0;
....@@ -312,11 +346,14 @@
312346 				if (dev->rx_outstanding >= dev->rx_fifo_depth)
313347 					break;
314348 
315
-				dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
349
+				regmap_write(dev->map, DW_IC_DATA_CMD,
350
+					     cmd | 0x100);
316351 				rx_limit--;
317352 				dev->rx_outstanding++;
318
-			} else
319
-				dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
353
+			} else {
354
+				regmap_write(dev->map, DW_IC_DATA_CMD,
355
+					     cmd | *buf++);
356
+			}
320357 			tx_limit--; buf_len--;
321358 		}
322359 
....@@ -346,7 +383,7 @@
346383 	if (dev->msg_err)
347384 		intr_mask = 0;
348385 
349
-	dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
386
+	regmap_write(dev->map,  DW_IC_INTR_MASK, intr_mask);
350387 }
351388 
352389 static u8
....@@ -371,10 +408,10 @@
371408 i2c_dw_read(struct dw_i2c_dev *dev)
372409 {
373410 	struct i2c_msg *msgs = dev->msgs;
374
-	int rx_valid;
411
+	unsigned int rx_valid;
375412 
376413 	for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
377
-		u32 len;
414
+		u32 len, tmp;
378415 		u8 *buf;
379416 
380417 		if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
....@@ -388,18 +425,29 @@
388425 			buf = dev->rx_buf;
389426 		}
390427 
391
-		rx_valid = dw_readl(dev, DW_IC_RXFLR);
428
+		regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
392429 
393430 		for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
394431 			u32 flags = msgs[dev->msg_read_idx].flags;
395432 
396
-			*buf = dw_readl(dev, DW_IC_DATA_CMD);
433
+			regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
397434 			/* Ensure length byte is a valid value */
398
-			if (flags & I2C_M_RECV_LEN &&
399
-				*buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
400
-				len = i2c_dw_recv_len(dev, *buf);
435
+			if (flags & I2C_M_RECV_LEN) {
436
+				/*
437
+				 * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be
438
+				 * detected from the registers, the controller can be
439
+				 * disabled if the STOP bit is set. But it is only set
440
+				 * after receiving block data response length in
441
+				 * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read
442
+				 * another byte with STOP bit set when the block data
443
+				 * response length is invalid to complete the transaction.
444
+				 */
445
+				if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX)
446
+					tmp = 1;
447
+
448
+				len = i2c_dw_recv_len(dev, tmp);
401449 			}
402
-			buf++;
450
+			*buf++ = tmp;
403451 			dev->rx_outstanding--;
404452 		}
405453 
....@@ -425,6 +473,11 @@
425473 	dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
426474 
427475 	pm_runtime_get_sync(dev->dev);
476
+
477
+	if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
478
+		ret = -ESHUTDOWN;
479
+		goto done_nolock;
480
+	}
428481 
429482 	reinit_completion(&dev->cmd_complete);
430483 	dev->msgs = msgs;
....@@ -512,55 +565,55 @@
512565 
513566 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
514567 {
515
-	u32 stat;
568
+	u32 stat, dummy;
516569 
517570 	/*
518571 	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
519
-	 * Ths unmasked raw version of interrupt status bits are available
572
+	 * The unmasked raw version of interrupt status bits is available
520573 	 * in the IC_RAW_INTR_STAT register.
521574 	 *
522575 	 * That is,
523
-	 *   stat = dw_readl(IC_INTR_STAT);
576
+	 *   stat = readl(IC_INTR_STAT);
524577 	 * equals to,
525
-	 *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
578
+	 *   stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
526579 	 *
527580 	 * The raw version might be useful for debugging purposes.
528581 	 */
529
-	stat = dw_readl(dev, DW_IC_INTR_STAT);
582
+	regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
530583 
531584 	/*
532585 	 * Do not use the IC_CLR_INTR register to clear interrupts, or
533586 	 * you'll miss some interrupts, triggered during the period from
534
-	 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
587
+	 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
535588 	 *
536589 	 * Instead, use the separately-prepared IC_CLR_* registers.
537590 	 */
538591 	if (stat & DW_IC_INTR_RX_UNDER)
539
-		dw_readl(dev, DW_IC_CLR_RX_UNDER);
592
+		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
540593 	if (stat & DW_IC_INTR_RX_OVER)
541
-		dw_readl(dev, DW_IC_CLR_RX_OVER);
594
+		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
542595 	if (stat & DW_IC_INTR_TX_OVER)
543
-		dw_readl(dev, DW_IC_CLR_TX_OVER);
596
+		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
544597 	if (stat & DW_IC_INTR_RD_REQ)
545
-		dw_readl(dev, DW_IC_CLR_RD_REQ);
598
+		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
546599 	if (stat & DW_IC_INTR_TX_ABRT) {
547600 		/*
548601 		 * The IC_TX_ABRT_SOURCE register is cleared whenever
549602 		 * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
550603 		 */
551
-		dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
552
-		dw_readl(dev, DW_IC_CLR_TX_ABRT);
604
+		regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
605
+		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
553606 	}
554607 	if (stat & DW_IC_INTR_RX_DONE)
555
-		dw_readl(dev, DW_IC_CLR_RX_DONE);
608
+		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
556609 	if (stat & DW_IC_INTR_ACTIVITY)
557
-		dw_readl(dev, DW_IC_CLR_ACTIVITY);
610
+		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
558611 	if (stat & DW_IC_INTR_STOP_DET)
559
-		dw_readl(dev, DW_IC_CLR_STOP_DET);
612
+		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
560613 	if (stat & DW_IC_INTR_START_DET)
561
-		dw_readl(dev, DW_IC_CLR_START_DET);
614
+		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
562615 	if (stat & DW_IC_INTR_GEN_CALL)
563
-		dw_readl(dev, DW_IC_CLR_GEN_CALL);
616
+		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
564617 
565618 	return stat;
566619 }
....@@ -582,7 +635,7 @@
582635 		 * Anytime TX_ABRT is set, the contents of the tx/rx
583636 		 * buffers are flushed. Make sure to skip them.
584637 		 */
585
-		dw_writel(dev, 0, DW_IC_INTR_MASK);
638
+		regmap_write(dev->map, DW_IC_INTR_MASK, 0);
586639 		goto tx_aborted;
587640 	}
588641 
....@@ -603,9 +656,9 @@
603656 		complete(&dev->cmd_complete);
604657 	else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
605658 		/* Workaround to trigger pending interrupt */
606
-		stat = dw_readl(dev, DW_IC_INTR_MASK);
659
+		regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
607660 		i2c_dw_disable_int(dev);
608
-		dw_writel(dev, stat, DW_IC_INTR_MASK);
661
+		regmap_write(dev->map, DW_IC_INTR_MASK, stat);
609662 	}
610663 
611664 	return 0;
....@@ -616,8 +669,8 @@
616669 	struct dw_i2c_dev *dev = dev_id;
617670 	u32 stat, enabled;
618671 
619
-	enabled = dw_readl(dev, DW_IC_ENABLE);
620
-	stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
672
+	regmap_read(dev->map, DW_IC_ENABLE, &enabled);
673
+	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
621674 	dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
622675 	if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
623676 		return IRQ_NONE;
....@@ -626,6 +679,30 @@
626679 
627680 	return IRQ_HANDLED;
628681 }
682
+
683
+void i2c_dw_configure_master(struct dw_i2c_dev *dev)
684
+{
685
+	struct i2c_timings *t = &dev->timings;
686
+
687
+	dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
688
+
689
+	dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
690
+			  DW_IC_CON_RESTART_EN;
691
+
692
+	dev->mode = DW_IC_MASTER;
693
+
694
+	switch (t->bus_freq_hz) {
695
+	case I2C_MAX_STANDARD_MODE_FREQ:
696
+		dev->master_cfg |= DW_IC_CON_SPEED_STD;
697
+		break;
698
+	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
699
+		dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
700
+		break;
701
+	default:
702
+		dev->master_cfg |= DW_IC_CON_SPEED_FAST;
703
+	}
704
+}
705
+EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
629706 
630707 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
631708 {
....@@ -650,15 +727,11 @@
650727 	struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
651728 	struct i2c_adapter *adap = &dev->adapter;
652729 	struct gpio_desc *gpio;
653
-	int r;
654730 
655
-	gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
656
-	if (IS_ERR(gpio)) {
657
-		r = PTR_ERR(gpio);
658
-		if (r == -ENOENT || r == -ENOSYS)
659
-			return 0;
660
-		return r;
661
-	}
731
+	gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
732
+	if (IS_ERR_OR_NULL(gpio))
733
+		return PTR_ERR_OR_ZERO(gpio);
734
+
662735 	rinfo->scl_gpiod = gpio;
663736 
664737 	gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
....@@ -677,7 +750,7 @@
677750 	return 0;
678751 }
679752 
680
-int i2c_dw_probe(struct dw_i2c_dev *dev)
753
+int i2c_dw_probe_master(struct dw_i2c_dev *dev)
681754 {
682755 	struct i2c_adapter *adap = &dev->adapter;
683756 	unsigned long irq_flags;
....@@ -689,11 +762,15 @@
689762 	dev->disable = i2c_dw_disable;
690763 	dev->disable_int = i2c_dw_disable_int;
691764 
692
-	ret = i2c_dw_set_reg_access(dev);
765
+	ret = i2c_dw_init_regmap(dev);
693766 	if (ret)
694767 		return ret;
695768 
696769 	ret = i2c_dw_set_timings_master(dev);
770
+	if (ret)
771
+		return ret;
772
+
773
+	ret = i2c_dw_set_fifo_size(dev);
697774 	if (ret)
698775 		return ret;
699776 
....@@ -709,7 +786,7 @@
709786 	adap->dev.parent = dev->dev;
710787 	i2c_set_adapdata(adap, dev);
711788 
712
-	if (dev->pm_disabled) {
789
+	if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
713790 		irq_flags = IRQF_NO_SUSPEND;
714791 	} else {
715792 		irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
....@@ -742,7 +819,7 @@
742819 
743820 	return ret;
744821 }
745
-EXPORT_SYMBOL_GPL(i2c_dw_probe);
822
+EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
746823 
747824 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
748825 MODULE_LICENSE("GPL");