.. | .. |
---|
50 | 50 | gv100_disp_dmac_fini(struct nv50_disp_chan *chan) |
---|
51 | 51 | { |
---|
52 | 52 | struct nvkm_device *device = chan->disp->base.engine.subdev.device; |
---|
| 53 | + const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; |
---|
53 | 54 | const u32 coff = chan->chid.ctrl * 0x04; |
---|
54 | 55 | nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); |
---|
55 | 56 | gv100_disp_dmac_idle(chan); |
---|
56 | 57 | nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); |
---|
| 58 | + chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); |
---|
57 | 59 | } |
---|
58 | 60 | |
---|
59 | 61 | int |
---|
.. | .. |
---|
71 | 73 | nvkm_wr32(device, 0x610b2c + poff, 0x00000040); |
---|
72 | 74 | |
---|
73 | 75 | nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); |
---|
74 | | - nvkm_wr32(device, 0x690000 + uoff, 0x00000000); |
---|
| 76 | + nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); |
---|
75 | 77 | nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); |
---|
76 | 78 | return gv100_disp_dmac_idle(chan); |
---|
77 | 79 | } |
---|