add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/gpu/drm/nouveau/nv50_fence.c
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@@ -37,7 +37,7 @@
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 {
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 	struct nv10_fence_priv *priv = chan->drm->fence;
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 	struct nv10_fence_chan *fctx;
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-	struct ttm_mem_reg *reg = &priv->bo->bo.mem;
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+	struct ttm_resource *reg = &priv->bo->bo.mem;
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 	u32 start = reg->start * PAGE_SIZE;
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 	u32 limit = start + reg->size - 1;
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 	int ret;
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@@ -51,7 +51,8 @@
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 	fctx->base.read = nv10_fence_read;
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 	fctx->base.sync = nv17_fence_sync;
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-	ret = nvif_object_init(&chan->user, NvSema, NV_DMA_IN_MEMORY,
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+	ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
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+			       NV_DMA_IN_MEMORY,
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 			       &(struct nv_dma_v0) {
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 					.target = NV_DMA_V0_TARGET_VRAM,
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 					.access = NV_DMA_V0_ACCESS_RDWR,
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@@ -80,10 +81,11 @@
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 	priv->base.context_del = nv10_fence_context_del;
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 	spin_lock_init(&priv->lock);
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-	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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+	ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
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+			     NOUVEAU_GEM_DOMAIN_VRAM,
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 			     0, 0x0000, NULL, NULL, &priv->bo);
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 	if (!ret) {
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-		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
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+		ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
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 		if (!ret) {
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 			ret = nouveau_bo_map(priv->bo);
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 			if (ret)