hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2
kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
....@@ -1,13 +1,5 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
- * GNU General Public License for more details.
113 */
124
135 #ifndef _DPU_HW_UTIL_H
....@@ -18,7 +10,6 @@
1810 #include "dpu_hw_mdss.h"
1911
2012 #define REG_MASK(n) ((BIT(n)) - 1)
21
-struct dpu_format_extended;
2213
2314 /*
2415 * This is the common struct maintained by each sub block
....@@ -146,16 +137,6 @@
146137 * Detail enhancer settings
147138 */
148139 struct dpu_hw_scaler3_de_cfg de;
149
-};
150
-
151
-struct dpu_hw_scaler3_lut_cfg {
152
- bool is_configured;
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- u32 *dir_lut;
154
- size_t dir_len;
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- u32 *cir_lut;
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- size_t cir_len;
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- u32 *sep_lut;
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- size_t sep_len;
159140 };
160141
161142 /**
....@@ -324,12 +305,6 @@
324305
325306 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
326307 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
327
-
328
-#define MISR_FRAME_COUNT_MASK 0xFF
329
-#define MISR_CTRL_ENABLE BIT(8)
330
-#define MISR_CTRL_STATUS BIT(9)
331
-#define MISR_CTRL_STATUS_CLEAR BIT(10)
332
-#define INTF_MISR_CTRL_FREE_RUN_MASK BIT(31)
333308
334309 void *dpu_hw_util_get_dir(void);
335310