add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/gpu/drm/msm/adreno/a5xx_power.c
..
..
@@ -1,14 +1,5 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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3
  */
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4
 
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 #include <linux/pm_opp.h>
..
..
@@ -31,6 +22,18 @@
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22
 
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 #define AGC_POWER_CONFIG_PRODUCTION_ID 1
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 #define AGC_INIT_MSG_VALUE 0xBABEFACE
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+
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+/* AGC_LM_CONFIG (A540+) */
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+#define AGC_LM_CONFIG (136/4)
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+#define AGC_LM_CONFIG_GPU_VERSION_SHIFT 17
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+#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE 1
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+#define AGC_LM_CONFIG_THROTTLE_DISABLE (2 << 8)
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+#define AGC_LM_CONFIG_ISENSE_ENABLE (1 << 4)
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+#define AGC_LM_CONFIG_ENABLE_ERROR (3 << 4)
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+#define AGC_LM_CONFIG_LLM_ENABLED (1 << 16)
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+#define AGC_LM_CONFIG_BCL_DISABLED (1 << 24)
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+
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+#define AGC_LEVEL_CONFIG (140/4)
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37
 
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 static struct {
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 	uint32_t reg;
..
..
@@ -116,7 +119,7 @@
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 }
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 /* Setup thermal limit management */
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-static void a5xx_lm_setup(struct msm_gpu *gpu)
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+static void a530_lm_setup(struct msm_gpu *gpu)
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 {
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 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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 	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
..
..
@@ -165,6 +168,45 @@
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 	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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 }
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170
 
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+#define PAYLOAD_SIZE(_size) ((_size) * sizeof(u32))
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+#define LM_DCVS_LIMIT 1
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+#define LEVEL_CONFIG ~(0x303)
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+
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+static void a540_lm_setup(struct msm_gpu *gpu)
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+{
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+	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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+	u32 config;
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+
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+	/* The battery current limiter isn't enabled for A540 */
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+	config = AGC_LM_CONFIG_BCL_DISABLED;
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+	config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
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+
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+	/* For now disable GPMU side throttling */
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+	config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
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+
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+	/* Until we get clock scaling 0 is always the active power level */
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+	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
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+
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+	/* Fixed at 6000 for now */
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+	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
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+
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+	gpu_write(gpu, AGC_MSG_STATE, 0x80000001);
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+	gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
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+
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
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+
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
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+
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config);
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+	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG);
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+	gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE,
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+	PAYLOAD_SIZE(AGC_LEVEL_CONFIG + 1));
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+
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+	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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+}
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+
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 /* Enable SP/TP cpower collapse */
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 static void a5xx_pc_init(struct msm_gpu *gpu)
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 {
..
..
@@ -198,7 +240,7 @@
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 	OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
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 	OUT_RING(ring, 1);
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242
 
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-	gpu->funcs->flush(gpu, ring);
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+	a5xx_flush(gpu, ring, true);
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 	if (!a5xx_idle(gpu, ring)) {
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 		DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
..
..
@@ -206,7 +248,8 @@
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 		return -EINVAL;
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 	}
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-	gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
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+	if (adreno_is_a530(adreno_gpu))
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+		gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
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 	/* Kick off the GPMU */
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 	gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
..
..
@@ -220,12 +263,26 @@
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 		DRM_ERROR("%s: GPMU firmware initialization timed out\n",
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 			gpu->name);
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+	if (!adreno_is_a530(adreno_gpu)) {
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+		u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1);
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+
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+		if (val)
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+			DRM_ERROR("%s: GPMU firmware initialization failed: %d\n",
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+				  gpu->name, val);
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+	}
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+
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 	return 0;
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 }
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 /* Enable limits management */
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 static void a5xx_lm_enable(struct msm_gpu *gpu)
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 {
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+	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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+
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+	/* This init sequence only applies to A530 */
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+	if (!adreno_is_a530(adreno_gpu))
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+		return;
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+
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 	gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
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 	gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
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 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
..
..
@@ -237,10 +294,18 @@
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294
 
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 int a5xx_power_init(struct msm_gpu *gpu)
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 {
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+	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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 	int ret;
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+	/* Not all A5xx chips have a GPMU */
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+	if (adreno_is_a510(adreno_gpu))
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+		return 0;
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+
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 	/* Set up the limits management */
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-	a5xx_lm_setup(gpu);
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+	if (adreno_is_a530(adreno_gpu))
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+		a530_lm_setup(gpu);
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+	else if (adreno_is_a540(adreno_gpu))
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+		a540_lm_setup(gpu);
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 	/* Set up SP/TP power collpase */
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 	a5xx_pc_init(gpu);
..
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@@ -264,6 +329,9 @@
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 	uint32_t dwords = 0, offset = 0, bosize;
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 	unsigned int *data, *ptr, *cmds;
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331
 	unsigned int cmds_size;
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+
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+	if (adreno_is_a510(adreno_gpu))
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+		return;
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 	if (a5xx_gpu->gpmu_bo)
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 		return;
..
..
@@ -298,7 +366,9 @@
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 		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace,
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 		&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
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 	if (IS_ERR(ptr))
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-		goto err;
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+		return;
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+
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+	msm_gem_object_set_name(a5xx_gpu->gpmu_bo, "gpmufw");
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 	while (cmds_size > 0) {
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 		int i;
..
..
@@ -317,15 +387,4 @@
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387
 
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 	msm_gem_put_vaddr(a5xx_gpu->gpmu_bo);
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 	a5xx_gpu->gpmu_dwords = dwords;
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-
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-	return;
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-err:
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-	if (a5xx_gpu->gpmu_iova)
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-		msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
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-	if (a5xx_gpu->gpmu_bo)
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-		drm_gem_object_unreference(a5xx_gpu->gpmu_bo);
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-
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-	a5xx_gpu->gpmu_bo = NULL;
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-	a5xx_gpu->gpmu_iova = 0;
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-	a5xx_gpu->gpmu_dwords = 0;
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 }