hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2
kernel/drivers/gpu/drm/gma500/mdfld_intel_display.c
....@@ -1,32 +1,23 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright © 2006-2007 Intel Corporation
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License along with
14
- * this program; if not, write to the Free Software Foundation, Inc.,
15
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
164 *
175 * Authors:
186 * Eric Anholt <eric@anholt.net>
197 */
208
9
+#include <linux/delay.h>
2110 #include <linux/i2c.h>
2211 #include <linux/pm_runtime.h>
2312
24
-#include <drm/drmP.h>
25
-#include "psb_intel_reg.h"
26
-#include "gma_display.h"
13
+#include <drm/drm_crtc.h>
14
+#include <drm/drm_fourcc.h>
15
+
2716 #include "framebuffer.h"
28
-#include "mdfld_output.h"
17
+#include "gma_display.h"
2918 #include "mdfld_dsi_output.h"
19
+#include "mdfld_output.h"
20
+#include "psb_intel_reg.h"
3021
3122 /* Hardcoded currently */
3223 static int ksel = KSEL_CRYSTAL_19;
....@@ -122,27 +113,6 @@
122113 return (pfit_control >> 29) & 0x3;
123114 }
124115
125
-static struct drm_device globle_dev;
126
-
127
-void mdfld__intel_plane_set_alpha(int enable)
128
-{
129
- struct drm_device *dev = &globle_dev;
130
- int dspcntr_reg = DSPACNTR;
131
- u32 dspcntr;
132
-
133
- dspcntr = REG_READ(dspcntr_reg);
134
-
135
- if (enable) {
136
- dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA;
137
- dspcntr |= DISPPLANE_32BPP;
138
- } else {
139
- dspcntr &= ~DISPPLANE_32BPP;
140
- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
141
- }
142
-
143
- REG_WRITE(dspcntr_reg, dspcntr);
144
-}
145
-
146116 static int check_fb(struct drm_framebuffer *fb)
147117 {
148118 if (!fb)
....@@ -172,8 +142,6 @@
172142 unsigned long start, offset;
173143 u32 dspcntr;
174144 int ret;
175
-
176
- memcpy(&globle_dev, dev, sizeof(struct drm_device));
177145
178146 dev_dbg(dev->dev, "pipe = 0x%x.\n", pipe);
179147
....@@ -690,16 +658,6 @@
690658
691659 dev_dbg(dev->dev, "pipe = 0x%x\n", pipe);
692660
693
-#if 0
694
- if (pipe == 1) {
695
- if (!gma_power_begin(dev, true))
696
- return 0;
697
- android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,
698
- x, y, old_fb);
699
- goto mrst_crtc_mode_set_exit;
700
- }
701
-#endif
702
-
703661 ret = check_fb(crtc->primary->fb);
704662 if (ret)
705663 return ret;
....@@ -950,14 +908,6 @@
950908 }
951909 dpll = 0;
952910
953
-#if 0 /* FIXME revisit later */
954
- if (ksel == KSEL_CRYSTAL_19 || ksel == KSEL_BYPASS_19 ||
955
- ksel == KSEL_BYPASS_25)
956
- dpll &= ~MDFLD_INPUT_REF_SEL;
957
- else if (ksel == KSEL_BYPASS_83_100)
958
- dpll |= MDFLD_INPUT_REF_SEL;
959
-#endif /* FIXME revisit later */
960
-
961911 if (is_hdmi)
962912 dpll |= MDFLD_VCO_SEL;
963913
....@@ -967,20 +917,7 @@
967917 /* compute bitmask from p1 value */
968918 dpll |= (1 << (clock.p1 - 2)) << 17;
969919
970
-#if 0 /* 1080p30 & 720p */
971
- dpll = 0x00050000;
972
- fp = 0x000001be;
973
-#endif
974
-#if 0 /* 480p */
975
- dpll = 0x02010000;
976
- fp = 0x000000d2;
977
-#endif
978920 } else {
979
-#if 0 /*DBI_TPO_480x864*/
980
- dpll = 0x00020000;
981
- fp = 0x00000156;
982
-#endif /* DBI_TPO_480x864 */ /* get from spec. */
983
-
984921 dpll = 0x00800000;
985922 fp = 0x000000c1;
986923 }