~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* tc358767 eDP bridge driver
3	4	*
..	..	@@ -12,18 +13,9 @@
12	13	*
13	14	* Copyright (C) 2012 Texas Instruments
14	15	* Author: Rob Clark <robdclark@gmail.com>
15		- *
16		- * This program is free software; you can redistribute it and/or modify
17		- * it under the terms of the GNU General Public License as published by
18		- * the Free Software Foundation; either version 2 of the License, or
19		- * (at your option) any later version.
20		- *
21		- * This program is distributed in the hope that it will be useful,
22		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
23		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24		- * GNU General Public License for more details.
25	16	*/
26	17
	18	+#include <linux/bitfield.h>
27	19	#include <linux/clk.h>
28	20	#include <linux/device.h>
29	21	#include <linux/gpio/consumer.h>
..	..	@@ -34,11 +26,13 @@
34	26	#include <linux/slab.h>
35	27
36	28	#include <drm/drm_atomic_helper.h>
37		-#include <drm/drm_crtc_helper.h>
	29	+#include <drm/drm_bridge.h>
38	30	#include <drm/drm_dp_helper.h>
39	31	#include <drm/drm_edid.h>
40	32	#include <drm/drm_of.h>
41	33	#include <drm/drm_panel.h>
	34	+#include <drm/drm_print.h>
	35	+#include <drm/drm_probe_helper.h>
42	36
43	37	/* Registers */
44	38
..	..	@@ -56,6 +50,7 @@
56	50
57	51	/* Video Path */
58	52	#define VPCTRL0 0x0450
	53	+#define VSDELAY GENMASK(31, 20)
59	54	#define OPXLFMT_RGB666 (0 << 8)
60	55	#define OPXLFMT_RGB888 (1 << 8)
61	56	#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
..	..	@@ -63,14 +58,23 @@
63	58	#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
64	59	#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
65	60	#define HTIM01 0x0454
	61	+#define HPW GENMASK(8, 0)
	62	+#define HBPR GENMASK(24, 16)
66	63	#define HTIM02 0x0458
	64	+#define HDISPR GENMASK(10, 0)
	65	+#define HFPR GENMASK(24, 16)
67	66	#define VTIM01 0x045c
	67	+#define VSPR GENMASK(7, 0)
	68	+#define VBPR GENMASK(23, 16)
68	69	#define VTIM02 0x0460
	70	+#define VFPR GENMASK(23, 16)
	71	+#define VDISPR GENMASK(10, 0)
69	72	#define VFUEN0 0x0464
70	73	#define VFUEN BIT(0) /* Video Frame Timing Upload */
71	74
72	75	/* System */
73	76	#define TC_IDREG 0x0500
	77	+#define SYSSTAT 0x0508
74	78	#define SYSCTRL 0x0510
75	79	#define DP0_AUDSRC_NO_INPUT (0 << 3)
76	80	#define DP0_AUDSRC_I2S_RX (1 << 3)
..	..	@@ -78,6 +82,26 @@
78	82	#define DP0_VIDSRC_DSI_RX (1 << 0)
79	83	#define DP0_VIDSRC_DPI_RX (2 << 0)
80	84	#define DP0_VIDSRC_COLOR_BAR (3 << 0)
	85	+#define SYSRSTENB 0x050c
	86	+#define ENBI2C (1 << 0)
	87	+#define ENBLCD0 (1 << 2)
	88	+#define ENBBM (1 << 3)
	89	+#define ENBDSIRX (1 << 4)
	90	+#define ENBREG (1 << 5)
	91	+#define ENBHDCP (1 << 8)
	92	+#define GPIOM 0x0540
	93	+#define GPIOC 0x0544
	94	+#define GPIOO 0x0548
	95	+#define GPIOI 0x054c
	96	+#define INTCTL_G 0x0560
	97	+#define INTSTS_G 0x0564
	98	+
	99	+#define INT_SYSERR BIT(16)
	100	+#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
	101	+#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
	102	+
	103	+#define INT_GP0_LCNT 0x0584
	104	+#define INT_GP1_LCNT 0x0588
81	105
82	106	/* Control */
83	107	#define DP0CTL 0x0600
..	..	@@ -94,19 +118,35 @@
94	118	/* Main Channel */
95	119	#define DP0_SECSAMPLE 0x0640
96	120	#define DP0_VIDSYNCDELAY 0x0644
	121	+#define VID_SYNC_DLY GENMASK(15, 0)
	122	+#define THRESH_DLY GENMASK(31, 16)
	123	+
97	124	#define DP0_TOTALVAL 0x0648
	125	+#define H_TOTAL GENMASK(15, 0)
	126	+#define V_TOTAL GENMASK(31, 16)
98	127	#define DP0_STARTVAL 0x064c
	128	+#define H_START GENMASK(15, 0)
	129	+#define V_START GENMASK(31, 16)
99	130	#define DP0_ACTIVEVAL 0x0650
	131	+#define H_ACT GENMASK(15, 0)
	132	+#define V_ACT GENMASK(31, 16)
	133	+
100	134	#define DP0_SYNCVAL 0x0654
	135	+#define VS_WIDTH GENMASK(30, 16)
	136	+#define HS_WIDTH GENMASK(14, 0)
101	137	#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
102	138	#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
103	139	#define DP0_MISC 0x0658
104	140	#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
	141	+#define MAX_TU_SYMBOL GENMASK(28, 23)
	142	+#define TU_SIZE GENMASK(21, 16)
105	143	#define BPC_6 (0 << 5)
106	144	#define BPC_8 (1 << 5)
107	145
108	146	/* AUX channel */
109	147	#define DP0_AUXCFG0 0x0660
	148	+#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
	149	+#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
110	150	#define DP0_AUXCFG1 0x0664
111	151	#define AUX_RX_FILTER_EN BIT(16)
112	152
..	..	@@ -114,10 +154,10 @@
114	154	#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
115	155	#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
116	156	#define DP0_AUXSTATUS 0x068c
117		-#define AUX_STATUS_MASK 0xf0
118		-#define AUX_STATUS_SHIFT 4
119		-#define AUX_TIMEOUT BIT(1)
120		-#define AUX_BUSY BIT(0)
	157	+#define AUX_BYTES GENMASK(15, 8)
	158	+#define AUX_STATUS GENMASK(7, 4)
	159	+#define AUX_TIMEOUT BIT(1)
	160	+#define AUX_BUSY BIT(0)
121	161	#define DP0_AUXI2CADR 0x0698
122	162
123	163	/* Link Training */
..	..	@@ -178,19 +218,24 @@
178	218
179	219	/* Test & Debug */
180	220	#define TSTCTL 0x0a00
	221	+#define COLOR_R GENMASK(31, 24)
	222	+#define COLOR_G GENMASK(23, 16)
	223	+#define COLOR_B GENMASK(15, 8)
	224	+#define ENI2CFILTER BIT(4)
	225	+#define COLOR_BAR_MODE GENMASK(1, 0)
	226	+#define COLOR_BAR_MODE_BARS 2
181	227	#define PLL_DBG 0x0a04
182	228
183	229	static bool tc_test_pattern;
184	230	module_param_named(test, tc_test_pattern, bool, 0644);
185	231
186	232	struct tc_edp_link {
187		- struct drm_dp_link base;
	233	+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
	234	+ unsigned int rate;
	235	+ u8 num_lanes;
188	236	u8 assr;
189		- int scrambler_dis;
190		- int spread;
191		- int coding8b10b;
192		- u8 swing;
193		- u8 preemp;
	237	+ bool scrambler_dis;
	238	+ bool spread;
194	239	};
195	240
196	241	struct tc_data {
..	..	@@ -199,16 +244,14 @@
199	244	struct drm_dp_aux aux;
200	245
201	246	struct drm_bridge bridge;
	247	+ struct drm_bridge *panel_bridge;
202	248	struct drm_connector connector;
203		- struct drm_panel *panel;
204	249
205	250	/* link settings */
206	251	struct tc_edp_link link;
207	252
208		- /* display edid */
209		- struct edid *edid;
210	253	/* current mode */
211		- struct drm_display_mode *mode;
	254	+ struct drm_display_mode mode;
212	255
213	256	u32 rev;
214	257	u8 assr;
..	..	@@ -216,6 +259,12 @@
216	259	struct gpio_desc *sd_gpio;
217	260	struct gpio_desc *reset_gpio;
218	261	struct clk *refclk;
	262	+
	263	+ /* do we have IRQ */
	264	+ bool have_irq;
	265	+
	266	+ /* HPD pin number (0 or 1) or -ENODEV */
	267	+ int hpd_pin;
219	268	};
220	269
221	270	static inline struct tc_data aux_to_tc(struct drm_dp_aux a)
..	..	@@ -233,69 +282,62 @@
233	282	return container_of(c, struct tc_data, connector);
234	283	}
235	284
236		-/* Simple macros to avoid repeated error checks */
237		-#define tc_write(reg, var) \
238		- do { \
239		- ret = regmap_write(tc->regmap, reg, var); \
240		- if (ret) \
241		- goto err; \
242		- } while (0)
243		-#define tc_read(reg, var) \
244		- do { \
245		- ret = regmap_read(tc->regmap, reg, var); \
246		- if (ret) \
247		- goto err; \
248		- } while (0)
249		-
250		-static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
	285	+static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
251	286	unsigned int cond_mask,
252	287	unsigned int cond_value,
253	288	unsigned long sleep_us, u64 timeout_us)
254	289	{
255		- ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
256	290	unsigned int val;
257		- int ret;
258	291
259		- for (;;) {
260		- ret = regmap_read(map, addr, &val);
261		- if (ret)
262		- break;
263		- if ((val & cond_mask) == cond_value)
264		- break;
265		- if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
266		- ret = regmap_read(map, addr, &val);
267		- break;
268		- }
269		- if (sleep_us)
270		- usleep_range((sleep_us >> 2) + 1, sleep_us);
271		- }
272		- return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
	292	+ return regmap_read_poll_timeout(tc->regmap, addr, val,
	293	+ (val & cond_mask) == cond_value,
	294	+ sleep_us, timeout_us);
273	295	}
274	296
275		-static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
	297	+static int tc_aux_wait_busy(struct tc_data *tc)
276	298	{
277		- return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
278		- 1000, 1000 * timeout_ms);
	299	+ return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
279	300	}
280	301
281		-static int tc_aux_get_status(struct tc_data tc, u8 reply)
	302	+static int tc_aux_write_data(struct tc_data tc, const void data,
	303	+ size_t size)
282	304	{
283		- int ret;
284		- u32 value;
	305	+ u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
	306	+ int ret, count = ALIGN(size, sizeof(u32));
285	307
286		- ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
287		- if (ret < 0)
	308	+ memcpy(auxwdata, data, size);
	309	+
	310	+ ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
	311	+ if (ret)
288	312	return ret;
289		- if (value & AUX_BUSY) {
290		- if (value & AUX_TIMEOUT) {
291		- dev_err(tc->dev, "i2c access timeout!\n");
292		- return -ETIMEDOUT;
293		- }
294		- return -EBUSY;
295		- }
296	313
297		- *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
298		- return 0;
	314	+ return size;
	315	+}
	316	+
	317	+static int tc_aux_read_data(struct tc_data tc, void data, size_t size)
	318	+{
	319	+ u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
	320	+ int ret, count = ALIGN(size, sizeof(u32));
	321	+
	322	+ ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
	323	+ if (ret)
	324	+ return ret;
	325	+
	326	+ memcpy(data, auxrdata, size);
	327	+
	328	+ return size;
	329	+}
	330	+
	331	+static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
	332	+{
	333	+ u32 auxcfg0 = msg->request;
	334	+
	335	+ if (size)
	336	+ auxcfg0 \|= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
	337	+ else
	338	+ auxcfg0 \|= DP0_AUXCFG0_ADDR_ONLY;
	339	+
	340	+ return auxcfg0;
299	341	}
300	342
301	343	static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
..	..	@@ -304,63 +346,67 @@
304	346	struct tc_data *tc = aux_to_tc(aux);
305	347	size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
306	348	u8 request = msg->request & ~DP_AUX_I2C_MOT;
307		- u8 *buf = msg->buffer;
308		- u32 tmp = 0;
309		- int i = 0;
	349	+ u32 auxstatus;
310	350	int ret;
311	351
312		- if (size == 0)
313		- return 0;
314		-
315		- ret = tc_aux_wait_busy(tc, 100);
	352	+ ret = tc_aux_wait_busy(tc);
316	353	if (ret)
317		- goto err;
	354	+ return ret;
318	355
319		- if (request == DP_AUX_I2C_WRITE \|\| request == DP_AUX_NATIVE_WRITE) {
320		- /* Store data */
321		- while (i < size) {
322		- if (request == DP_AUX_NATIVE_WRITE)
323		- tmp = tmp \| (buf[i] << (8 * (i & 0x3)));
324		- else
325		- tmp = (tmp << 8) \| buf[i];
326		- i++;
327		- if (((i % 4) == 0) \|\| (i == size)) {
328		- tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
329		- tmp = 0;
330		- }
	356	+ switch (request) {
	357	+ case DP_AUX_NATIVE_READ:
	358	+ case DP_AUX_I2C_READ:
	359	+ break;
	360	+ case DP_AUX_NATIVE_WRITE:
	361	+ case DP_AUX_I2C_WRITE:
	362	+ if (size) {
	363	+ ret = tc_aux_write_data(tc, msg->buffer, size);
	364	+ if (ret < 0)
	365	+ return ret;
331	366	}
332		- } else if (request != DP_AUX_I2C_READ &&
333		- request != DP_AUX_NATIVE_READ) {
	367	+ break;
	368	+ default:
334	369	return -EINVAL;
335	370	}
336	371
337	372	/* Store address */
338		- tc_write(DP0_AUXADDR, msg->address);
	373	+ ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
	374	+ if (ret)
	375	+ return ret;
339	376	/* Start transfer */
340		- tc_write(DP0_AUXCFG0, ((size - 1) << 8) \| request);
341		-
342		- ret = tc_aux_wait_busy(tc, 100);
	377	+ ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
343	378	if (ret)
344		- goto err;
	379	+ return ret;
345	380
346		- ret = tc_aux_get_status(tc, &msg->reply);
	381	+ ret = tc_aux_wait_busy(tc);
347	382	if (ret)
348		- goto err;
	383	+ return ret;
349	384
350		- if (request == DP_AUX_I2C_READ \|\| request == DP_AUX_NATIVE_READ) {
351		- /* Read data */
352		- while (i < size) {
353		- if ((i % 4) == 0)
354		- tc_read(DP0_AUXRDATA(i >> 2), &tmp);
355		- buf[i] = tmp & 0xff;
356		- tmp = tmp >> 8;
357		- i++;
358		- }
	385	+ ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
	386	+ if (ret)
	387	+ return ret;
	388	+
	389	+ if (auxstatus & AUX_TIMEOUT)
	390	+ return -ETIMEDOUT;
	391	+ /*
	392	+ * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
	393	+ * reports 1 byte transferred in its status. To deal we that
	394	+ * we ignore aux_bytes field if we know that this was an
	395	+ * address-only transfer
	396	+ */
	397	+ if (size)
	398	+ size = FIELD_GET(AUX_BYTES, auxstatus);
	399	+ msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
	400	+
	401	+ switch (request) {
	402	+ case DP_AUX_NATIVE_READ:
	403	+ case DP_AUX_I2C_READ:
	404	+ if (size)
	405	+ return tc_aux_read_data(tc, msg->buffer, size);
	406	+ break;
359	407	}
360	408
361	409	return size;
362		-err:
363		- return ret;
364	410	}
365	411
366	412	static const char * const training_pattern1_errors[] = {
..	..	@@ -387,26 +433,31 @@
387	433	* No training pattern, skew lane 1 data by two LSCLK cycles with
388	434	* respect to lane 0 data, AutoCorrect Mode = 0
389	435	*/
390		- u32 reg = DP0_SRCCTRL_NOTP \| DP0_SRCCTRL_LANESKEW;
	436	+ u32 reg = DP0_SRCCTRL_NOTP \| DP0_SRCCTRL_LANESKEW \| DP0_SRCCTRL_EN810B;
391	437
392	438	if (tc->link.scrambler_dis)
393	439	reg \|= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
394		- if (tc->link.coding8b10b)
395		- /* Enable 8/10B Encoder (TxData[19:16] not used) */
396		- reg \|= DP0_SRCCTRL_EN810B;
397	440	if (tc->link.spread)
398	441	reg \|= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
399		- if (tc->link.base.num_lanes == 2)
	442	+ if (tc->link.num_lanes == 2)
400	443	reg \|= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
401		- if (tc->link.base.rate != 162000)
	444	+ if (tc->link.rate != 162000)
402	445	reg \|= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
403	446	return reg;
404	447	}
405	448
406		-static void tc_wait_pll_lock(struct tc_data *tc)
	449	+static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
407	450	{
	451	+ int ret;
	452	+
	453	+ ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE \| PLLEN);
	454	+ if (ret)
	455	+ return ret;
	456	+
408	457	/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
409	458	usleep_range(3000, 6000);
	459	+
	460	+ return 0;
410	461	}
411	462
412	463	static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
..	..	@@ -420,6 +471,7 @@
420	471	int ext_div[] = {1, 2, 3, 5, 7};
421	472	int best_pixelclock = 0;
422	473	int vco_hi = 0;
	474	+ u32 pxl_pllparam;
423	475
424	476	dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
425	477	refclk);
..	..	@@ -489,24 +541,23 @@
489	541	best_mul = 0;
490	542
491	543	/* Power up PLL and switch to bypass */
492		- tc_write(PXL_PLLCTRL, PLLBYP \| PLLEN);
	544	+ ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP \| PLLEN);
	545	+ if (ret)
	546	+ return ret;
493	547
494		- tc_write(PXL_PLLPARAM,
495		- (vco_hi << 24) \| /* For PLL VCO >= 300 MHz = 1 */
496		- (ext_div[best_pre] << 20) \| /* External Pre-divider */
497		- (ext_div[best_post] << 16) \| /* External Post-divider */
498		- IN_SEL_REFCLK \| /* Use RefClk as PLL input */
499		- (best_div << 8) \| /* Divider for PLL RefClk */
500		- (best_mul << 0)); /* Multiplier for PLL */
	548	+ pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
	549	+ pxl_pllparam \|= ext_div[best_pre] << 20; /* External Pre-divider */
	550	+ pxl_pllparam \|= ext_div[best_post] << 16; /* External Post-divider */
	551	+ pxl_pllparam \|= IN_SEL_REFCLK; /* Use RefClk as PLL input */
	552	+ pxl_pllparam \|= best_div << 8; /* Divider for PLL RefClk */
	553	+ pxl_pllparam \|= best_mul; /* Multiplier for PLL */
	554	+
	555	+ ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
	556	+ if (ret)
	557	+ return ret;
501	558
502	559	/* Force PLL parameter update and disable bypass */
503		- tc_write(PXL_PLLCTRL, PLLUPDATE \| PLLEN);
504		-
505		- tc_wait_pll_lock(tc);
506		-
507		- return 0;
508		-err:
509		- return ret;
	560	+ return tc_pllupdate(tc, PXL_PLLCTRL);
510	561	}
511	562
512	563	static int tc_pxl_pll_dis(struct tc_data *tc)
..	..	@@ -517,7 +568,6 @@
517	568
518	569	static int tc_stream_clock_calc(struct tc_data *tc)
519	570	{
520		- int ret;
521	571	/*
522	572	* If the Stream clock and Link Symbol clock are
523	573	* asynchronous with each other, the value of M changes over
..	..	@@ -533,70 +583,78 @@
533	583	* M/N = f_STRMCLK / f_LSCLK
534	584	*
535	585	*/
536		- tc_write(DP0_VIDMNGEN1, 32768);
537		-
538		- return 0;
539		-err:
540		- return ret;
	586	+ return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
541	587	}
542	588
543		-static int tc_aux_link_setup(struct tc_data *tc)
	589	+static int tc_set_syspllparam(struct tc_data *tc)
544	590	{
545	591	unsigned long rate;
546		- u32 value;
547		- int ret;
548		- u32 dp_phy_ctrl;
	592	+ u32 pllparam = SYSCLK_SEL_LSCLK \| LSCLK_DIV_2;
549	593
550	594	rate = clk_get_rate(tc->refclk);
551	595	switch (rate) {
552	596	case 38400000:
553		- value = REF_FREQ_38M4;
	597	+ pllparam \|= REF_FREQ_38M4;
554	598	break;
555	599	case 26000000:
556		- value = REF_FREQ_26M;
	600	+ pllparam \|= REF_FREQ_26M;
557	601	break;
558	602	case 19200000:
559		- value = REF_FREQ_19M2;
	603	+ pllparam \|= REF_FREQ_19M2;
560	604	break;
561	605	case 13000000:
562		- value = REF_FREQ_13M;
	606	+ pllparam \|= REF_FREQ_13M;
563	607	break;
564	608	default:
565	609	dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
566	610	return -EINVAL;
567	611	}
568	612
	613	+ return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
	614	+}
	615	+
	616	+static int tc_aux_link_setup(struct tc_data *tc)
	617	+{
	618	+ int ret;
	619	+ u32 dp0_auxcfg1;
	620	+
569	621	/* Setup DP-PHY / PLL */
570		- value \|= SYSCLK_SEL_LSCLK \| LSCLK_DIV_2;
571		- tc_write(SYS_PLLPARAM, value);
	622	+ ret = tc_set_syspllparam(tc);
	623	+ if (ret)
	624	+ goto err;
572	625
573		- dp_phy_ctrl = BGREN \| PWR_SW_EN \| PHY_A0_EN;
574		- if (tc->link.base.num_lanes == 2)
575		- dp_phy_ctrl \|= PHY_2LANE;
576		- tc_write(DP_PHY_CTRL, dp_phy_ctrl);
577		-
	626	+ ret = regmap_write(tc->regmap, DP_PHY_CTRL,
	627	+ BGREN \| PWR_SW_EN \| PHY_A0_EN);
	628	+ if (ret)
	629	+ goto err;
578	630	/*
579	631	* Initially PLLs are in bypass. Force PLL parameter update,
580	632	* disable PLL bypass, enable PLL
581	633	*/
582		- tc_write(DP0_PLLCTRL, PLLUPDATE \| PLLEN);
583		- tc_wait_pll_lock(tc);
	634	+ ret = tc_pllupdate(tc, DP0_PLLCTRL);
	635	+ if (ret)
	636	+ goto err;
584	637
585		- tc_write(DP1_PLLCTRL, PLLUPDATE \| PLLEN);
586		- tc_wait_pll_lock(tc);
	638	+ ret = tc_pllupdate(tc, DP1_PLLCTRL);
	639	+ if (ret)
	640	+ goto err;
587	641
588		- ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
589		- 1000);
	642	+ ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
590	643	if (ret == -ETIMEDOUT) {
591	644	dev_err(tc->dev, "Timeout waiting for PHY to become ready");
592	645	return ret;
593		- } else if (ret)
	646	+ } else if (ret) {
594	647	goto err;
	648	+ }
595	649
596	650	/* Setup AUX link */
597		- tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN \|
598		- (0x06 << 8) \| /* Aux Bit Period Calculator Threshold */
599		- (0x3f << 0)); /* Aux Response Timeout Timer */
	651	+ dp0_auxcfg1 = AUX_RX_FILTER_EN;
	652	+ dp0_auxcfg1 \|= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
	653	+ dp0_auxcfg1 \|= 0x3f << 0; /* Aux Response Timeout Timer */
	654	+
	655	+ ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
	656	+ if (ret)
	657	+ goto err;
600	658
601	659	return 0;
602	660	err:
..	..	@@ -606,47 +664,60 @@
606	664
607	665	static int tc_get_display_props(struct tc_data *tc)
608	666	{
	667	+ u8 revision, num_lanes;
	668	+ unsigned int rate;
609	669	int ret;
610		- /* temp buffer */
611		- u8 tmp[8];
	670	+ u8 reg;
612	671
613	672	/* Read DP Rx Link Capability */
614		- ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
	673	+ ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
	674	+ DP_RECEIVER_CAP_SIZE);
615	675	if (ret < 0)
616	676	goto err_dpcd_read;
617		- if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
	677	+
	678	+ revision = tc->link.dpcd[DP_DPCD_REV];
	679	+ rate = drm_dp_max_link_rate(tc->link.dpcd);
	680	+ num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
	681	+
	682	+ if (rate != 162000 && rate != 270000) {
618	683	dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
619		- tc->link.base.rate = 270000;
	684	+ rate = 270000;
620	685	}
621	686
622		- if (tc->link.base.num_lanes > 2) {
	687	+ tc->link.rate = rate;
	688	+
	689	+ if (num_lanes > 2) {
623	690	dev_dbg(tc->dev, "Falling to 2 lanes\n");
624		- tc->link.base.num_lanes = 2;
	691	+ num_lanes = 2;
625	692	}
626	693
627		- ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
628		- if (ret < 0)
629		- goto err_dpcd_read;
630		- tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
	694	+ tc->link.num_lanes = num_lanes;
631	695
632		- ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
	696	+ ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
633	697	if (ret < 0)
634	698	goto err_dpcd_read;
635		- tc->link.coding8b10b = tmp[0] & BIT(0);
636		- tc->link.scrambler_dis = 0;
	699	+ tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
	700	+
	701	+ ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
	702	+ if (ret < 0)
	703	+ goto err_dpcd_read;
	704	+
	705	+ tc->link.scrambler_dis = false;
637	706	/* read assr */
638		- ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
	707	+ ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
639	708	if (ret < 0)
640	709	goto err_dpcd_read;
641		- tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
	710	+ tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
642	711
643	712	dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
644		- tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
645		- (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
646		- tc->link.base.num_lanes,
647		- (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
648		- "enhanced" : "non-enhanced");
649		- dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
	713	+ revision >> 4, revision & 0x0f,
	714	+ (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
	715	+ tc->link.num_lanes,
	716	+ drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
	717	+ "enhanced" : "default");
	718	+ dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
	719	+ tc->link.spread ? "0.5%" : "0.0%",
	720	+ tc->link.scrambler_dis ? "disabled" : "enabled");
650	721	dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
651	722	tc->link.assr, tc->assr);
652	723
..	..	@@ -657,7 +728,8 @@
657	728	return ret;
658	729	}
659	730
660		-static int tc_set_video_mode(struct tc_data tc, struct drm_display_mode mode)
	731	+static int tc_set_video_mode(struct tc_data *tc,
	732	+ const struct drm_display_mode *mode)
661	733	{
662	734	int ret;
663	735	int vid_sync_dly;
..	..	@@ -669,6 +741,9 @@
669	741	int upper_margin = mode->vtotal - mode->vsync_end;
670	742	int lower_margin = mode->vsync_start - mode->vdisplay;
671	743	int vsync_len = mode->vsync_end - mode->vsync_start;
	744	+ u32 dp0_syncval;
	745	+ u32 bits_per_pixel = 24;
	746	+ u32 in_bw, out_bw;
672	747
673	748	/*
674	749	* Recommended maximum number of symbols transferred in a transfer unit:
..	..	@@ -676,7 +751,10 @@
676	751	* (output active video bandwidth in bytes))
677	752	* Must be less than tu_size.
678	753	*/
679		- max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
	754	+
	755	+ in_bw = mode->clock * bits_per_pixel / 8;
	756	+ out_bw = tc->link.num_lanes * tc->link.rate;
	757	+ max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
680	758
681	759	dev_dbg(tc->dev, "set mode %dx%d\n",
682	760	mode->hdisplay, mode->vdisplay);
..	..	@@ -693,223 +771,193 @@
693	771	* assume we do not need any delay when DPI is a source of
694	772	* sync signals
695	773	*/
696		- tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ \|
697		- OPXLFMT_RGB888 \| FRMSYNC_DISABLED \| MSF_DISABLED);
698		- tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) \| /* H back porch */
699		- (ALIGN(hsync_len, 2) << 0)); /* Hsync */
700		- tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) \| /* H front porch */
701		- (ALIGN(mode->hdisplay, 2) << 0)); /* width */
702		- tc_write(VTIM01, (upper_margin << 16) \| /* V back porch */
703		- (vsync_len << 0)); /* Vsync */
704		- tc_write(VTIM02, (lower_margin << 16) \| /* V front porch */
705		- (mode->vdisplay << 0)); /* height */
706		- tc_write(VFUEN0, VFUEN); /* update settings */
	774	+ ret = regmap_write(tc->regmap, VPCTRL0,
	775	+ FIELD_PREP(VSDELAY, 0) \|
	776	+ OPXLFMT_RGB888 \| FRMSYNC_DISABLED \| MSF_DISABLED);
	777	+ if (ret)
	778	+ return ret;
	779	+
	780	+ ret = regmap_write(tc->regmap, HTIM01,
	781	+ FIELD_PREP(HBPR, ALIGN(left_margin, 2)) \|
	782	+ FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
	783	+ if (ret)
	784	+ return ret;
	785	+
	786	+ ret = regmap_write(tc->regmap, HTIM02,
	787	+ FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) \|
	788	+ FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
	789	+ if (ret)
	790	+ return ret;
	791	+
	792	+ ret = regmap_write(tc->regmap, VTIM01,
	793	+ FIELD_PREP(VBPR, upper_margin) \|
	794	+ FIELD_PREP(VSPR, vsync_len));
	795	+ if (ret)
	796	+ return ret;
	797	+
	798	+ ret = regmap_write(tc->regmap, VTIM02,
	799	+ FIELD_PREP(VFPR, lower_margin) \|
	800	+ FIELD_PREP(VDISPR, mode->vdisplay));
	801	+ if (ret)
	802	+ return ret;
	803	+
	804	+ ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
	805	+ if (ret)
	806	+ return ret;
707	807
708	808	/* Test pattern settings */
709		- tc_write(TSTCTL,
710		- (120 << 24) \| /* Red Color component value */
711		- (20 << 16) \| /* Green Color component value */
712		- (99 << 8) \| /* Blue Color component value */
713		- (1 << 4) \| /* Enable I2C Filter */
714		- (2 << 0) \| /* Color bar Mode */
715		- 0);
	809	+ ret = regmap_write(tc->regmap, TSTCTL,
	810	+ FIELD_PREP(COLOR_R, 120) \|
	811	+ FIELD_PREP(COLOR_G, 20) \|
	812	+ FIELD_PREP(COLOR_B, 99) \|
	813	+ ENI2CFILTER \|
	814	+ FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
	815	+ if (ret)
	816	+ return ret;
716	817
717	818	/* DP Main Stream Attributes */
718	819	vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
719		- tc_write(DP0_VIDSYNCDELAY,
720		- (max_tu_symbol << 16) \| /* thresh_dly */
721		- (vid_sync_dly << 0));
	820	+ ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
	821	+ FIELD_PREP(THRESH_DLY, max_tu_symbol) \|
	822	+ FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
722	823
723		- tc_write(DP0_TOTALVAL, (mode->vtotal << 16) \| (mode->htotal));
	824	+ ret = regmap_write(tc->regmap, DP0_TOTALVAL,
	825	+ FIELD_PREP(H_TOTAL, mode->htotal) \|
	826	+ FIELD_PREP(V_TOTAL, mode->vtotal));
	827	+ if (ret)
	828	+ return ret;
724	829
725		- tc_write(DP0_STARTVAL,
726		- ((upper_margin + vsync_len) << 16) \|
727		- ((left_margin + hsync_len) << 0));
	830	+ ret = regmap_write(tc->regmap, DP0_STARTVAL,
	831	+ FIELD_PREP(H_START, left_margin + hsync_len) \|
	832	+ FIELD_PREP(V_START, upper_margin + vsync_len));
	833	+ if (ret)
	834	+ return ret;
728	835
729		- tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) \| (mode->hdisplay));
	836	+ ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
	837	+ FIELD_PREP(V_ACT, mode->vdisplay) \|
	838	+ FIELD_PREP(H_ACT, mode->hdisplay));
	839	+ if (ret)
	840	+ return ret;
730	841
731		- tc_write(DP0_SYNCVAL, (vsync_len << 16) \| (hsync_len << 0) \|
732		- ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) \|
733		- ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
	842	+ dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) \|
	843	+ FIELD_PREP(HS_WIDTH, hsync_len);
734	844
735		- tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW \| HS_POL_ACTIVE_LOW \|
736		- DE_POL_ACTIVE_HIGH \| SUB_CFG_TYPE_CONFIG1 \| DPI_BPP_RGB888);
	845	+ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
	846	+ dp0_syncval \|= SYNCVAL_VS_POL_ACTIVE_LOW;
737	847
738		- tc_write(DP0_MISC, (max_tu_symbol << 23) \| (TU_SIZE_RECOMMENDED << 16) \|
	848	+ if (mode->flags & DRM_MODE_FLAG_NHSYNC)
	849	+ dp0_syncval \|= SYNCVAL_HS_POL_ACTIVE_LOW;
	850	+
	851	+ ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
	852	+ if (ret)
	853	+ return ret;
	854	+
	855	+ ret = regmap_write(tc->regmap, DPIPXLFMT,
	856	+ VS_POL_ACTIVE_LOW \| HS_POL_ACTIVE_LOW \|
	857	+ DE_POL_ACTIVE_HIGH \| SUB_CFG_TYPE_CONFIG1 \|
	858	+ DPI_BPP_RGB888);
	859	+ if (ret)
	860	+ return ret;
	861	+
	862	+ ret = regmap_write(tc->regmap, DP0_MISC,
	863	+ FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) \|
	864	+ FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) \|
739	865	BPC_8);
	866	+ if (ret)
	867	+ return ret;
740	868
741	869	return 0;
742		-err:
743		- return ret;
744	870	}
745	871
746		-static int tc_link_training(struct tc_data *tc, int pattern)
	872	+static int tc_wait_link_training(struct tc_data *tc)
747	873	{
748		- const char * const *errors;
749		- u32 srcctrl = tc_srcctrl(tc) \| DP0_SRCCTRL_SCRMBLDIS \|
750		- DP0_SRCCTRL_AUTOCORRECT;
751		- int timeout;
752		- int retry;
753	874	u32 value;
754	875	int ret;
755	876
756		- if (pattern == DP_TRAINING_PATTERN_1) {
757		- srcctrl \|= DP0_SRCCTRL_TP1;
758		- errors = training_pattern1_errors;
759		- } else {
760		- srcctrl \|= DP0_SRCCTRL_TP2;
761		- errors = training_pattern2_errors;
	877	+ ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
	878	+ LT_LOOPDONE, 500, 100000);
	879	+ if (ret) {
	880	+ dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
	881	+ return ret;
762	882	}
763	883
764		- /* Set DPCD 0x102 for Training Part 1 or 2 */
765		- tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE \| pattern);
	884	+ ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
	885	+ if (ret)
	886	+ return ret;
766	887
767		- tc_write(DP0_LTLOOPCTRL,
768		- (0x0f << 28) \| /* Defer Iteration Count */
769		- (0x0f << 24) \| /* Loop Iteration Count */
770		- (0x0d << 0)); /* Loop Timer Delay */
771		-
772		- retry = 5;
773		- do {
774		- /* Set DP0 Training Pattern */
775		- tc_write(DP0_SRCCTRL, srcctrl);
776		-
777		- /* Enable DP0 to start Link Training */
778		- tc_write(DP0CTL, DP_EN);
779		-
780		- /* wait */
781		- timeout = 1000;
782		- do {
783		- tc_read(DP0_LTSTAT, &value);
784		- udelay(1);
785		- } while ((!(value & LT_LOOPDONE)) && (--timeout));
786		- if (timeout == 0) {
787		- dev_err(tc->dev, "Link training timeout!\n");
788		- } else {
789		- int pattern = (value >> 11) & 0x3;
790		- int error = (value >> 8) & 0x7;
791		-
792		- dev_dbg(tc->dev,
793		- "Link training phase %d done after %d uS: %s\n",
794		- pattern, 1000 - timeout, errors[error]);
795		- if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
796		- break;
797		- if (pattern == DP_TRAINING_PATTERN_2) {
798		- value &= LT_CHANNEL1_EQ_BITS \|
799		- LT_INTERLANE_ALIGN_DONE \|
800		- LT_CHANNEL0_EQ_BITS;
801		- /* in case of two lanes */
802		- if ((tc->link.base.num_lanes == 2) &&
803		- (value == (LT_CHANNEL1_EQ_BITS \|
804		- LT_INTERLANE_ALIGN_DONE \|
805		- LT_CHANNEL0_EQ_BITS)))
806		- break;
807		- /* in case of one line */
808		- if ((tc->link.base.num_lanes == 1) &&
809		- (value == (LT_INTERLANE_ALIGN_DONE \|
810		- LT_CHANNEL0_EQ_BITS)))
811		- break;
812		- }
813		- }
814		- /* restart */
815		- tc_write(DP0CTL, 0);
816		- usleep_range(10, 20);
817		- } while (--retry);
818		- if (retry == 0) {
819		- dev_err(tc->dev, "Failed to finish training phase %d\n",
820		- pattern);
821		- }
822		-
823		- return 0;
824		-err:
825		- return ret;
	888	+ return (value >> 8) & 0x7;
826	889	}
827	890
828		-static int tc_main_link_setup(struct tc_data *tc)
	891	+static int tc_main_link_enable(struct tc_data *tc)
829	892	{
830	893	struct drm_dp_aux *aux = &tc->aux;
831	894	struct device *dev = tc->dev;
832		- unsigned int rate;
833	895	u32 dp_phy_ctrl;
834		- int timeout;
835	896	u32 value;
836	897	int ret;
837		- u8 tmp[8];
	898	+ u8 tmp[DP_LINK_STATUS_SIZE];
838	899
839		- /* display mode should be set at this point */
840		- if (!tc->mode)
841		- return -EINVAL;
	900	+ dev_dbg(tc->dev, "link enable\n");
842	901
843		- tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
844		- /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
845		- tc_write(DP1_SRCCTRL,
846		- (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) \|
847		- ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
	902	+ ret = regmap_read(tc->regmap, DP0CTL, &value);
	903	+ if (ret)
	904	+ return ret;
848	905
849		- rate = clk_get_rate(tc->refclk);
850		- switch (rate) {
851		- case 38400000:
852		- value = REF_FREQ_38M4;
853		- break;
854		- case 26000000:
855		- value = REF_FREQ_26M;
856		- break;
857		- case 19200000:
858		- value = REF_FREQ_19M2;
859		- break;
860		- case 13000000:
861		- value = REF_FREQ_13M;
862		- break;
863		- default:
864		- return -EINVAL;
	906	+ if (WARN_ON(value & DP_EN)) {
	907	+ ret = regmap_write(tc->regmap, DP0CTL, 0);
	908	+ if (ret)
	909	+ return ret;
865	910	}
866		- value \|= SYSCLK_SEL_LSCLK \| LSCLK_DIV_2;
867		- tc_write(SYS_PLLPARAM, value);
	911	+
	912	+ ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
	913	+ if (ret)
	914	+ return ret;
	915	+ /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
	916	+ ret = regmap_write(tc->regmap, DP1_SRCCTRL,
	917	+ (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) \|
	918	+ ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
	919	+ if (ret)
	920	+ return ret;
	921	+
	922	+ ret = tc_set_syspllparam(tc);
	923	+ if (ret)
	924	+ return ret;
868	925
869	926	/* Setup Main Link */
870	927	dp_phy_ctrl = BGREN \| PWR_SW_EN \| PHY_A0_EN \| PHY_M0_EN;
871		- if (tc->link.base.num_lanes == 2)
	928	+ if (tc->link.num_lanes == 2)
872	929	dp_phy_ctrl \|= PHY_2LANE;
873		- tc_write(DP_PHY_CTRL, dp_phy_ctrl);
874		- msleep(100);
	930	+
	931	+ ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
	932	+ if (ret)
	933	+ return ret;
875	934
876	935	/* PLL setup */
877		- tc_write(DP0_PLLCTRL, PLLUPDATE \| PLLEN);
878		- tc_wait_pll_lock(tc);
	936	+ ret = tc_pllupdate(tc, DP0_PLLCTRL);
	937	+ if (ret)
	938	+ return ret;
879	939
880		- tc_write(DP1_PLLCTRL, PLLUPDATE \| PLLEN);
881		- tc_wait_pll_lock(tc);
882		-
883		- /* PXL PLL setup */
884		- if (tc_test_pattern) {
885		- ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
886		- 1000 * tc->mode->clock);
887		- if (ret)
888		- goto err;
889		- }
	940	+ ret = tc_pllupdate(tc, DP1_PLLCTRL);
	941	+ if (ret)
	942	+ return ret;
890	943
891	944	/* Reset/Enable Main Links */
892	945	dp_phy_ctrl \|= DP_PHY_RST \| PHY_M1_RST \| PHY_M0_RST;
893		- tc_write(DP_PHY_CTRL, dp_phy_ctrl);
	946	+ ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
894	947	usleep_range(100, 200);
895	948	dp_phy_ctrl &= ~(DP_PHY_RST \| PHY_M1_RST \| PHY_M0_RST);
896		- tc_write(DP_PHY_CTRL, dp_phy_ctrl);
	949	+ ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
897	950
898		- timeout = 1000;
899		- do {
900		- tc_read(DP_PHY_CTRL, &value);
901		- udelay(1);
902		- } while ((!(value & PHY_RDY)) && (--timeout));
903		-
904		- if (timeout == 0) {
	951	+ ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
	952	+ if (ret) {
905	953	dev_err(dev, "timeout waiting for phy become ready");
906		- return -ETIMEDOUT;
	954	+ return ret;
907	955	}
908	956
909	957	/* Set misc: 8 bits per color */
910	958	ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
911	959	if (ret)
912		- goto err;
	960	+ return ret;
913	961
914	962	/*
915	963	* ASSR mode
..	..	@@ -933,32 +981,121 @@
933	981
934	982	if (tmp[0] != tc->assr) {
935	983	dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
936		- tc->assr);
	984	+ tc->assr);
937	985	/* trying with disabled scrambler */
938		- tc->link.scrambler_dis = 1;
	986	+ tc->link.scrambler_dis = true;
939	987	}
940	988	}
941	989
942	990	/* Setup Link & DPRx Config for Training */
943		- ret = drm_dp_link_configure(aux, &tc->link.base);
	991	+ tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
	992	+ tmp[1] = tc->link.num_lanes;
	993	+
	994	+ if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
	995	+ tmp[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	996	+
	997	+ ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
944	998	if (ret < 0)
945	999	goto err_dpcd_write;
946	1000
947	1001	/* DOWNSPREAD_CTRL */
948	1002	tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
949	1003	/* MAIN_LINK_CHANNEL_CODING_SET */
950		- tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
	1004	+ tmp[1] = DP_SET_ANSI_8B10B;
951	1005	ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
952	1006	if (ret < 0)
953	1007	goto err_dpcd_write;
954	1008
955		- ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
956		- if (ret)
957		- goto err;
	1009	+ /* Reset voltage-swing & pre-emphasis */
	1010	+ tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 \|
	1011	+ DP_TRAIN_PRE_EMPH_LEVEL_0;
	1012	+ ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
	1013	+ if (ret < 0)
	1014	+ goto err_dpcd_write;
958	1015
959		- ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
	1016	+ /* Clock-Recovery */
	1017	+
	1018	+ /* Set DPCD 0x102 for Training Pattern 1 */
	1019	+ ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
	1020	+ DP_LINK_SCRAMBLING_DISABLE \|
	1021	+ DP_TRAINING_PATTERN_1);
960	1022	if (ret)
961		- goto err;
	1023	+ return ret;
	1024	+
	1025	+ ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
	1026	+ (15 << 28) \| /* Defer Iteration Count */
	1027	+ (15 << 24) \| /* Loop Iteration Count */
	1028	+ (0xd << 0)); /* Loop Timer Delay */
	1029	+ if (ret)
	1030	+ return ret;
	1031	+
	1032	+ ret = regmap_write(tc->regmap, DP0_SRCCTRL,
	1033	+ tc_srcctrl(tc) \| DP0_SRCCTRL_SCRMBLDIS \|
	1034	+ DP0_SRCCTRL_AUTOCORRECT \|
	1035	+ DP0_SRCCTRL_TP1);
	1036	+ if (ret)
	1037	+ return ret;
	1038	+
	1039	+ /* Enable DP0 to start Link Training */
	1040	+ ret = regmap_write(tc->regmap, DP0CTL,
	1041	+ (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
	1042	+ EF_EN : 0) \| DP_EN);
	1043	+ if (ret)
	1044	+ return ret;
	1045	+
	1046	+ /* wait */
	1047	+
	1048	+ ret = tc_wait_link_training(tc);
	1049	+ if (ret < 0)
	1050	+ return ret;
	1051	+
	1052	+ if (ret) {
	1053	+ dev_err(tc->dev, "Link training phase 1 failed: %s\n",
	1054	+ training_pattern1_errors[ret]);
	1055	+ return -ENODEV;
	1056	+ }
	1057	+
	1058	+ /* Channel Equalization */
	1059	+
	1060	+ /* Set DPCD 0x102 for Training Pattern 2 */
	1061	+ ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
	1062	+ DP_LINK_SCRAMBLING_DISABLE \|
	1063	+ DP_TRAINING_PATTERN_2);
	1064	+ if (ret)
	1065	+ return ret;
	1066	+
	1067	+ ret = regmap_write(tc->regmap, DP0_SRCCTRL,
	1068	+ tc_srcctrl(tc) \| DP0_SRCCTRL_SCRMBLDIS \|
	1069	+ DP0_SRCCTRL_AUTOCORRECT \|
	1070	+ DP0_SRCCTRL_TP2);
	1071	+ if (ret)
	1072	+ return ret;
	1073	+
	1074	+ /* wait */
	1075	+ ret = tc_wait_link_training(tc);
	1076	+ if (ret < 0)
	1077	+ return ret;
	1078	+
	1079	+ if (ret) {
	1080	+ dev_err(tc->dev, "Link training phase 2 failed: %s\n",
	1081	+ training_pattern2_errors[ret]);
	1082	+ return -ENODEV;
	1083	+ }
	1084	+
	1085	+ /*
	1086	+ * Toshiba's documentation suggests to first clear DPCD 0x102, then
	1087	+ * clear the training pattern bit in DP0_SRCCTRL. Testing shows
	1088	+ * that the link sometimes drops if those steps are done in that order,
	1089	+ * but if the steps are done in reverse order, the link stays up.
	1090	+ *
	1091	+ * So we do the steps differently than documented here.
	1092	+ */
	1093	+
	1094	+ /* Clear Training Pattern, set AutoCorrect Mode = 1 */
	1095	+ ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) \|
	1096	+ DP0_SRCCTRL_AUTOCORRECT);
	1097	+ if (ret)
	1098	+ return ret;
962	1099
963	1100	/* Clear DPCD 0x102 */
964	1101	/* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
..	..	@@ -967,47 +1104,43 @@
967	1104	if (ret < 0)
968	1105	goto err_dpcd_write;
969	1106
970		- /* Clear Training Pattern, set AutoCorrect Mode = 1 */
971		- tc_write(DP0_SRCCTRL, tc_srcctrl(tc) \| DP0_SRCCTRL_AUTOCORRECT);
	1107	+ /* Check link status */
	1108	+ ret = drm_dp_dpcd_read_link_status(aux, tmp);
	1109	+ if (ret < 0)
	1110	+ goto err_dpcd_read;
972	1111
973		- /* Wait */
974		- timeout = 100;
975		- do {
976		- udelay(1);
977		- /* Read DPCD 0x202-0x207 */
978		- ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
979		- if (ret < 0)
980		- goto err_dpcd_read;
981		- } while ((--timeout) &&
982		- !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
	1112	+ ret = 0;
983	1113
984		- if (timeout == 0) {
985		- /* Read DPCD 0x200-0x201 */
986		- ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
987		- if (ret < 0)
988		- goto err_dpcd_read;
989		- dev_err(dev, "channel(s) EQ not ok\n");
990		- dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
991		- dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
992		- tmp[1]);
993		- dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
994		- dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
995		- tmp[4]);
996		- dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
997		- dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
998		- tmp[6]);
	1114	+ value = tmp[0] & DP_CHANNEL_EQ_BITS;
999	1115
1000		- return -EAGAIN;
	1116	+ if (value != DP_CHANNEL_EQ_BITS) {
	1117	+ dev_err(tc->dev, "Lane 0 failed: %x\n", value);
	1118	+ ret = -ENODEV;
1001	1119	}
1002	1120
1003		- ret = tc_set_video_mode(tc, tc->mode);
1004		- if (ret)
1005		- goto err;
	1121	+ if (tc->link.num_lanes == 2) {
	1122	+ value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1006	1123
1007		- /* Set M/N */
1008		- ret = tc_stream_clock_calc(tc);
1009		- if (ret)
1010		- goto err;
	1124	+ if (value != DP_CHANNEL_EQ_BITS) {
	1125	+ dev_err(tc->dev, "Lane 1 failed: %x\n", value);
	1126	+ ret = -ENODEV;
	1127	+ }
	1128	+
	1129	+ if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
	1130	+ dev_err(tc->dev, "Interlane align failed\n");
	1131	+ ret = -ENODEV;
	1132	+ }
	1133	+ }
	1134	+
	1135	+ if (ret) {
	1136	+ dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
	1137	+ dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
	1138	+ dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
	1139	+ dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
	1140	+ dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
	1141	+ dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
	1142	+ return ret;
	1143	+ }
1011	1144
1012	1145	return 0;
1013	1146	err_dpcd_read:
..	..	@@ -1015,53 +1148,90 @@
1015	1148	return ret;
1016	1149	err_dpcd_write:
1017	1150	dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1018		-err:
1019	1151	return ret;
1020	1152	}
1021	1153
1022		-static int tc_main_link_stream(struct tc_data *tc, int state)
	1154	+static int tc_main_link_disable(struct tc_data *tc)
	1155	+{
	1156	+ int ret;
	1157	+
	1158	+ dev_dbg(tc->dev, "link disable\n");
	1159	+
	1160	+ ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
	1161	+ if (ret)
	1162	+ return ret;
	1163	+
	1164	+ return regmap_write(tc->regmap, DP0CTL, 0);
	1165	+}
	1166	+
	1167	+static int tc_stream_enable(struct tc_data *tc)
1023	1168	{
1024	1169	int ret;
1025	1170	u32 value;
1026	1171
1027		- dev_dbg(tc->dev, "stream: %d\n", state);
	1172	+ dev_dbg(tc->dev, "enable video stream\n");
1028	1173
1029		- if (state) {
1030		- value = VID_MN_GEN \| DP_EN;
1031		- if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1032		- value \|= EF_EN;
1033		- tc_write(DP0CTL, value);
1034		- /*
1035		- * VID_EN assertion should be delayed by at least N * LSCLK
1036		- * cycles from the time VID_MN_GEN is enabled in order to
1037		- * generate stable values for VID_M. LSCLK is 270 MHz or
1038		- * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1039		- * so a delay of at least 203 us should suffice.
1040		- */
1041		- usleep_range(500, 1000);
1042		- value \|= VID_EN;
1043		- tc_write(DP0CTL, value);
1044		- /* Set input interface */
1045		- value = DP0_AUDSRC_NO_INPUT;
1046		- if (tc_test_pattern)
1047		- value \|= DP0_VIDSRC_COLOR_BAR;
1048		- else
1049		- value \|= DP0_VIDSRC_DPI_RX;
1050		- tc_write(SYSCTRL, value);
1051		- } else {
1052		- tc_write(DP0CTL, 0);
	1174	+ /* PXL PLL setup */
	1175	+ if (tc_test_pattern) {
	1176	+ ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
	1177	+ 1000 * tc->mode.clock);
	1178	+ if (ret)
	1179	+ return ret;
1053	1180	}
1054	1181
	1182	+ ret = tc_set_video_mode(tc, &tc->mode);
	1183	+ if (ret)
	1184	+ return ret;
	1185	+
	1186	+ /* Set M/N */
	1187	+ ret = tc_stream_clock_calc(tc);
	1188	+ if (ret)
	1189	+ return ret;
	1190	+
	1191	+ value = VID_MN_GEN \| DP_EN;
	1192	+ if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
	1193	+ value \|= EF_EN;
	1194	+ ret = regmap_write(tc->regmap, DP0CTL, value);
	1195	+ if (ret)
	1196	+ return ret;
	1197	+ /*
	1198	+ * VID_EN assertion should be delayed by at least N * LSCLK
	1199	+ * cycles from the time VID_MN_GEN is enabled in order to
	1200	+ * generate stable values for VID_M. LSCLK is 270 MHz or
	1201	+ * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
	1202	+ * so a delay of at least 203 us should suffice.
	1203	+ */
	1204	+ usleep_range(500, 1000);
	1205	+ value \|= VID_EN;
	1206	+ ret = regmap_write(tc->regmap, DP0CTL, value);
	1207	+ if (ret)
	1208	+ return ret;
	1209	+ /* Set input interface */
	1210	+ value = DP0_AUDSRC_NO_INPUT;
	1211	+ if (tc_test_pattern)
	1212	+ value \|= DP0_VIDSRC_COLOR_BAR;
	1213	+ else
	1214	+ value \|= DP0_VIDSRC_DPI_RX;
	1215	+ ret = regmap_write(tc->regmap, SYSCTRL, value);
	1216	+ if (ret)
	1217	+ return ret;
	1218	+
1055	1219	return 0;
1056		-err:
1057		- return ret;
1058	1220	}
1059	1221
1060		-static void tc_bridge_pre_enable(struct drm_bridge *bridge)
	1222	+static int tc_stream_disable(struct tc_data *tc)
1061	1223	{
1062		- struct tc_data *tc = bridge_to_tc(bridge);
	1224	+ int ret;
1063	1225
1064		- drm_panel_prepare(tc->panel);
	1226	+ dev_dbg(tc->dev, "disable video stream\n");
	1227	+
	1228	+ ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
	1229	+ if (ret)
	1230	+ return ret;
	1231	+
	1232	+ tc_pxl_pll_dis(tc);
	1233	+
	1234	+ return 0;
1065	1235	}
1066	1236
1067	1237	static void tc_bridge_enable(struct drm_bridge *bridge)
..	..	@@ -1069,19 +1239,24 @@
1069	1239	struct tc_data *tc = bridge_to_tc(bridge);
1070	1240	int ret;
1071	1241
1072		- ret = tc_main_link_setup(tc);
	1242	+ ret = tc_get_display_props(tc);
1073	1243	if (ret < 0) {
1074		- dev_err(tc->dev, "main link setup error: %d\n", ret);
	1244	+ dev_err(tc->dev, "failed to read display props: %d\n", ret);
1075	1245	return;
1076	1246	}
1077	1247
1078		- ret = tc_main_link_stream(tc, 1);
	1248	+ ret = tc_main_link_enable(tc);
	1249	+ if (ret < 0) {
	1250	+ dev_err(tc->dev, "main link enable error: %d\n", ret);
	1251	+ return;
	1252	+ }
	1253	+
	1254	+ ret = tc_stream_enable(tc);
1079	1255	if (ret < 0) {
1080	1256	dev_err(tc->dev, "main link stream start error: %d\n", ret);
	1257	+ tc_main_link_disable(tc);
1081	1258	return;
1082	1259	}
1083		-
1084		- drm_panel_enable(tc->panel);
1085	1260	}
1086	1261
1087	1262	static void tc_bridge_disable(struct drm_bridge *bridge)
..	..	@@ -1089,18 +1264,13 @@
1089	1264	struct tc_data *tc = bridge_to_tc(bridge);
1090	1265	int ret;
1091	1266
1092		- drm_panel_disable(tc->panel);
1093		-
1094		- ret = tc_main_link_stream(tc, 0);
	1267	+ ret = tc_stream_disable(tc);
1095	1268	if (ret < 0)
1096	1269	dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1097		-}
1098	1270
1099		-static void tc_bridge_post_disable(struct drm_bridge *bridge)
1100		-{
1101		- struct tc_data *tc = bridge_to_tc(bridge);
1102		-
1103		- drm_panel_unprepare(tc->panel);
	1271	+ ret = tc_main_link_disable(tc);
	1272	+ if (ret < 0)
	1273	+ dev_err(tc->dev, "main link disable error: %d\n", ret);
1104	1274	}
1105	1275
1106	1276	static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
..	..	@@ -1115,10 +1285,11 @@
1115	1285	return true;
1116	1286	}
1117	1287
1118		-static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
1119		- struct drm_display_mode *mode)
	1288	+static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
	1289	+ const struct drm_display_info *info,
	1290	+ const struct drm_display_mode *mode)
1120	1291	{
1121		- struct tc_data *tc = connector_to_tc(connector);
	1292	+ struct tc_data *tc = bridge_to_tc(bridge);
1122	1293	u32 req, avail;
1123	1294	u32 bits_per_pixel = 24;
1124	1295
..	..	@@ -1127,7 +1298,7 @@
1127	1298	return MODE_CLOCK_HIGH;
1128	1299
1129	1300	req = mode->clock * bits_per_pixel / 8;
1130		- avail = tc->link.base.num_lanes * tc->link.base.rate;
	1301	+ avail = tc->link.num_lanes * tc->link.rate;
1131	1302
1132	1303	if (req > avail)
1133	1304	return MODE_BAD;
..	..	@@ -1136,19 +1307,27 @@
1136	1307	}
1137	1308
1138	1309	static void tc_bridge_mode_set(struct drm_bridge *bridge,
1139		- struct drm_display_mode *mode,
1140		- struct drm_display_mode *adj)
	1310	+ const struct drm_display_mode *mode,
	1311	+ const struct drm_display_mode *adj)
1141	1312	{
1142	1313	struct tc_data *tc = bridge_to_tc(bridge);
1143	1314
1144		- tc->mode = mode;
	1315	+ tc->mode = *mode;
	1316	+}
	1317	+
	1318	+static struct edid tc_get_edid(struct drm_bridge bridge,
	1319	+ struct drm_connector *connector)
	1320	+{
	1321	+ struct tc_data *tc = bridge_to_tc(bridge);
	1322	+
	1323	+ return drm_get_edid(connector, &tc->aux.ddc);
1145	1324	}
1146	1325
1147	1326	static int tc_connector_get_modes(struct drm_connector *connector)
1148	1327	{
1149	1328	struct tc_data *tc = connector_to_tc(connector);
	1329	+ int num_modes;
1150	1330	struct edid *edid;
1151		- unsigned int count;
1152	1331	int ret;
1153	1332
1154	1333	ret = tc_get_display_props(tc);
..	..	@@ -1157,48 +1336,58 @@
1157	1336	return 0;
1158	1337	}
1159	1338
1160		- if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1161		- count = tc->panel->funcs->get_modes(tc->panel);
1162		- if (count > 0)
1163		- return count;
	1339	+ if (tc->panel_bridge) {
	1340	+ num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
	1341	+ if (num_modes > 0)
	1342	+ return num_modes;
1164	1343	}
1165	1344
1166		- edid = drm_get_edid(connector, &tc->aux.ddc);
	1345	+ edid = tc_get_edid(&tc->bridge, connector);
	1346	+ num_modes = drm_add_edid_modes(connector, edid);
	1347	+ kfree(edid);
1167	1348
1168		- kfree(tc->edid);
1169		- tc->edid = edid;
1170		- if (!edid)
1171		- return 0;
1172		-
1173		- drm_connector_update_edid_property(connector, edid);
1174		- count = drm_add_edid_modes(connector, edid);
1175		-
1176		- return count;
1177		-}
1178		-
1179		-static void tc_connector_set_polling(struct tc_data *tc,
1180		- struct drm_connector *connector)
1181		-{
1182		- /* TODO: add support for HPD */
1183		- connector->polled = DRM_CONNECTOR_POLL_CONNECT \|
1184		- DRM_CONNECTOR_POLL_DISCONNECT;
1185		-}
1186		-
1187		-static struct drm_encoder *
1188		-tc_connector_best_encoder(struct drm_connector *connector)
1189		-{
1190		- struct tc_data *tc = connector_to_tc(connector);
1191		-
1192		- return tc->bridge.encoder;
	1349	+ return num_modes;
1193	1350	}
1194	1351
1195	1352	static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1196	1353	.get_modes = tc_connector_get_modes,
1197		- .mode_valid = tc_connector_mode_valid,
1198		- .best_encoder = tc_connector_best_encoder,
1199	1354	};
1200	1355
	1356	+static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
	1357	+{
	1358	+ struct tc_data *tc = bridge_to_tc(bridge);
	1359	+ bool conn;
	1360	+ u32 val;
	1361	+ int ret;
	1362	+
	1363	+ ret = regmap_read(tc->regmap, GPIOI, &val);
	1364	+ if (ret)
	1365	+ return connector_status_unknown;
	1366	+
	1367	+ conn = val & BIT(tc->hpd_pin);
	1368	+
	1369	+ if (conn)
	1370	+ return connector_status_connected;
	1371	+ else
	1372	+ return connector_status_disconnected;
	1373	+}
	1374	+
	1375	+static enum drm_connector_status
	1376	+tc_connector_detect(struct drm_connector *connector, bool force)
	1377	+{
	1378	+ struct tc_data *tc = connector_to_tc(connector);
	1379	+
	1380	+ if (tc->hpd_pin >= 0)
	1381	+ return tc_bridge_detect(&tc->bridge);
	1382	+
	1383	+ if (tc->panel_bridge)
	1384	+ return connector_status_connected;
	1385	+ else
	1386	+ return connector_status_unknown;
	1387	+}
	1388	+
1201	1389	static const struct drm_connector_funcs tc_connector_funcs = {
	1390	+ .detect = tc_connector_detect,
1202	1391	.fill_modes = drm_helper_probe_single_connector_modes,
1203	1392	.destroy = drm_connector_cleanup,
1204	1393	.reset = drm_atomic_helper_connector_reset,
..	..	@@ -1206,29 +1395,46 @@
1206	1395	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1207	1396	};
1208	1397
1209		-static int tc_bridge_attach(struct drm_bridge *bridge)
	1398	+static int tc_bridge_attach(struct drm_bridge *bridge,
	1399	+ enum drm_bridge_attach_flags flags)
1210	1400	{
1211	1401	u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1212	1402	struct tc_data *tc = bridge_to_tc(bridge);
1213	1403	struct drm_device *drm = bridge->dev;
1214	1404	int ret;
1215	1405
1216		- /* Create eDP connector */
	1406	+ if (tc->panel_bridge) {
	1407	+ /* If a connector is required then this driver shall create it */
	1408	+ ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
	1409	+ &tc->bridge, flags \| DRM_BRIDGE_ATTACH_NO_CONNECTOR);
	1410	+ if (ret)
	1411	+ return ret;
	1412	+ }
	1413	+
	1414	+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
	1415	+ return 0;
	1416	+
	1417	+ /* Create DP/eDP connector */
1217	1418	drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1218		- ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1219		- DRM_MODE_CONNECTOR_eDP);
	1419	+ ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1220	1420	if (ret)
1221	1421	return ret;
1222	1422
1223		- if (tc->panel)
1224		- drm_panel_attach(tc->panel, &tc->connector);
	1423	+ /* Don't poll if don't have HPD connected */
	1424	+ if (tc->hpd_pin >= 0) {
	1425	+ if (tc->have_irq)
	1426	+ tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
	1427	+ else
	1428	+ tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT \|
	1429	+ DRM_CONNECTOR_POLL_DISCONNECT;
	1430	+ }
1225	1431
1226	1432	drm_display_info_set_bus_formats(&tc->connector.display_info,
1227	1433	&bus_format, 1);
1228	1434	tc->connector.display_info.bus_flags =
1229	1435	DRM_BUS_FLAG_DE_HIGH \|
1230		- DRM_BUS_FLAG_PIXDATA_NEGEDGE \|
1231		- DRM_BUS_FLAG_SYNC_NEGEDGE;
	1436	+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE \|
	1437	+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1232	1438	drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1233	1439
1234	1440	return 0;
..	..	@@ -1236,12 +1442,13 @@
1236	1442
1237	1443	static const struct drm_bridge_funcs tc_bridge_funcs = {
1238	1444	.attach = tc_bridge_attach,
	1445	+ .mode_valid = tc_mode_valid,
1239	1446	.mode_set = tc_bridge_mode_set,
1240		- .pre_enable = tc_bridge_pre_enable,
1241	1447	.enable = tc_bridge_enable,
1242	1448	.disable = tc_bridge_disable,
1243		- .post_disable = tc_bridge_post_disable,
1244	1449	.mode_fixup = tc_bridge_mode_fixup,
	1450	+ .detect = tc_bridge_detect,
	1451	+ .get_edid = tc_get_edid,
1245	1452	};
1246	1453
1247	1454	static bool tc_readable_reg(struct device *dev, unsigned int reg)
..	..	@@ -1255,6 +1462,8 @@
1255	1462	regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1256	1463	regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1257	1464	regmap_reg_range(VFUEN0, VFUEN0),
	1465	+ regmap_reg_range(INTSTS_G, INTSTS_G),
	1466	+ regmap_reg_range(GPIOI, GPIOI),
1258	1467	};
1259	1468
1260	1469	static const struct regmap_access_table tc_volatile_table = {
..	..	@@ -1283,6 +1492,83 @@
1283	1492	.val_format_endian = REGMAP_ENDIAN_LITTLE,
1284	1493	};
1285	1494
	1495	+static irqreturn_t tc_irq_handler(int irq, void *arg)
	1496	+{
	1497	+ struct tc_data *tc = arg;
	1498	+ u32 val;
	1499	+ int r;
	1500	+
	1501	+ r = regmap_read(tc->regmap, INTSTS_G, &val);
	1502	+ if (r)
	1503	+ return IRQ_NONE;
	1504	+
	1505	+ if (!val)
	1506	+ return IRQ_NONE;
	1507	+
	1508	+ if (val & INT_SYSERR) {
	1509	+ u32 stat = 0;
	1510	+
	1511	+ regmap_read(tc->regmap, SYSSTAT, &stat);
	1512	+
	1513	+ dev_err(tc->dev, "syserr %x\n", stat);
	1514	+ }
	1515	+
	1516	+ if (tc->hpd_pin >= 0 && tc->bridge.dev) {
	1517	+ /*
	1518	+ * H is triggered when the GPIO goes high.
	1519	+ *
	1520	+ * LC is triggered when the GPIO goes low and stays low for
	1521	+ * the duration of LCNT
	1522	+ */
	1523	+ bool h = val & INT_GPIO_H(tc->hpd_pin);
	1524	+ bool lc = val & INT_GPIO_LC(tc->hpd_pin);
	1525	+
	1526	+ dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
	1527	+ h ? "H" : "", lc ? "LC" : "");
	1528	+
	1529	+ if (h \|\| lc)
	1530	+ drm_kms_helper_hotplug_event(tc->bridge.dev);
	1531	+ }
	1532	+
	1533	+ regmap_write(tc->regmap, INTSTS_G, val);
	1534	+
	1535	+ return IRQ_HANDLED;
	1536	+}
	1537	+
	1538	+static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
	1539	+{
	1540	+ struct device *dev = tc->dev;
	1541	+ struct drm_panel *panel;
	1542	+ int ret;
	1543	+
	1544	+ /* port@2 is the output port */
	1545	+ ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
	1546	+ if (ret && ret != -ENODEV)
	1547	+ return ret;
	1548	+
	1549	+ if (panel) {
	1550	+ struct drm_bridge *panel_bridge;
	1551	+
	1552	+ panel_bridge = devm_drm_panel_bridge_add(dev, panel);
	1553	+ if (IS_ERR(panel_bridge))
	1554	+ return PTR_ERR(panel_bridge);
	1555	+
	1556	+ tc->panel_bridge = panel_bridge;
	1557	+ tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
	1558	+ } else {
	1559	+ tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
	1560	+ }
	1561	+
	1562	+ return 0;
	1563	+}
	1564	+
	1565	+static void tc_clk_disable(void *data)
	1566	+{
	1567	+ struct clk *refclk = data;
	1568	+
	1569	+ clk_disable_unprepare(refclk);
	1570	+}
	1571	+
1286	1572	static int tc_probe(struct i2c_client client, const struct i2c_device_id id)
1287	1573	{
1288	1574	struct device *dev = &client->dev;
..	..	@@ -1295,10 +1581,27 @@
1295	1581
1296	1582	tc->dev = dev;
1297	1583
1298		- /* port@2 is the output port */
1299		- ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1300		- if (ret && ret != -ENODEV)
	1584	+ ret = tc_probe_edp_bridge_endpoint(tc);
	1585	+ if (ret)
1301	1586	return ret;
	1587	+
	1588	+ tc->refclk = devm_clk_get(dev, "ref");
	1589	+ if (IS_ERR(tc->refclk)) {
	1590	+ ret = PTR_ERR(tc->refclk);
	1591	+ dev_err(dev, "Failed to get refclk: %d\n", ret);
	1592	+ return ret;
	1593	+ }
	1594	+
	1595	+ ret = clk_prepare_enable(tc->refclk);
	1596	+ if (ret)
	1597	+ return ret;
	1598	+
	1599	+ ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk);
	1600	+ if (ret)
	1601	+ return ret;
	1602	+
	1603	+ /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
	1604	+ usleep_range(10, 15);
1302	1605
1303	1606	/* Shut down GPIO is optional */
1304	1607	tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
..	..	@@ -1320,18 +1623,38 @@
1320	1623	usleep_range(5000, 10000);
1321	1624	}
1322	1625
1323		- tc->refclk = devm_clk_get(dev, "ref");
1324		- if (IS_ERR(tc->refclk)) {
1325		- ret = PTR_ERR(tc->refclk);
1326		- dev_err(dev, "Failed to get refclk: %d\n", ret);
1327		- return ret;
1328		- }
1329		-
1330	1626	tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1331	1627	if (IS_ERR(tc->regmap)) {
1332	1628	ret = PTR_ERR(tc->regmap);
1333	1629	dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1334	1630	return ret;
	1631	+ }
	1632	+
	1633	+ ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
	1634	+ &tc->hpd_pin);
	1635	+ if (ret) {
	1636	+ tc->hpd_pin = -ENODEV;
	1637	+ } else {
	1638	+ if (tc->hpd_pin < 0 \|\| tc->hpd_pin > 1) {
	1639	+ dev_err(dev, "failed to parse HPD number\n");
	1640	+ return ret;
	1641	+ }
	1642	+ }
	1643	+
	1644	+ if (client->irq > 0) {
	1645	+ /* enable SysErr */
	1646	+ regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
	1647	+
	1648	+ ret = devm_request_threaded_irq(dev, client->irq,
	1649	+ NULL, tc_irq_handler,
	1650	+ IRQF_ONESHOT,
	1651	+ "tc358767-irq", tc);
	1652	+ if (ret) {
	1653	+ dev_err(dev, "failed to register dp interrupt\n");
	1654	+ return ret;
	1655	+ }
	1656	+
	1657	+ tc->have_irq = true;
1335	1658	}
1336	1659
1337	1660	ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
..	..	@@ -1347,6 +1670,38 @@
1347	1670
1348	1671	tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1349	1672
	1673	+ if (!tc->reset_gpio) {
	1674	+ /*
	1675	+ * If the reset pin isn't present, do a software reset. It isn't
	1676	+ * as thorough as the hardware reset, as we can't reset the I2C
	1677	+ * communication block for obvious reasons, but it's getting the
	1678	+ * chip into a defined state.
	1679	+ */
	1680	+ regmap_update_bits(tc->regmap, SYSRSTENB,
	1681	+ ENBLCD0 \| ENBBM \| ENBDSIRX \| ENBREG \| ENBHDCP,
	1682	+ 0);
	1683	+ regmap_update_bits(tc->regmap, SYSRSTENB,
	1684	+ ENBLCD0 \| ENBBM \| ENBDSIRX \| ENBREG \| ENBHDCP,
	1685	+ ENBLCD0 \| ENBBM \| ENBDSIRX \| ENBREG \| ENBHDCP);
	1686	+ usleep_range(5000, 10000);
	1687	+ }
	1688	+
	1689	+ if (tc->hpd_pin >= 0) {
	1690	+ u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
	1691	+ u32 h_lc = INT_GPIO_H(tc->hpd_pin) \| INT_GPIO_LC(tc->hpd_pin);
	1692	+
	1693	+ /* Set LCNT to 2ms */
	1694	+ regmap_write(tc->regmap, lcnt_reg,
	1695	+ clk_get_rate(tc->refclk) * 2 / 1000);
	1696	+ /* We need the "alternate" mode for HPD */
	1697	+ regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
	1698	+
	1699	+ if (tc->have_irq) {
	1700	+ /* enable H & LC */
	1701	+ regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
	1702	+ }
	1703	+ }
	1704	+
1350	1705	ret = tc_aux_link_setup(tc);
1351	1706	if (ret)
1352	1707	return ret;
..	..	@@ -1359,22 +1714,17 @@
1359	1714	if (ret)
1360	1715	return ret;
1361	1716
1362		- ret = tc_get_display_props(tc);
1363		- if (ret)
1364		- goto err_unregister_aux;
1365		-
1366		- tc_connector_set_polling(tc, &tc->connector);
1367		-
1368	1717	tc->bridge.funcs = &tc_bridge_funcs;
	1718	+ if (tc->hpd_pin >= 0)
	1719	+ tc->bridge.ops \|= DRM_BRIDGE_OP_DETECT;
	1720	+ tc->bridge.ops \|= DRM_BRIDGE_OP_EDID;
	1721	+
1369	1722	tc->bridge.of_node = dev->of_node;
1370	1723	drm_bridge_add(&tc->bridge);
1371	1724
1372	1725	i2c_set_clientdata(client, tc);
1373	1726
1374	1727	return 0;
1375		-err_unregister_aux:
1376		- drm_dp_aux_unregister(&tc->aux);
1377		- return ret;
1378	1728	}
1379	1729
1380	1730	static int tc_remove(struct i2c_client *client)
..	..	@@ -1383,8 +1733,6 @@
1383	1733
1384	1734	drm_bridge_remove(&tc->bridge);
1385	1735	drm_dp_aux_unregister(&tc->aux);
1386		-
1387		- tc_pxl_pll_dis(tc);
1388	1736
1389	1737	return 0;
1390	1738	}