add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
..
..
@@ -33,7 +33,6 @@
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 #include "core_status.h"
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 #include "core_types.h"
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-#include "hw_sequencer.h"
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 #include "resource.h"
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..
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@@ -115,16 +114,16 @@
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 				plane_state->clip_rect.height);
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 		SURFACE_TRACE(
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-				"plane_state->plane_size.grph.surface_size.x = %d;\n"
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-				"plane_state->plane_size.grph.surface_size.y = %d;\n"
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-				"plane_state->plane_size.grph.surface_size.width = %d;\n"
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-				"plane_state->plane_size.grph.surface_size.height = %d;\n"
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-				"plane_state->plane_size.grph.surface_pitch = %d;\n",
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-				plane_state->plane_size.grph.surface_size.x,
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-				plane_state->plane_size.grph.surface_size.y,
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-				plane_state->plane_size.grph.surface_size.width,
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-				plane_state->plane_size.grph.surface_size.height,
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-				plane_state->plane_size.grph.surface_pitch);
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+				"plane_state->plane_size.surface_size.x = %d;\n"
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+				"plane_state->plane_size.surface_size.y = %d;\n"
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+				"plane_state->plane_size.surface_size.width = %d;\n"
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+				"plane_state->plane_size.surface_size.height = %d;\n"
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+				"plane_state->plane_size.surface_pitch = %d;\n",
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+				plane_state->plane_size.surface_size.x,
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+				plane_state->plane_size.surface_size.y,
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+				plane_state->plane_size.surface_size.width,
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+				plane_state->plane_size.surface_size.height,
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+				plane_state->plane_size.surface_pitch);
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 		SURFACE_TRACE(
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@@ -202,20 +201,20 @@
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 			SURFACE_TRACE(
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 					"plane_info->color_space = %d;\n"
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 					"plane_info->format = %d;\n"
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-					"plane_info->plane_size.grph.surface_pitch = %d;\n"
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-					"plane_info->plane_size.grph.surface_size.height = %d;\n"
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-					"plane_info->plane_size.grph.surface_size.width = %d;\n"
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-					"plane_info->plane_size.grph.surface_size.x = %d;\n"
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-					"plane_info->plane_size.grph.surface_size.y = %d;\n"
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+					"plane_info->plane_size.surface_pitch = %d;\n"
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+					"plane_info->plane_size.surface_size.height = %d;\n"
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+					"plane_info->plane_size.surface_size.width = %d;\n"
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+					"plane_info->plane_size.surface_size.x = %d;\n"
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+					"plane_info->plane_size.surface_size.y = %d;\n"
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 					"plane_info->rotation = %d;\n"
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 					"plane_info->stereo_format = %d;\n",
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 					update->plane_info->color_space,
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 					update->plane_info->format,
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-					update->plane_info->plane_size.grph.surface_pitch,
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-					update->plane_info->plane_size.grph.surface_size.height,
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-					update->plane_info->plane_size.grph.surface_size.width,
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-					update->plane_info->plane_size.grph.surface_size.x,
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-					update->plane_info->plane_size.grph.surface_size.y,
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+					update->plane_info->plane_size.surface_pitch,
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+					update->plane_info->plane_size.surface_size.height,
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+					update->plane_info->plane_size.surface_size.width,
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+					update->plane_info->plane_size.surface_size.x,
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+					update->plane_info->plane_size.surface_size.y,
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 					update->plane_info->rotation,
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 					update->plane_info->stereo_format);
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..
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@@ -310,30 +309,28 @@
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 		struct resource_context *res_ctx)
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 {
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 	int i;
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-	struct dc  *core_dc = dc;
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-	int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
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+	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
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 	struct crtc_position position;
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-	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
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+	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
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 	DC_LOGGER_INIT(dc->ctx->logger);
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-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
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+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
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 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
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 		/* get_position() returns CRTC vertical/horizontal counter
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 		 * hence not applicable for underlay pipe
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 		 */
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-		if (pipe_ctx->stream == NULL
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-				 || pipe_ctx->pipe_idx == underlay_idx)
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+		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
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 			continue;
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 		pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
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 		h_pos[i] = position.horizontal_count;
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 		v_pos[i] = position.vertical_count;
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 	}
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-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
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+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
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 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
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-		if (pipe_ctx->stream == NULL)
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+		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
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 			continue;
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 		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",
..
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@@ -348,23 +345,82 @@
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 		struct dc *dc,
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 		struct dc_state *context)
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 {
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-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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+#if defined(CONFIG_DRM_AMD_DC_DCN)
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 	DC_LOGGER_INIT(dc->ctx->logger);
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 	CLOCK_TRACE("Current: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
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 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
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-			context->bw.dcn.clk.dispclk_khz,
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-			context->bw.dcn.clk.dppclk_khz,
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-			context->bw.dcn.clk.dcfclk_khz,
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-			context->bw.dcn.clk.dcfclk_deep_sleep_khz,
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-			context->bw.dcn.clk.fclk_khz,
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-			context->bw.dcn.clk.socclk_khz);
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+			context->bw_ctx.bw.dcn.clk.dispclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dppclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
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+			context->bw_ctx.bw.dcn.clk.fclk_khz,
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+			context->bw_ctx.bw.dcn.clk.socclk_khz);
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 	CLOCK_TRACE("Calculated: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
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 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
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-			context->bw.dcn.clk.dispclk_khz,
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-			context->bw.dcn.clk.dppclk_khz,
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-			context->bw.dcn.clk.dcfclk_khz,
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-			context->bw.dcn.clk.dcfclk_deep_sleep_khz,
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-			context->bw.dcn.clk.fclk_khz,
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-			context->bw.dcn.clk.socclk_khz);
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+			context->bw_ctx.bw.dcn.clk.dispclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dppclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
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+			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
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+			context->bw_ctx.bw.dcn.clk.fclk_khz,
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+			context->bw_ctx.bw.dcn.clk.socclk_khz);
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 #endif
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 }
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+
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+/**
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+ * dc_status_to_str - convert dc_status to a human readable string
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+ * @status: dc_status to be converted
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+ *
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+ * Return:
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+ * A string describing the DC status.
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+ */
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+char *dc_status_to_str(enum dc_status status)
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+{
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+	switch (status) {
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+	case DC_OK:
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+		return "DC OK";
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+	case DC_NO_CONTROLLER_RESOURCE:
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+		return "No controller resource";
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+	case DC_NO_STREAM_ENC_RESOURCE:
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+		return "No stream encoder";
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+	case DC_NO_CLOCK_SOURCE_RESOURCE:
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+		return "No clock source";
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+	case DC_FAIL_CONTROLLER_VALIDATE:
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+		return "Controller validation failure";
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+	case DC_FAIL_ENC_VALIDATE:
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+		return "Encoder validation failure";
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+	case DC_FAIL_ATTACH_SURFACES:
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+		return "Surfaces attachment failure";
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+	case DC_FAIL_DETACH_SURFACES:
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+		return "Surfaces detachment failure";
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+	case DC_FAIL_SURFACE_VALIDATE:
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+		return "Surface validation failure";
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+	case DC_NO_DP_LINK_BANDWIDTH:
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+		return "No DP link bandwidth";
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+	case DC_EXCEED_DONGLE_CAP:
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+		return "Exceed dongle capability";
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+	case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
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+		return "Unsupported pixel format";
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+	case DC_FAIL_BANDWIDTH_VALIDATE:
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+		return "Bandwidth validation failure (BW and Watermark)";
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+	case DC_FAIL_SCALING:
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+		return "Scaling failure";
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+	case DC_FAIL_DP_LINK_TRAINING:
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+		return "DP link training failure";
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+	case DC_FAIL_DSC_VALIDATE:
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+		return "DSC validation failure";
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+	case DC_NO_DSC_RESOURCE:
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+		return "No DSC resource";
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+	case DC_FAIL_UNSUPPORTED_1:
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+		return "Unsupported";
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+	case DC_FAIL_CLK_EXCEED_MAX:
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+		return "Clk exceed max failure";
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+	case DC_FAIL_CLK_BELOW_MIN:
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+		return "Fail clk below minimum";
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+	case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
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+		return "Fail clk below required CFG (hard_min in PPLIB)";
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+	case DC_ERROR_UNEXPECTED:
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+		return "Unexpected error";
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+	}
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+
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+	return "Unexpected status error";
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+}