add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/clk/zynq/clkc.c
..
..
@@ -1,21 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Zynq clock controller
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  *
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  *  Copyright (C) 2012 - 2013 Xilinx
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  *
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  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
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- *
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- * This program is free software: you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License v2 as published by
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- * the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #include <linux/clk/zynq.h>
..
..
@@ -158,7 +147,7 @@
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 	clks[fclk] = clk_register_gate(NULL, clk_name,
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 			div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
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 			0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
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-	enable_reg = clk_readl(fclk_gate_reg) & 1;
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+	enable_reg = readl(fclk_gate_reg) & 1;
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 	if (enable && !enable_reg) {
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 		if (clk_prepare_enable(clks[fclk]))
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 			pr_warn("%s: FCLK%u enable failed\n", __func__,
..
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@@ -287,7 +276,7 @@
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 			SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
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 	/* CPU clocks */
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-	tmp = clk_readl(SLCR_621_TRUE) & 1;
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+	tmp = readl(SLCR_621_TRUE) & 1;
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 	clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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 			CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
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 			&armclk_lock);
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@@ -510,7 +499,7 @@
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 			&dbgclk_lock);
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 	/* leave debug clocks in the state the bootloader set them up to */
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-	tmp = clk_readl(SLCR_DBG_CLK_CTRL);
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+	tmp = readl(SLCR_DBG_CLK_CTRL);
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 	if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
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 		if (clk_prepare_enable(clks[dbg_trc]))
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 			pr_warn("%s: trace clk enable failed\n", __func__);
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@@ -602,7 +591,7 @@
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 	}
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 	if (of_address_to_resource(np, 0, &res)) {
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-		pr_err("%s: failed to get resource\n", np->name);
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+		pr_err("%pOFn: failed to get resource\n", np);
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 		goto np_err;
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 	}
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..
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@@ -611,7 +600,7 @@
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 	if (slcr->data) {
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 		zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
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 	} else {
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-		pr_err("%s: Unable to get I/O memory\n", np->name);
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+		pr_err("%pOFn: Unable to get I/O memory\n", np);
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 		of_node_put(slcr);
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 		goto np_err;
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 	}