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2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/clk/tegra/clk-tegra114.c
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #include <linux/io.h>
....@@ -746,8 +735,9 @@
746735 	[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
747736 	[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
748737 	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
749
-	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
750
-	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
738
+	[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
739
+	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
740
+	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
751741 	[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
752742 	[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
753743 	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
....@@ -789,10 +779,6 @@
789779 	[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
790780 	[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
791781 	[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
792
-	[tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
793
-	[tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
794
-	[tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
795
-	[tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
796782 	[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
797783 	[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
798784 	[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
....@@ -814,9 +800,6 @@
814800 	[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
815801 	[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
816802 	[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
817
-	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
818
-	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
819
-	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
820803 	[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
821804 	[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
822805 	[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
....@@ -826,8 +809,9 @@
826809 	{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
827810 	{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
828811 	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
829
-	{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
830
-	{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
812
+	{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
813
+	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
814
+	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
831815 	{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
832816 	{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
833817 	{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
....@@ -874,10 +858,9 @@
874858 	{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
875859 	{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
876860 	{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
877
-	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
878
-	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
879
-	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
880
-	{ .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
861
+	{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
862
+	{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
863
+	{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
881864 	{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
882865 	{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
883866 	{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
....@@ -911,17 +894,6 @@
911894 	/* clk_32k */
912895 	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
913896 	clks[TEGRA114_CLK_CLK_32K] = clk;
914
-
915
-	/* clk_m_div2 */
916
-	clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
917
-					CLK_SET_RATE_PARENT, 1, 2);
918
-	clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
919
-
920
-	/* clk_m_div4 */
921
-	clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
922
-					CLK_SET_RATE_PARENT, 1, 4);
923
-	clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
924
-
925897 }
926898 
927899 static void __init tegra114_pll_init(void __iomem *clk_base,
....@@ -1164,11 +1136,8 @@
11641136 	{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
11651137 	{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
11661138 	{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1167
-	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
1168
-	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
1169
-	{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
1170
-	{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
1171
-	{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
1139
+	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
1140
+	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
11721141 	{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
11731142 	{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
11741143 	{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
....@@ -1348,6 +1317,7 @@
13481317 	}
13491318 
13501319 	pmc_base = of_iomap(node, 0);
1320
+	of_node_put(node);
13511321 	if (!pmc_base) {
13521322 		pr_err("Can't map pmc registers\n");
13531323 		WARN_ON(1);
....@@ -1370,7 +1340,6 @@
13701340 	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
13711341 			     tegra114_audio_plls,
13721342 			     ARRAY_SIZE(tegra114_audio_plls), 24000000);
1373
-	tegra_pmc_clk_init(pmc_base, tegra114_clks);
13741343 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
13751344 					&pll_x_params);
13761345