add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/clk/tegra/clk-super.c
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/kernel.h>
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@@ -38,6 +27,9 @@
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 #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
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 #define super_state_to_src_shift(m, s) ((m->width * s))
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 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
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+
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+#define CCLK_SRC_PLLP_OUT0 4
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+#define CCLK_SRC_PLLP_OUT4 5
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 static u8 clk_super_get_parent(struct clk_hw *hw)
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 {
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@@ -108,11 +100,22 @@
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 		if (index == mux->div2_index)
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 			index = mux->pllx_index;
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 	}
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+
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+	/* enable PLLP branches to CPU before selecting PLLP source */
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+	if ((mux->flags & TEGRA210_CPU_CLK) &&
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+	    (index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4))
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+		tegra_clk_set_pllp_out_cpu(true);
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+
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 	val &= ~((super_state_to_src_mask(mux)) << shift);
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 	val |= (index & (super_state_to_src_mask(mux))) << shift;
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 	writel_relaxed(val, mux->reg);
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 	udelay(2);
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+
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+	/* disable PLLP branches to CPU if not used */
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+	if ((mux->flags & TEGRA210_CPU_CLK) &&
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+	    index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
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+		tegra_clk_set_pllp_out_cpu(false);
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 out:
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 	if (mux->lock)
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@@ -121,9 +124,21 @@
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 	return err;
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 }
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-const struct clk_ops tegra_clk_super_mux_ops = {
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+static void clk_super_mux_restore_context(struct clk_hw *hw)
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+{
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+	int parent_id;
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+
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+	parent_id = clk_hw_get_parent_index(hw);
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+	if (WARN_ON(parent_id < 0))
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+		return;
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+
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+	clk_super_set_parent(hw, parent_id);
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+}
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+
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+static const struct clk_ops tegra_clk_super_mux_ops = {
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 	.get_parent = clk_super_get_parent,
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 	.set_parent = clk_super_set_parent,
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+	.restore_context = clk_super_mux_restore_context,
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 };
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 static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
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@@ -159,12 +174,27 @@
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 	return super->div_ops->set_rate(div_hw, rate, parent_rate);
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 }
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+static void clk_super_restore_context(struct clk_hw *hw)
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+{
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+	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
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+	struct clk_hw *div_hw = &super->frac_div.hw;
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+	int parent_id;
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+
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+	parent_id = clk_hw_get_parent_index(hw);
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+	if (WARN_ON(parent_id < 0))
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+		return;
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+
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+	super->div_ops->restore_context(div_hw);
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+	clk_super_set_parent(hw, parent_id);
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+}
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+
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 const struct clk_ops tegra_clk_super_ops = {
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 	.get_parent = clk_super_get_parent,
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 	.set_parent = clk_super_set_parent,
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 	.set_rate = clk_super_set_rate,
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 	.round_rate = clk_super_round_rate,
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 	.recalc_rate = clk_super_recalc_rate,
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+	.restore_context = clk_super_restore_context,
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 };
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 struct clk *tegra_clk_register_super_mux(const char *name,
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@@ -174,7 +204,7 @@
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 {
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 	struct tegra_clk_super_mux *super;
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 	struct clk *clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	super = kzalloc(sizeof(*super), GFP_KERNEL);
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 	if (!super)
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@@ -210,7 +240,7 @@
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 {
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 	struct tegra_clk_super_mux *super;
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 	struct clk *clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	super = kzalloc(sizeof(*super), GFP_KERNEL);
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 	if (!super)