add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/clk/tegra/clk-periph-gate.c
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/clk-provider.h>
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@@ -59,18 +48,9 @@
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 	return state;
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 }
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-static int clk_periph_enable(struct clk_hw *hw)
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+static void clk_periph_enable_locked(struct clk_hw *hw)
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 {
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 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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-	unsigned long flags = 0;
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-
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-	spin_lock_irqsave(&periph_ref_lock, flags);
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-
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-	gate->enable_refcnt[gate->clk_num]++;
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-	if (gate->enable_refcnt[gate->clk_num] > 1) {
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-		spin_unlock_irqrestore(&periph_ref_lock, flags);
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-		return 0;
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-	}
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 	write_enb_set(periph_clk_to_bit(gate), gate);
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 	udelay(2);
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@@ -89,6 +69,32 @@
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 		udelay(1);
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 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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 	}
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+}
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+
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+static void clk_periph_disable_locked(struct clk_hw *hw)
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+{
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+	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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+
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+	/*
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+	 * If peripheral is in the APB bus then read the APB bus to
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+	 * flush the write operation in apb bus. This will avoid the
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+	 * peripheral access after disabling clock
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+	 */
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+	if (gate->flags & TEGRA_PERIPH_ON_APB)
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+		tegra_read_chipid();
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+
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+	write_enb_clr(periph_clk_to_bit(gate), gate);
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+}
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+
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+static int clk_periph_enable(struct clk_hw *hw)
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+{
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+	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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+	unsigned long flags = 0;
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+
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+	spin_lock_irqsave(&periph_ref_lock, flags);
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+
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+	if (!gate->enable_refcnt[gate->clk_num]++)
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+		clk_periph_enable_locked(hw);
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 	spin_unlock_irqrestore(&periph_ref_lock, flags);
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@@ -102,21 +108,28 @@
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 	spin_lock_irqsave(&periph_ref_lock, flags);
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-	gate->enable_refcnt[gate->clk_num]--;
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-	if (gate->enable_refcnt[gate->clk_num] > 0) {
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-		spin_unlock_irqrestore(&periph_ref_lock, flags);
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-		return;
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-	}
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+	WARN_ON(!gate->enable_refcnt[gate->clk_num]);
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+
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+	if (--gate->enable_refcnt[gate->clk_num] == 0)
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+		clk_periph_disable_locked(hw);
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+
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+	spin_unlock_irqrestore(&periph_ref_lock, flags);
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+}
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+
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+static void clk_periph_disable_unused(struct clk_hw *hw)
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+{
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+	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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+	unsigned long flags = 0;
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+
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+	spin_lock_irqsave(&periph_ref_lock, flags);
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 	/*
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-	 * If peripheral is in the APB bus then read the APB bus to
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-	 * flush the write operation in apb bus. This will avoid the
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-	 * peripheral access after disabling clock
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+	 * Some clocks are duplicated and some of them are marked as critical,
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+	 * like fuse and fuse_burn for example, thus the enable_refcnt will
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+	 * be non-zero here if the "unused" duplicate is disabled by CCF.
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 	 */
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-	if (gate->flags & TEGRA_PERIPH_ON_APB)
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-		tegra_read_chipid();
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-
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-	write_enb_clr(periph_clk_to_bit(gate), gate);
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+	if (!gate->enable_refcnt[gate->clk_num])
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+		clk_periph_disable_locked(hw);
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 	spin_unlock_irqrestore(&periph_ref_lock, flags);
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 }
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@@ -125,6 +138,7 @@
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 	.is_enabled = clk_periph_is_enabled,
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 	.enable = clk_periph_enable,
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 	.disable = clk_periph_disable,
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+	.disable_unused = clk_periph_disable_unused,
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 };
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 struct clk *tegra_clk_register_periph_gate(const char *name,
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@@ -133,7 +147,7 @@
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 {
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 	struct tegra_clk_periph_gate *gate;
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 	struct clk *clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	const struct tegra_clk_periph_regs *pregs;
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 	pregs = get_reg_bank(clk_num);
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@@ -158,9 +172,6 @@
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 	gate->flags = gate_flags;
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 	gate->enable_refcnt = enable_refcnt;
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 	gate->regs = pregs;
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-
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-	if (read_enb(gate) & periph_clk_to_bit(gate))
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-		enable_refcnt[clk_num]++;
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 	/* Data in .init is copied by clk_register(), so stack variable OK */
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 	gate->hw.init = &init;