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2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/clk/qcom/gcc-sdm845.c
....@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
3
+ * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
44  */
55 
66 #include <linux/kernel.h>
....@@ -96,22 +96,6 @@
9696 
9797 static const char * const gcc_parent_names_4[] = {
9898 	"bi_tcxo",
99
-	"core_bi_pll_test_se",
100
-};
101
-
102
-static const struct parent_map gcc_parent_map_5[] = {
103
-	{ P_BI_TCXO, 0 },
104
-	{ P_GPLL0_OUT_MAIN, 1 },
105
-	{ P_GPLL4_OUT_MAIN, 5 },
106
-	{ P_GPLL0_OUT_EVEN, 6 },
107
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
108
-};
109
-
110
-static const char * const gcc_parent_names_5[] = {
111
-	"bi_tcxo",
112
-	"gpll0",
113
-	"gpll4",
114
-	"gpll0_out_even",
11599 	"core_bi_pll_test_se",
116100 };
117101 
....@@ -362,6 +346,28 @@
362346 	},
363347 };
364348 
349
+static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
350
+	F(19200000, P_BI_TCXO, 1, 0, 0),
351
+	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
352
+	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
353
+	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
354
+	{ }
355
+};
356
+
357
+static struct clk_rcg2 gcc_qspi_core_clk_src = {
358
+	.cmd_rcgr = 0x4b008,
359
+	.mnd_width = 0,
360
+	.hid_width = 5,
361
+	.parent_map = gcc_parent_map_0,
362
+	.freq_tbl = ftbl_gcc_qspi_core_clk_src,
363
+	.clkr.hw.init = &(struct clk_init_data){
364
+		.name = "gcc_qspi_core_clk_src",
365
+		.parent_names = gcc_parent_names_0,
366
+		.num_parents = 4,
367
+		.ops = &clk_rcg2_floor_ops,
368
+	},
369
+};
370
+
365371 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
366372 	F(9600000, P_BI_TCXO, 2, 0, 0),
367373 	F(19200000, P_BI_TCXO, 1, 0, 0),
....@@ -402,18 +408,27 @@
402408 	{ }
403409 };
404410 
411
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
412
+	.name = "gcc_qupv3_wrap0_s0_clk_src",
413
+	.parent_names = gcc_parent_names_0,
414
+	.num_parents = 4,
415
+	.ops = &clk_rcg2_shared_ops,
416
+};
417
+
405418 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
406419 	.cmd_rcgr = 0x17034,
407420 	.mnd_width = 16,
408421 	.hid_width = 5,
409422 	.parent_map = gcc_parent_map_0,
410423 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
411
-	.clkr.hw.init = &(struct clk_init_data){
412
-		.name = "gcc_qupv3_wrap0_s0_clk_src",
413
-		.parent_names = gcc_parent_names_0,
414
-		.num_parents = 4,
415
-		.ops = &clk_rcg2_shared_ops,
416
-	},
424
+	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
425
+};
426
+
427
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
428
+	.name = "gcc_qupv3_wrap0_s1_clk_src",
429
+	.parent_names = gcc_parent_names_0,
430
+	.num_parents = 4,
431
+	.ops = &clk_rcg2_shared_ops,
417432 };
418433 
419434 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
....@@ -422,12 +437,14 @@
422437 	.hid_width = 5,
423438 	.parent_map = gcc_parent_map_0,
424439 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
425
-	.clkr.hw.init = &(struct clk_init_data){
426
-		.name = "gcc_qupv3_wrap0_s1_clk_src",
427
-		.parent_names = gcc_parent_names_0,
428
-		.num_parents = 4,
429
-		.ops = &clk_rcg2_shared_ops,
430
-	},
440
+	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
441
+};
442
+
443
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
444
+	.name = "gcc_qupv3_wrap0_s2_clk_src",
445
+	.parent_names = gcc_parent_names_0,
446
+	.num_parents = 4,
447
+	.ops = &clk_rcg2_shared_ops,
431448 };
432449 
433450 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
....@@ -436,12 +453,14 @@
436453 	.hid_width = 5,
437454 	.parent_map = gcc_parent_map_0,
438455 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
439
-	.clkr.hw.init = &(struct clk_init_data){
440
-		.name = "gcc_qupv3_wrap0_s2_clk_src",
441
-		.parent_names = gcc_parent_names_0,
442
-		.num_parents = 4,
443
-		.ops = &clk_rcg2_shared_ops,
444
-	},
456
+	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
457
+};
458
+
459
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
460
+	.name = "gcc_qupv3_wrap0_s3_clk_src",
461
+	.parent_names = gcc_parent_names_0,
462
+	.num_parents = 4,
463
+	.ops = &clk_rcg2_shared_ops,
445464 };
446465 
447466 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
....@@ -450,12 +469,14 @@
450469 	.hid_width = 5,
451470 	.parent_map = gcc_parent_map_0,
452471 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
453
-	.clkr.hw.init = &(struct clk_init_data){
454
-		.name = "gcc_qupv3_wrap0_s3_clk_src",
455
-		.parent_names = gcc_parent_names_0,
456
-		.num_parents = 4,
457
-		.ops = &clk_rcg2_shared_ops,
458
-	},
472
+	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
473
+};
474
+
475
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
476
+	.name = "gcc_qupv3_wrap0_s4_clk_src",
477
+	.parent_names = gcc_parent_names_0,
478
+	.num_parents = 4,
479
+	.ops = &clk_rcg2_shared_ops,
459480 };
460481 
461482 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
....@@ -464,12 +485,14 @@
464485 	.hid_width = 5,
465486 	.parent_map = gcc_parent_map_0,
466487 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
467
-	.clkr.hw.init = &(struct clk_init_data){
468
-		.name = "gcc_qupv3_wrap0_s4_clk_src",
469
-		.parent_names = gcc_parent_names_0,
470
-		.num_parents = 4,
471
-		.ops = &clk_rcg2_shared_ops,
472
-	},
488
+	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
489
+};
490
+
491
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
492
+	.name = "gcc_qupv3_wrap0_s5_clk_src",
493
+	.parent_names = gcc_parent_names_0,
494
+	.num_parents = 4,
495
+	.ops = &clk_rcg2_shared_ops,
473496 };
474497 
475498 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
....@@ -478,12 +501,14 @@
478501 	.hid_width = 5,
479502 	.parent_map = gcc_parent_map_0,
480503 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
481
-	.clkr.hw.init = &(struct clk_init_data){
482
-		.name = "gcc_qupv3_wrap0_s5_clk_src",
483
-		.parent_names = gcc_parent_names_0,
484
-		.num_parents = 4,
485
-		.ops = &clk_rcg2_shared_ops,
486
-	},
504
+	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
505
+};
506
+
507
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
508
+	.name = "gcc_qupv3_wrap0_s6_clk_src",
509
+	.parent_names = gcc_parent_names_0,
510
+	.num_parents = 4,
511
+	.ops = &clk_rcg2_shared_ops,
487512 };
488513 
489514 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
....@@ -492,12 +517,14 @@
492517 	.hid_width = 5,
493518 	.parent_map = gcc_parent_map_0,
494519 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
495
-	.clkr.hw.init = &(struct clk_init_data){
496
-		.name = "gcc_qupv3_wrap0_s6_clk_src",
497
-		.parent_names = gcc_parent_names_0,
498
-		.num_parents = 4,
499
-		.ops = &clk_rcg2_shared_ops,
500
-	},
520
+	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
521
+};
522
+
523
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
524
+	.name = "gcc_qupv3_wrap0_s7_clk_src",
525
+	.parent_names = gcc_parent_names_0,
526
+	.num_parents = 4,
527
+	.ops = &clk_rcg2_shared_ops,
501528 };
502529 
503530 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
....@@ -506,12 +533,14 @@
506533 	.hid_width = 5,
507534 	.parent_map = gcc_parent_map_0,
508535 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
509
-	.clkr.hw.init = &(struct clk_init_data){
510
-		.name = "gcc_qupv3_wrap0_s7_clk_src",
511
-		.parent_names = gcc_parent_names_0,
512
-		.num_parents = 4,
513
-		.ops = &clk_rcg2_shared_ops,
514
-	},
536
+	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
537
+};
538
+
539
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
540
+	.name = "gcc_qupv3_wrap1_s0_clk_src",
541
+	.parent_names = gcc_parent_names_0,
542
+	.num_parents = 4,
543
+	.ops = &clk_rcg2_shared_ops,
515544 };
516545 
517546 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
....@@ -520,12 +549,14 @@
520549 	.hid_width = 5,
521550 	.parent_map = gcc_parent_map_0,
522551 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
523
-	.clkr.hw.init = &(struct clk_init_data){
524
-		.name = "gcc_qupv3_wrap1_s0_clk_src",
525
-		.parent_names = gcc_parent_names_0,
526
-		.num_parents = 4,
527
-		.ops = &clk_rcg2_shared_ops,
528
-	},
552
+	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
553
+};
554
+
555
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
556
+	.name = "gcc_qupv3_wrap1_s1_clk_src",
557
+	.parent_names = gcc_parent_names_0,
558
+	.num_parents = 4,
559
+	.ops = &clk_rcg2_shared_ops,
529560 };
530561 
531562 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
....@@ -534,12 +565,14 @@
534565 	.hid_width = 5,
535566 	.parent_map = gcc_parent_map_0,
536567 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
537
-	.clkr.hw.init = &(struct clk_init_data){
538
-		.name = "gcc_qupv3_wrap1_s1_clk_src",
539
-		.parent_names = gcc_parent_names_0,
540
-		.num_parents = 4,
541
-		.ops = &clk_rcg2_shared_ops,
542
-	},
568
+	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
569
+};
570
+
571
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
572
+	.name = "gcc_qupv3_wrap1_s2_clk_src",
573
+	.parent_names = gcc_parent_names_0,
574
+	.num_parents = 4,
575
+	.ops = &clk_rcg2_shared_ops,
543576 };
544577 
545578 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
....@@ -548,12 +581,14 @@
548581 	.hid_width = 5,
549582 	.parent_map = gcc_parent_map_0,
550583 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
551
-	.clkr.hw.init = &(struct clk_init_data){
552
-		.name = "gcc_qupv3_wrap1_s2_clk_src",
553
-		.parent_names = gcc_parent_names_0,
554
-		.num_parents = 4,
555
-		.ops = &clk_rcg2_shared_ops,
556
-	},
584
+	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
585
+};
586
+
587
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
588
+	.name = "gcc_qupv3_wrap1_s3_clk_src",
589
+	.parent_names = gcc_parent_names_0,
590
+	.num_parents = 4,
591
+	.ops = &clk_rcg2_shared_ops,
557592 };
558593 
559594 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
....@@ -562,12 +597,14 @@
562597 	.hid_width = 5,
563598 	.parent_map = gcc_parent_map_0,
564599 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
565
-	.clkr.hw.init = &(struct clk_init_data){
566
-		.name = "gcc_qupv3_wrap1_s3_clk_src",
567
-		.parent_names = gcc_parent_names_0,
568
-		.num_parents = 4,
569
-		.ops = &clk_rcg2_shared_ops,
570
-	},
600
+	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
601
+};
602
+
603
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
604
+	.name = "gcc_qupv3_wrap1_s4_clk_src",
605
+	.parent_names = gcc_parent_names_0,
606
+	.num_parents = 4,
607
+	.ops = &clk_rcg2_shared_ops,
571608 };
572609 
573610 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
....@@ -576,12 +613,14 @@
576613 	.hid_width = 5,
577614 	.parent_map = gcc_parent_map_0,
578615 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
579
-	.clkr.hw.init = &(struct clk_init_data){
580
-		.name = "gcc_qupv3_wrap1_s4_clk_src",
581
-		.parent_names = gcc_parent_names_0,
582
-		.num_parents = 4,
583
-		.ops = &clk_rcg2_shared_ops,
584
-	},
616
+	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
617
+};
618
+
619
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
620
+	.name = "gcc_qupv3_wrap1_s5_clk_src",
621
+	.parent_names = gcc_parent_names_0,
622
+	.num_parents = 4,
623
+	.ops = &clk_rcg2_shared_ops,
585624 };
586625 
587626 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
....@@ -590,12 +629,14 @@
590629 	.hid_width = 5,
591630 	.parent_map = gcc_parent_map_0,
592631 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
593
-	.clkr.hw.init = &(struct clk_init_data){
594
-		.name = "gcc_qupv3_wrap1_s5_clk_src",
595
-		.parent_names = gcc_parent_names_0,
596
-		.num_parents = 4,
597
-		.ops = &clk_rcg2_shared_ops,
598
-	},
632
+	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
633
+};
634
+
635
+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
636
+	.name = "gcc_qupv3_wrap1_s6_clk_src",
637
+	.parent_names = gcc_parent_names_0,
638
+	.num_parents = 4,
639
+	.ops = &clk_rcg2_shared_ops,
599640 };
600641 
601642 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
....@@ -604,12 +645,14 @@
604645 	.hid_width = 5,
605646 	.parent_map = gcc_parent_map_0,
606647 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
607
-	.clkr.hw.init = &(struct clk_init_data){
608
-		.name = "gcc_qupv3_wrap1_s6_clk_src",
609
-		.parent_names = gcc_parent_names_0,
610
-		.num_parents = 4,
611
-		.ops = &clk_rcg2_shared_ops,
612
-	},
648
+	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
649
+};
650
+
651
+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
652
+	.name = "gcc_qupv3_wrap1_s7_clk_src",
653
+	.parent_names = gcc_parent_names_0,
654
+	.num_parents = 4,
655
+	.ops = &clk_rcg2_shared_ops,
613656 };
614657 
615658 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
....@@ -618,12 +661,7 @@
618661 	.hid_width = 5,
619662 	.parent_map = gcc_parent_map_0,
620663 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
621
-	.clkr.hw.init = &(struct clk_init_data){
622
-		.name = "gcc_qupv3_wrap1_s7_clk_src",
623
-		.parent_names = gcc_parent_names_0,
624
-		.num_parents = 4,
625
-		.ops = &clk_rcg2_shared_ops,
626
-	},
664
+	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
627665 };
628666 
629667 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
....@@ -1306,7 +1344,7 @@
13061344 				"gpll0",
13071345 			},
13081346 			.num_parents = 1,
1309
-			.ops = &clk_branch2_ops,
1347
+			.ops = &clk_branch2_aon_ops,
13101348 		},
13111349 	},
13121350 };
....@@ -1665,6 +1703,9 @@
16651703 		.enable_mask = BIT(4),
16661704 		.hw.init = &(struct clk_init_data){
16671705 			.name = "gcc_pcie_0_pipe_clk",
1706
+			.parent_names = (const char *[]){ "pcie_0_pipe_clk" },
1707
+			.num_parents = 1,
1708
+			.flags = CLK_SET_RATE_PARENT,
16681709 			.ops = &clk_branch2_ops,
16691710 		},
16701711 	},
....@@ -1764,6 +1805,8 @@
17641805 		.enable_mask = BIT(30),
17651806 		.hw.init = &(struct clk_init_data){
17661807 			.name = "gcc_pcie_1_pipe_clk",
1808
+			.parent_names = (const char *[]){ "pcie_1_pipe_clk" },
1809
+			.num_parents = 1,
17671810 			.ops = &clk_branch2_ops,
17681811 		},
17691812 	},
....@@ -1934,6 +1977,37 @@
19341977 		.enable_mask = BIT(0),
19351978 		.hw.init = &(struct clk_init_data){
19361979 			.name = "gcc_qmip_video_ahb_clk",
1980
+			.ops = &clk_branch2_ops,
1981
+		},
1982
+	},
1983
+};
1984
+
1985
+static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1986
+	.halt_reg = 0x4b000,
1987
+	.halt_check = BRANCH_HALT,
1988
+	.clkr = {
1989
+		.enable_reg = 0x4b000,
1990
+		.enable_mask = BIT(0),
1991
+		.hw.init = &(struct clk_init_data){
1992
+			.name = "gcc_qspi_cnoc_periph_ahb_clk",
1993
+			.ops = &clk_branch2_ops,
1994
+		},
1995
+	},
1996
+};
1997
+
1998
+static struct clk_branch gcc_qspi_core_clk = {
1999
+	.halt_reg = 0x4b004,
2000
+	.halt_check = BRANCH_HALT,
2001
+	.clkr = {
2002
+		.enable_reg = 0x4b004,
2003
+		.enable_mask = BIT(0),
2004
+		.hw.init = &(struct clk_init_data){
2005
+			.name = "gcc_qspi_core_clk",
2006
+			.parent_names = (const char *[]){
2007
+				"gcc_qspi_core_clk_src",
2008
+			},
2009
+			.num_parents = 1,
2010
+			.flags = CLK_SET_RATE_PARENT,
19372011 			.ops = &clk_branch2_ops,
19382012 		},
19392013 	},
....@@ -3090,6 +3164,37 @@
30903164 	},
30913165 };
30923166 
3167
+/* TODO: Remove after DTS updated to protect these */
3168
+#ifdef CONFIG_SDM_LPASSCC_845
3169
+static struct clk_branch gcc_lpass_q6_axi_clk = {
3170
+	.halt_reg = 0x47000,
3171
+	.halt_check = BRANCH_HALT,
3172
+	.clkr = {
3173
+		.enable_reg = 0x47000,
3174
+		.enable_mask = BIT(0),
3175
+		.hw.init = &(struct clk_init_data){
3176
+			.name = "gcc_lpass_q6_axi_clk",
3177
+			.flags = CLK_IS_CRITICAL,
3178
+			.ops = &clk_branch2_ops,
3179
+		},
3180
+	},
3181
+};
3182
+
3183
+static struct clk_branch gcc_lpass_sway_clk = {
3184
+	.halt_reg = 0x47008,
3185
+	.halt_check = BRANCH_HALT,
3186
+	.clkr = {
3187
+		.enable_reg = 0x47008,
3188
+		.enable_mask = BIT(0),
3189
+		.hw.init = &(struct clk_init_data){
3190
+			.name = "gcc_lpass_sway_clk",
3191
+			.flags = CLK_IS_CRITICAL,
3192
+			.ops = &clk_branch2_ops,
3193
+		},
3194
+	},
3195
+};
3196
+#endif
3197
+
30933198 static struct gdsc pcie_0_gdsc = {
30943199 	.gdscr = 0x6b004,
30953200 	.pd = {
....@@ -3394,6 +3499,13 @@
33943499 	[GPLL4] = &gpll4.clkr,
33953500 	[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
33963501 	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3502
+	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3503
+	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3504
+	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3505
+#ifdef CONFIG_SDM_LPASSCC_845
3506
+	[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3507
+	[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3508
+#endif
33973509 };
33983510 
33993511 static const struct qcom_reset_map gcc_sdm845_resets[] = {
....@@ -3471,9 +3583,29 @@
34713583 };
34723584 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
34733585 
3586
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3587
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3588
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3589
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3590
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3591
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3592
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3593
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3594
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3595
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3596
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3597
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3598
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3599
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3600
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3601
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3602
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3603
+};
3604
+
34743605 static int gcc_sdm845_probe(struct platform_device *pdev)
34753606 {
34763607 	struct regmap *regmap;
3608
+	int ret;
34773609 
34783610 	regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
34793611 	if (IS_ERR(regmap))
....@@ -3483,6 +3615,11 @@
34833615 	regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
34843616 	regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
34853617 
3618
+	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3619
+					ARRAY_SIZE(gcc_dfs_clocks));
3620
+	if (ret)
3621
+		return ret;
3622
+
34863623 	return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
34873624 }
34883625 
....@@ -3491,6 +3628,7 @@
34913628 	.driver		= {
34923629 		.name	= "gcc-sdm845",
34933630 		.of_match_table = gcc_sdm845_match_table,
3631
+		.sync_state = clk_sync_state,
34943632 	},
34953633 };
34963634 
....@@ -3498,7 +3636,7 @@
34983636 {
34993637 	return platform_driver_register(&gcc_sdm845_driver);
35003638 }
3501
-subsys_initcall(gcc_sdm845_init);
3639
+core_initcall(gcc_sdm845_init);
35023640 
35033641 static void __exit gcc_sdm845_exit(void)
35043642 {