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2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/drivers/clk/qcom/clk-rpmh.c
....@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
3
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
44  */
55 
66 #include <linux/clk-provider.h>
....@@ -12,11 +12,26 @@
1212 #include <linux/platform_device.h>
1313 #include <soc/qcom/cmd-db.h>
1414 #include <soc/qcom/rpmh.h>
15
+#include <soc/qcom/tcs.h>
1516 
1617 #include <dt-bindings/clock/qcom,rpmh.h>
1718 
1819 #define CLK_RPMH_ARC_EN_OFFSET		0
1920 #define CLK_RPMH_VRM_EN_OFFSET		4
21
+
22
+/**
23
+ * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
24
+ * @unit: divisor used to convert Hz value to an RPMh msg
25
+ * @width: multiplier used to convert Hz value to an RPMh msg
26
+ * @vcd: virtual clock domain that this bcm belongs to
27
+ * @reserved: reserved to pad the struct
28
+ */
29
+struct bcm_db {
30
+	__le32 unit;
31
+	__le16 width;
32
+	u8 vcd;
33
+	u8 reserved;
34
+};
2035 
2136 /**
2237  * struct clk_rpmh - individual rpmh clock data structure
....@@ -29,6 +44,7 @@
2944  * @aggr_state:		rpmh clock aggregated state
3045  * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
3146  * @valid_state_mask:	mask to determine the state of the rpmh clock
47
+ * @unit:		divisor to convert rate to rpmh msg in magnitudes of Khz
3248  * @dev:		device to which it is attached
3349  * @peer:		pointer to the clock rpmh sibling
3450  */
....@@ -42,6 +58,7 @@
4258 	u32 aggr_state;
4359 	u32 last_sent_aggr_state;
4460 	u32 valid_state_mask;
61
+	u32 unit;
4562 	struct device *dev;
4663 	struct clk_rpmh *peer;
4764 };
....@@ -68,7 +85,10 @@
6885 		.hw.init = &(struct clk_init_data){			\
6986 			.ops = &clk_rpmh_ops,				\
7087 			.name = #_name,					\
71
-			.parent_names = (const char *[]){ "xo_board" },	\
88
+			.parent_data =  &(const struct clk_parent_data){ \
89
+					.fw_name = "xo",		\
90
+					.name = "xo_board",		\
91
+			},						\
7292 			.num_parents = 1,				\
7393 		},							\
7494 	};								\
....@@ -83,7 +103,10 @@
83103 		.hw.init = &(struct clk_init_data){			\
84104 			.ops = &clk_rpmh_ops,				\
85105 			.name = #_name_active,				\
86
-			.parent_names = (const char *[]){ "xo_board" },	\
106
+			.parent_data =  &(const struct clk_parent_data){ \
107
+					.fw_name = "xo",		\
108
+					.name = "xo_board",		\
109
+			},						\
87110 			.num_parents = 1,				\
88111 		},							\
89112 	}
....@@ -98,6 +121,17 @@
98121 	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\
99122 			  CLK_RPMH_VRM_EN_OFFSET, 1, _div)
100123 
124
+#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name)		\
125
+	static struct clk_rpmh _platform##_##_name = {			\
126
+		.res_name = _res_name,					\
127
+		.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE),	\
128
+		.div = 1,						\
129
+		.hw.init = &(struct clk_init_data){			\
130
+			.ops = &clk_rpmh_bcm_ops,			\
131
+			.name = #_name,					\
132
+		},							\
133
+	}
134
+
101135 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
102136 {
103137 	return container_of(_hw, struct clk_rpmh, hw);
....@@ -109,12 +143,22 @@
109143 		!= (c->aggr_state & BIT(state));
110144 }
111145 
146
+static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
147
+			 struct tcs_cmd *cmd, bool wait)
148
+{
149
+	if (wait)
150
+		return rpmh_write(c->dev, state, cmd, 1);
151
+
152
+	return rpmh_write_async(c->dev, state, cmd, 1);
153
+}
154
+
112155 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
113156 {
114157 	struct tcs_cmd cmd = { 0 };
115158 	u32 cmd_state, on_val;
116159 	enum rpmh_state state = RPMH_SLEEP_STATE;
117160 	int ret;
161
+	bool wait;
118162 
119163 	cmd.addr = c->res_addr;
120164 	cmd_state = c->aggr_state;
....@@ -125,7 +169,8 @@
125169 			if (cmd_state & BIT(state))
126170 				cmd.data = on_val;
127171 
128
-			ret = rpmh_write_async(c->dev, state, &cmd, 1);
172
+			wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
173
+			ret = clk_rpmh_send(c, state, &cmd, wait);
129174 			if (ret) {
130175 				dev_err(c->dev, "set %s state of %s failed: (%d)\n",
131176 					!state ? "sleep" :
....@@ -182,7 +227,7 @@
182227 	mutex_unlock(&rpmh_clk_lock);
183228 
184229 	return ret;
185
-};
230
+}
186231 
187232 static void clk_rpmh_unprepare(struct clk_hw *hw)
188233 {
....@@ -210,13 +255,100 @@
210255 	.recalc_rate	= clk_rpmh_recalc_rate,
211256 };
212257 
213
-/* Resource name must match resource id present in cmd-db. */
258
+static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
259
+{
260
+	struct tcs_cmd cmd = { 0 };
261
+	u32 cmd_state;
262
+	int ret = 0;
263
+
264
+	mutex_lock(&rpmh_clk_lock);
265
+	if (enable) {
266
+		cmd_state = 1;
267
+		if (c->aggr_state)
268
+			cmd_state = c->aggr_state;
269
+	} else {
270
+		cmd_state = 0;
271
+	}
272
+
273
+	if (c->last_sent_aggr_state != cmd_state) {
274
+		cmd.addr = c->res_addr;
275
+		cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
276
+
277
+		ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
278
+		if (ret) {
279
+			dev_err(c->dev, "set active state of %s failed: (%d)\n",
280
+				c->res_name, ret);
281
+		} else {
282
+			c->last_sent_aggr_state = cmd_state;
283
+		}
284
+	}
285
+
286
+	mutex_unlock(&rpmh_clk_lock);
287
+
288
+	return ret;
289
+}
290
+
291
+static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
292
+{
293
+	struct clk_rpmh *c = to_clk_rpmh(hw);
294
+
295
+	return clk_rpmh_bcm_send_cmd(c, true);
296
+}
297
+
298
+static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
299
+{
300
+	struct clk_rpmh *c = to_clk_rpmh(hw);
301
+
302
+	clk_rpmh_bcm_send_cmd(c, false);
303
+}
304
+
305
+static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
306
+				 unsigned long parent_rate)
307
+{
308
+	struct clk_rpmh *c = to_clk_rpmh(hw);
309
+
310
+	c->aggr_state = rate / c->unit;
311
+	/*
312
+	 * Since any non-zero value sent to hw would result in enabling the
313
+	 * clock, only send the value if the clock has already been prepared.
314
+	 */
315
+	if (clk_hw_is_prepared(hw))
316
+		clk_rpmh_bcm_send_cmd(c, true);
317
+
318
+	return 0;
319
+}
320
+
321
+static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
322
+				unsigned long *parent_rate)
323
+{
324
+	return rate;
325
+}
326
+
327
+static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
328
+					unsigned long prate)
329
+{
330
+	struct clk_rpmh *c = to_clk_rpmh(hw);
331
+
332
+	return c->aggr_state * c->unit;
333
+}
334
+
335
+static const struct clk_ops clk_rpmh_bcm_ops = {
336
+	.prepare	= clk_rpmh_bcm_prepare,
337
+	.unprepare	= clk_rpmh_bcm_unprepare,
338
+	.set_rate	= clk_rpmh_bcm_set_rate,
339
+	.round_rate	= clk_rpmh_round_rate,
340
+	.recalc_rate	= clk_rpmh_bcm_recalc_rate,
341
+};
342
+
343
+/* Resource name must match resource id present in cmd-db */
214344 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
215345 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
216346 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
217347 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
218348 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
219349 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
350
+DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
351
+DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
220352 
221353 static struct clk_hw *sdm845_rpmh_clocks[] = {
222354 	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
....@@ -231,11 +363,73 @@
231363 	[RPMH_RF_CLK2_A]	= &sdm845_rf_clk2_ao.hw,
232364 	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
233365 	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
366
+	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,
234367 };
235368 
236369 static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
237370 	.clks = sdm845_rpmh_clocks,
238371 	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
372
+};
373
+
374
+static struct clk_hw *sm8150_rpmh_clocks[] = {
375
+	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
376
+	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
377
+	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
378
+	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
379
+	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,
380
+	[RPMH_LN_BB_CLK3_A]	= &sdm845_ln_bb_clk3_ao.hw,
381
+	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
382
+	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
383
+	[RPMH_RF_CLK2]		= &sdm845_rf_clk2.hw,
384
+	[RPMH_RF_CLK2_A]	= &sdm845_rf_clk2_ao.hw,
385
+	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
386
+	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
387
+};
388
+
389
+static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
390
+	.clks = sm8150_rpmh_clocks,
391
+	.num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
392
+};
393
+
394
+static struct clk_hw *sc7180_rpmh_clocks[] = {
395
+	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
396
+	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
397
+	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
398
+	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
399
+	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,
400
+	[RPMH_LN_BB_CLK3_A]	= &sdm845_ln_bb_clk3_ao.hw,
401
+	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
402
+	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
403
+	[RPMH_RF_CLK2]		= &sdm845_rf_clk2.hw,
404
+	[RPMH_RF_CLK2_A]	= &sdm845_rf_clk2_ao.hw,
405
+	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,
406
+};
407
+
408
+static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
409
+	.clks = sc7180_rpmh_clocks,
410
+	.num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
411
+};
412
+
413
+DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
414
+
415
+static struct clk_hw *sm8250_rpmh_clocks[] = {
416
+	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
417
+	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
418
+	[RPMH_LN_BB_CLK1]	= &sm8250_ln_bb_clk1.hw,
419
+	[RPMH_LN_BB_CLK1_A]	= &sm8250_ln_bb_clk1_ao.hw,
420
+	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
421
+	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
422
+	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,
423
+	[RPMH_LN_BB_CLK3_A]	= &sdm845_ln_bb_clk3_ao.hw,
424
+	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
425
+	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
426
+	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
427
+	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
428
+};
429
+
430
+static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
431
+	.clks = sm8250_rpmh_clocks,
432
+	.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
239433 };
240434 
241435 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
....@@ -266,7 +460,15 @@
266460 	hw_clks = desc->clks;
267461 
268462 	for (i = 0; i < desc->num_clks; i++) {
463
+		const char *name;
269464 		u32 res_addr;
465
+		size_t aux_data_len;
466
+		const struct bcm_db *data;
467
+
468
+		if (!hw_clks[i])
469
+			continue;
470
+
471
+		name = hw_clks[i]->init->name;
270472 
271473 		rpmh_clk = to_clk_rpmh(hw_clks[i]);
272474 		res_addr = cmd_db_read_addr(rpmh_clk->res_name);
....@@ -275,13 +477,26 @@
275477 				rpmh_clk->res_name);
276478 			return -ENODEV;
277479 		}
480
+
481
+		data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
482
+		if (IS_ERR(data)) {
483
+			ret = PTR_ERR(data);
484
+			dev_err(&pdev->dev,
485
+				"error reading RPMh aux data for %s (%d)\n",
486
+				rpmh_clk->res_name, ret);
487
+			return ret;
488
+		}
489
+
490
+		/* Convert unit from Khz to Hz */
491
+		if (aux_data_len == sizeof(*data))
492
+			rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
493
+
278494 		rpmh_clk->res_addr += res_addr;
279495 		rpmh_clk->dev = &pdev->dev;
280496 
281497 		ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
282498 		if (ret) {
283
-			dev_err(&pdev->dev, "failed to register %s\n",
284
-				hw_clks[i]->init->name);
499
+			dev_err(&pdev->dev, "failed to register %s\n", name);
285500 			return ret;
286501 		}
287502 	}
....@@ -300,7 +515,10 @@
300515 }
301516 
302517 static const struct of_device_id clk_rpmh_match_table[] = {
518
+	{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
303519 	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
520
+	{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
521
+	{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
304522 	{ }
305523 };
306524 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
....@@ -317,7 +535,7 @@
317535 {
318536 	return platform_driver_register(&clk_rpmh_driver);
319537 }
320
-subsys_initcall(clk_rpmh_init);
538
+core_initcall(clk_rpmh_init);
321539 
322540 static void __exit clk_rpmh_exit(void)
323541 {