add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/clk/qcom/clk-rcg.h
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@@ -71,7 +71,6 @@
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  * @freq_tbl: frequency table
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  * @clkr: regmap clock handle
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  * @lock: register lock
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- *
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  */
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 struct clk_rcg {
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 	u32		ns_reg;
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@@ -107,7 +106,6 @@
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  * @freq_tbl: frequency table
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  * @clkr: regmap clock handle
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  * @lock: register lock
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- *
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  */
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 struct clk_dyn_rcg {
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 	u32	ns_reg[2];
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@@ -140,7 +138,7 @@
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  * @parent_map: map from software's parent index to hardware's src_sel field
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  * @freq_tbl: frequency table
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  * @clkr: regmap clock handle
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- *
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+ * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
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  */
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 struct clk_rcg2 {
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 	u32			cmd_rcgr;
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@@ -150,6 +148,7 @@
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 	const struct parent_map	*parent_map;
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 	const struct freq_tbl	*freq_tbl;
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 	struct clk_regmap	clkr;
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+	u8			cfg_off;
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 };
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 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
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@@ -162,5 +161,17 @@
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 extern const struct clk_ops clk_pixel_ops;
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 extern const struct clk_ops clk_gfx3d_ops;
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 extern const struct clk_ops clk_rcg2_shared_ops;
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+extern const struct clk_ops clk_dp_ops;
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+struct clk_rcg_dfs_data {
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+	struct clk_rcg2 *rcg;
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+	struct clk_init_data *init;
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+};
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+
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+#define DEFINE_RCG_DFS(r) \
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+	{ .rcg = &r, .init = &r##_init }
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+
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+extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
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+				    const struct clk_rcg_dfs_data *rcgs,
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+				    size_t len);
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 #endif