~hc/RK356X_SDK_RELEASE.git

..	..	@@ -10,78 +10,45 @@
10	10	#include <linux/clk.h>
11	11	#include <linux/clk-provider.h>
12	12	#include <linux/init.h>
	13	+#include <linux/mfd/syscon.h>
13	14	#include <linux/of_address.h>
14		-#include <linux/platform_device.h>
15	15	#include <linux/reset-controller.h>
16	16	#include <linux/slab.h>
17	17	#include <linux/regmap.h>
18	18
19		-#include "clkc.h"
20	19	#include "meson8b.h"
21	20	#include "clk-regmap.h"
	21	+#include "clk-pll.h"
	22	+#include "clk-mpll.h"
22	23
23	24	static DEFINE_SPINLOCK(meson_clk_lock);
24	25
25		-static void __iomem *clk_base;
26		-
27	26	struct meson8b_clk_reset {
28	27	struct reset_controller_dev reset;
29		- void __iomem *base;
	28	+ struct regmap *regmap;
30	29	};
31	30
32		-static const struct pll_rate_table sys_pll_rate_table[] = {
33		- PLL_RATE(312000000, 52, 1, 2),
34		- PLL_RATE(336000000, 56, 1, 2),
35		- PLL_RATE(360000000, 60, 1, 2),
36		- PLL_RATE(384000000, 64, 1, 2),
37		- PLL_RATE(408000000, 68, 1, 2),
38		- PLL_RATE(432000000, 72, 1, 2),
39		- PLL_RATE(456000000, 76, 1, 2),
40		- PLL_RATE(480000000, 80, 1, 2),
41		- PLL_RATE(504000000, 84, 1, 2),
42		- PLL_RATE(528000000, 88, 1, 2),
43		- PLL_RATE(552000000, 92, 1, 2),
44		- PLL_RATE(576000000, 96, 1, 2),
45		- PLL_RATE(600000000, 50, 1, 1),
46		- PLL_RATE(624000000, 52, 1, 1),
47		- PLL_RATE(648000000, 54, 1, 1),
48		- PLL_RATE(672000000, 56, 1, 1),
49		- PLL_RATE(696000000, 58, 1, 1),
50		- PLL_RATE(720000000, 60, 1, 1),
51		- PLL_RATE(744000000, 62, 1, 1),
52		- PLL_RATE(768000000, 64, 1, 1),
53		- PLL_RATE(792000000, 66, 1, 1),
54		- PLL_RATE(816000000, 68, 1, 1),
55		- PLL_RATE(840000000, 70, 1, 1),
56		- PLL_RATE(864000000, 72, 1, 1),
57		- PLL_RATE(888000000, 74, 1, 1),
58		- PLL_RATE(912000000, 76, 1, 1),
59		- PLL_RATE(936000000, 78, 1, 1),
60		- PLL_RATE(960000000, 80, 1, 1),
61		- PLL_RATE(984000000, 82, 1, 1),
62		- PLL_RATE(1008000000, 84, 1, 1),
63		- PLL_RATE(1032000000, 86, 1, 1),
64		- PLL_RATE(1056000000, 88, 1, 1),
65		- PLL_RATE(1080000000, 90, 1, 1),
66		- PLL_RATE(1104000000, 92, 1, 1),
67		- PLL_RATE(1128000000, 94, 1, 1),
68		- PLL_RATE(1152000000, 96, 1, 1),
69		- PLL_RATE(1176000000, 98, 1, 1),
70		- PLL_RATE(1200000000, 50, 1, 0),
71		- PLL_RATE(1224000000, 51, 1, 0),
72		- PLL_RATE(1248000000, 52, 1, 0),
73		- PLL_RATE(1272000000, 53, 1, 0),
74		- PLL_RATE(1296000000, 54, 1, 0),
75		- PLL_RATE(1320000000, 55, 1, 0),
76		- PLL_RATE(1344000000, 56, 1, 0),
77		- PLL_RATE(1368000000, 57, 1, 0),
78		- PLL_RATE(1392000000, 58, 1, 0),
79		- PLL_RATE(1416000000, 59, 1, 0),
80		- PLL_RATE(1440000000, 60, 1, 0),
81		- PLL_RATE(1464000000, 61, 1, 0),
82		- PLL_RATE(1488000000, 62, 1, 0),
83		- PLL_RATE(1512000000, 63, 1, 0),
84		- PLL_RATE(1536000000, 64, 1, 0),
	31	+static const struct pll_params_table sys_pll_params_table[] = {
	32	+ PLL_PARAMS(50, 1),
	33	+ PLL_PARAMS(51, 1),
	34	+ PLL_PARAMS(52, 1),
	35	+ PLL_PARAMS(53, 1),
	36	+ PLL_PARAMS(54, 1),
	37	+ PLL_PARAMS(55, 1),
	38	+ PLL_PARAMS(56, 1),
	39	+ PLL_PARAMS(57, 1),
	40	+ PLL_PARAMS(58, 1),
	41	+ PLL_PARAMS(59, 1),
	42	+ PLL_PARAMS(60, 1),
	43	+ PLL_PARAMS(61, 1),
	44	+ PLL_PARAMS(62, 1),
	45	+ PLL_PARAMS(63, 1),
	46	+ PLL_PARAMS(64, 1),
	47	+ PLL_PARAMS(65, 1),
	48	+ PLL_PARAMS(66, 1),
	49	+ PLL_PARAMS(67, 1),
	50	+ PLL_PARAMS(68, 1),
	51	+ PLL_PARAMS(84, 1),
85	52	{ /* sentinel */ },
86	53	};
87	54
..	..	@@ -94,8 +61,13 @@
94	61	},
95	62	};
96	63
97		-static struct clk_regmap meson8b_fixed_pll = {
	64	+static struct clk_regmap meson8b_fixed_pll_dco = {
98	65	.data = &(struct meson_clk_pll_data){
	66	+ .en = {
	67	+ .reg_off = HHI_MPLL_CNTL,
	68	+ .shift = 30,
	69	+ .width = 1,
	70	+ },
99	71	.m = {
100	72	.reg_off = HHI_MPLL_CNTL,
101	73	.shift = 0,
..	..	@@ -105,11 +77,6 @@
105	77	.reg_off = HHI_MPLL_CNTL,
106	78	.shift = 9,
107	79	.width = 5,
108		- },
109		- .od = {
110		- .reg_off = HHI_MPLL_CNTL,
111		- .shift = 16,
112		- .width = 2,
113	80	},
114	81	.frac = {
115	82	.reg_off = HHI_MPLL_CNTL2,
..	..	@@ -128,15 +95,45 @@
128	95	},
129	96	},
130	97	.hw.init = &(struct clk_init_data){
131		- .name = "fixed_pll",
	98	+ .name = "fixed_pll_dco",
132	99	.ops = &meson_clk_pll_ro_ops,
133		- .parent_names = (const char *[]){ "xtal" },
	100	+ .parent_data = &(const struct clk_parent_data) {
	101	+ .fw_name = "xtal",
	102	+ .name = "xtal",
	103	+ .index = -1,
	104	+ },
134	105	.num_parents = 1,
135	106	},
136	107	};
137	108
138		-static struct clk_regmap meson8b_vid_pll = {
	109	+static struct clk_regmap meson8b_fixed_pll = {
	110	+ .data = &(struct clk_regmap_div_data){
	111	+ .offset = HHI_MPLL_CNTL,
	112	+ .shift = 16,
	113	+ .width = 2,
	114	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	115	+ },
	116	+ .hw.init = &(struct clk_init_data){
	117	+ .name = "fixed_pll",
	118	+ .ops = &clk_regmap_divider_ro_ops,
	119	+ .parent_hws = (const struct clk_hw *[]) {
	120	+ &meson8b_fixed_pll_dco.hw
	121	+ },
	122	+ .num_parents = 1,
	123	+ /*
	124	+ * This clock won't ever change at runtime so
	125	+ * CLK_SET_RATE_PARENT is not required
	126	+ */
	127	+ },
	128	+};
	129	+
	130	+static struct clk_regmap meson8b_hdmi_pll_dco = {
139	131	.data = &(struct meson_clk_pll_data){
	132	+ .en = {
	133	+ .reg_off = HHI_VID_PLL_CNTL,
	134	+ .shift = 30,
	135	+ .width = 1,
	136	+ },
140	137	.m = {
141	138	.reg_off = HHI_VID_PLL_CNTL,
142	139	.shift = 0,
..	..	@@ -147,10 +144,10 @@
147	144	.shift = 10,
148	145	.width = 5,
149	146	},
150		- .od = {
151		- .reg_off = HHI_VID_PLL_CNTL,
152		- .shift = 16,
153		- .width = 2,
	147	+ .frac = {
	148	+ .reg_off = HHI_VID_PLL_CNTL2,
	149	+ .shift = 0,
	150	+ .width = 12,
154	151	},
155	152	.l = {
156	153	.reg_off = HHI_VID_PLL_CNTL,
..	..	@@ -164,15 +161,61 @@
164	161	},
165	162	},
166	163	.hw.init = &(struct clk_init_data){
167		- .name = "vid_pll",
	164	+ /* sometimes also called "HPLL" or "HPLL PLL" */
	165	+ .name = "hdmi_pll_dco",
168	166	.ops = &meson_clk_pll_ro_ops,
169		- .parent_names = (const char *[]){ "xtal" },
	167	+ .parent_data = &(const struct clk_parent_data) {
	168	+ .fw_name = "xtal",
	169	+ .name = "xtal",
	170	+ .index = -1,
	171	+ },
170	172	.num_parents = 1,
171	173	},
172	174	};
173	175
174		-static struct clk_regmap meson8b_sys_pll = {
	176	+static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
	177	+ .data = &(struct clk_regmap_div_data){
	178	+ .offset = HHI_VID_PLL_CNTL,
	179	+ .shift = 16,
	180	+ .width = 2,
	181	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	182	+ },
	183	+ .hw.init = &(struct clk_init_data){
	184	+ .name = "hdmi_pll_lvds_out",
	185	+ .ops = &clk_regmap_divider_ro_ops,
	186	+ .parent_hws = (const struct clk_hw *[]) {
	187	+ &meson8b_hdmi_pll_dco.hw
	188	+ },
	189	+ .num_parents = 1,
	190	+ .flags = CLK_SET_RATE_PARENT,
	191	+ },
	192	+};
	193	+
	194	+static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
	195	+ .data = &(struct clk_regmap_div_data){
	196	+ .offset = HHI_VID_PLL_CNTL,
	197	+ .shift = 18,
	198	+ .width = 2,
	199	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	200	+ },
	201	+ .hw.init = &(struct clk_init_data){
	202	+ .name = "hdmi_pll_hdmi_out",
	203	+ .ops = &clk_regmap_divider_ro_ops,
	204	+ .parent_hws = (const struct clk_hw *[]) {
	205	+ &meson8b_hdmi_pll_dco.hw
	206	+ },
	207	+ .num_parents = 1,
	208	+ .flags = CLK_SET_RATE_PARENT,
	209	+ },
	210	+};
	211	+
	212	+static struct clk_regmap meson8b_sys_pll_dco = {
175	213	.data = &(struct meson_clk_pll_data){
	214	+ .en = {
	215	+ .reg_off = HHI_SYS_PLL_CNTL,
	216	+ .shift = 30,
	217	+ .width = 1,
	218	+ },
176	219	.m = {
177	220	.reg_off = HHI_SYS_PLL_CNTL,
178	221	.shift = 0,
..	..	@@ -183,11 +226,6 @@
183	226	.shift = 9,
184	227	.width = 5,
185	228	},
186		- .od = {
187		- .reg_off = HHI_SYS_PLL_CNTL,
188		- .shift = 16,
189		- .width = 2,
190		- },
191	229	.l = {
192	230	.reg_off = HHI_SYS_PLL_CNTL,
193	231	.shift = 31,
..	..	@@ -198,13 +236,35 @@
198	236	.shift = 29,
199	237	.width = 1,
200	238	},
201		- .table = sys_pll_rate_table,
	239	+ .table = sys_pll_params_table,
	240	+ },
	241	+ .hw.init = &(struct clk_init_data){
	242	+ .name = "sys_pll_dco",
	243	+ .ops = &meson_clk_pll_ops,
	244	+ .parent_data = &(const struct clk_parent_data) {
	245	+ .fw_name = "xtal",
	246	+ .name = "xtal",
	247	+ .index = -1,
	248	+ },
	249	+ .num_parents = 1,
	250	+ },
	251	+};
	252	+
	253	+static struct clk_regmap meson8b_sys_pll = {
	254	+ .data = &(struct clk_regmap_div_data){
	255	+ .offset = HHI_SYS_PLL_CNTL,
	256	+ .shift = 16,
	257	+ .width = 2,
	258	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
202	259	},
203	260	.hw.init = &(struct clk_init_data){
204	261	.name = "sys_pll",
205		- .ops = &meson_clk_pll_ro_ops,
206		- .parent_names = (const char *[]){ "xtal" },
	262	+ .ops = &clk_regmap_divider_ops,
	263	+ .parent_hws = (const struct clk_hw *[]) {
	264	+ &meson8b_sys_pll_dco.hw
	265	+ },
207	266	.num_parents = 1,
	267	+ .flags = CLK_SET_RATE_PARENT,
208	268	},
209	269	};
210	270
..	..	@@ -214,7 +274,9 @@
214	274	.hw.init = &(struct clk_init_data){
215	275	.name = "fclk_div2_div",
216	276	.ops = &clk_fixed_factor_ops,
217		- .parent_names = (const char *[]){ "fixed_pll" },
	277	+ .parent_hws = (const struct clk_hw *[]) {
	278	+ &meson8b_fixed_pll.hw
	279	+ },
218	280	.num_parents = 1,
219	281	},
220	282	};
..	..	@@ -227,15 +289,10 @@
227	289	.hw.init = &(struct clk_init_data){
228	290	.name = "fclk_div2",
229	291	.ops = &clk_regmap_gate_ops,
230		- .parent_names = (const char *[]){ "fclk_div2_div" },
	292	+ .parent_hws = (const struct clk_hw *[]) {
	293	+ &meson8b_fclk_div2_div.hw
	294	+ },
231	295	.num_parents = 1,
232		- /*
233		- * FIXME: Ethernet with a RGMII PHYs is not working if
234		- * fclk_div2 is disabled. it is currently unclear why this
235		- * is. keep it enabled until the Ethernet driver knows how
236		- * to manage this clock.
237		- */
238		- .flags = CLK_IS_CRITICAL,
239	296	},
240	297	};
241	298
..	..	@@ -245,7 +302,9 @@
245	302	.hw.init = &(struct clk_init_data){
246	303	.name = "fclk_div3_div",
247	304	.ops = &clk_fixed_factor_ops,
248		- .parent_names = (const char *[]){ "fixed_pll" },
	305	+ .parent_hws = (const struct clk_hw *[]) {
	306	+ &meson8b_fixed_pll.hw
	307	+ },
249	308	.num_parents = 1,
250	309	},
251	310	};
..	..	@@ -258,7 +317,9 @@
258	317	.hw.init = &(struct clk_init_data){
259	318	.name = "fclk_div3",
260	319	.ops = &clk_regmap_gate_ops,
261		- .parent_names = (const char *[]){ "fclk_div3_div" },
	320	+ .parent_hws = (const struct clk_hw *[]) {
	321	+ &meson8b_fclk_div3_div.hw
	322	+ },
262	323	.num_parents = 1,
263	324	},
264	325	};
..	..	@@ -269,7 +330,9 @@
269	330	.hw.init = &(struct clk_init_data){
270	331	.name = "fclk_div4_div",
271	332	.ops = &clk_fixed_factor_ops,
272		- .parent_names = (const char *[]){ "fixed_pll" },
	333	+ .parent_hws = (const struct clk_hw *[]) {
	334	+ &meson8b_fixed_pll.hw
	335	+ },
273	336	.num_parents = 1,
274	337	},
275	338	};
..	..	@@ -282,7 +345,9 @@
282	345	.hw.init = &(struct clk_init_data){
283	346	.name = "fclk_div4",
284	347	.ops = &clk_regmap_gate_ops,
285		- .parent_names = (const char *[]){ "fclk_div4_div" },
	348	+ .parent_hws = (const struct clk_hw *[]) {
	349	+ &meson8b_fclk_div4_div.hw
	350	+ },
286	351	.num_parents = 1,
287	352	},
288	353	};
..	..	@@ -293,7 +358,9 @@
293	358	.hw.init = &(struct clk_init_data){
294	359	.name = "fclk_div5_div",
295	360	.ops = &clk_fixed_factor_ops,
296		- .parent_names = (const char *[]){ "fixed_pll" },
	361	+ .parent_hws = (const struct clk_hw *[]) {
	362	+ &meson8b_fixed_pll.hw
	363	+ },
297	364	.num_parents = 1,
298	365	},
299	366	};
..	..	@@ -306,7 +373,9 @@
306	373	.hw.init = &(struct clk_init_data){
307	374	.name = "fclk_div5",
308	375	.ops = &clk_regmap_gate_ops,
309		- .parent_names = (const char *[]){ "fclk_div5_div" },
	376	+ .parent_hws = (const struct clk_hw *[]) {
	377	+ &meson8b_fclk_div5_div.hw
	378	+ },
310	379	.num_parents = 1,
311	380	},
312	381	};
..	..	@@ -317,7 +386,9 @@
317	386	.hw.init = &(struct clk_init_data){
318	387	.name = "fclk_div7_div",
319	388	.ops = &clk_fixed_factor_ops,
320		- .parent_names = (const char *[]){ "fixed_pll" },
	389	+ .parent_hws = (const struct clk_hw *[]) {
	390	+ &meson8b_fixed_pll.hw
	391	+ },
321	392	.num_parents = 1,
322	393	},
323	394	};
..	..	@@ -330,7 +401,9 @@
330	401	.hw.init = &(struct clk_init_data){
331	402	.name = "fclk_div7",
332	403	.ops = &clk_regmap_gate_ops,
333		- .parent_names = (const char *[]){ "fclk_div7_div" },
	404	+ .parent_hws = (const struct clk_hw *[]) {
	405	+ &meson8b_fclk_div7_div.hw
	406	+ },
334	407	.num_parents = 1,
335	408	},
336	409	};
..	..	@@ -344,7 +417,9 @@
344	417	.hw.init = &(struct clk_init_data){
345	418	.name = "mpll_prediv",
346	419	.ops = &clk_regmap_divider_ro_ops,
347		- .parent_names = (const char *[]){ "fixed_pll" },
	420	+ .parent_hws = (const struct clk_hw *[]) {
	421	+ &meson8b_fixed_pll.hw
	422	+ },
348	423	.num_parents = 1,
349	424	},
350	425	};
..	..	@@ -376,7 +451,9 @@
376	451	.hw.init = &(struct clk_init_data){
377	452	.name = "mpll0_div",
378	453	.ops = &meson_clk_mpll_ops,
379		- .parent_names = (const char *[]){ "mpll_prediv" },
	454	+ .parent_hws = (const struct clk_hw *[]) {
	455	+ &meson8b_mpll_prediv.hw
	456	+ },
380	457	.num_parents = 1,
381	458	},
382	459	};
..	..	@@ -389,7 +466,9 @@
389	466	.hw.init = &(struct clk_init_data){
390	467	.name = "mpll0",
391	468	.ops = &clk_regmap_gate_ops,
392		- .parent_names = (const char *[]){ "mpll0_div" },
	469	+ .parent_hws = (const struct clk_hw *[]) {
	470	+ &meson8b_mpll0_div.hw
	471	+ },
393	472	.num_parents = 1,
394	473	.flags = CLK_SET_RATE_PARENT,
395	474	},
..	..	@@ -417,7 +496,9 @@
417	496	.hw.init = &(struct clk_init_data){
418	497	.name = "mpll1_div",
419	498	.ops = &meson_clk_mpll_ops,
420		- .parent_names = (const char *[]){ "mpll_prediv" },
	499	+ .parent_hws = (const struct clk_hw *[]) {
	500	+ &meson8b_mpll_prediv.hw
	501	+ },
421	502	.num_parents = 1,
422	503	},
423	504	};
..	..	@@ -430,7 +511,9 @@
430	511	.hw.init = &(struct clk_init_data){
431	512	.name = "mpll1",
432	513	.ops = &clk_regmap_gate_ops,
433		- .parent_names = (const char *[]){ "mpll1_div" },
	514	+ .parent_hws = (const struct clk_hw *[]) {
	515	+ &meson8b_mpll1_div.hw
	516	+ },
434	517	.num_parents = 1,
435	518	.flags = CLK_SET_RATE_PARENT,
436	519	},
..	..	@@ -458,7 +541,9 @@
458	541	.hw.init = &(struct clk_init_data){
459	542	.name = "mpll2_div",
460	543	.ops = &meson_clk_mpll_ops,
461		- .parent_names = (const char *[]){ "mpll_prediv" },
	544	+ .parent_hws = (const struct clk_hw *[]) {
	545	+ &meson8b_mpll_prediv.hw
	546	+ },
462	547	.num_parents = 1,
463	548	},
464	549	};
..	..	@@ -471,7 +556,9 @@
471	556	.hw.init = &(struct clk_init_data){
472	557	.name = "mpll2",
473	558	.ops = &clk_regmap_gate_ops,
474		- .parent_names = (const char *[]){ "mpll2_div" },
	559	+ .parent_hws = (const struct clk_hw *[]) {
	560	+ &meson8b_mpll2_div.hw
	561	+ },
475	562	.num_parents = 1,
476	563	.flags = CLK_SET_RATE_PARENT,
477	564	},
..	..	@@ -493,8 +580,11 @@
493	580	* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
494	581	* fclk_div4, fclk_div3, fclk_div5
495	582	*/
496		- .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
497		- "fclk_div5" },
	583	+ .parent_hws = (const struct clk_hw *[]) {
	584	+ &meson8b_fclk_div3.hw,
	585	+ &meson8b_fclk_div4.hw,
	586	+ &meson8b_fclk_div5.hw,
	587	+ },
498	588	.num_parents = 3,
499	589	},
500	590	};
..	..	@@ -508,7 +598,9 @@
508	598	.hw.init = &(struct clk_init_data){
509	599	.name = "mpeg_clk_div",
510	600	.ops = &clk_regmap_divider_ro_ops,
511		- .parent_names = (const char *[]){ "mpeg_clk_sel" },
	601	+ .parent_hws = (const struct clk_hw *[]) {
	602	+ &meson8b_mpeg_clk_sel.hw
	603	+ },
512	604	.num_parents = 1,
513	605	},
514	606	};
..	..	@@ -521,7 +613,9 @@
521	613	.hw.init = &(struct clk_init_data){
522	614	.name = "clk81",
523	615	.ops = &clk_regmap_gate_ops,
524		- .parent_names = (const char *[]){ "mpeg_clk_div" },
	616	+ .parent_hws = (const struct clk_hw *[]) {
	617	+ &meson8b_mpeg_clk_div.hw
	618	+ },
525	619	.num_parents = 1,
526	620	.flags = CLK_IS_CRITICAL,
527	621	},
..	..	@@ -535,33 +629,40 @@
535	629	},
536	630	.hw.init = &(struct clk_init_data){
537	631	.name = "cpu_in_sel",
538		- .ops = &clk_regmap_mux_ro_ops,
539		- .parent_names = (const char *[]){ "xtal", "sys_pll" },
	632	+ .ops = &clk_regmap_mux_ops,
	633	+ .parent_data = (const struct clk_parent_data[]) {
	634	+ { .fw_name = "xtal", .name = "xtal", .index = -1, },
	635	+ { .hw = &meson8b_sys_pll.hw, },
	636	+ },
540	637	.num_parents = 2,
541	638	.flags = (CLK_SET_RATE_PARENT \|
542	639	CLK_SET_RATE_NO_REPARENT),
543	640	},
544	641	};
545	642
546		-static struct clk_fixed_factor meson8b_cpu_div2 = {
	643	+static struct clk_fixed_factor meson8b_cpu_in_div2 = {
547	644	.mult = 1,
548	645	.div = 2,
549	646	.hw.init = &(struct clk_init_data){
550		- .name = "cpu_div2",
	647	+ .name = "cpu_in_div2",
551	648	.ops = &clk_fixed_factor_ops,
552		- .parent_names = (const char *[]){ "cpu_in_sel" },
	649	+ .parent_hws = (const struct clk_hw *[]) {
	650	+ &meson8b_cpu_in_sel.hw
	651	+ },
553	652	.num_parents = 1,
554	653	.flags = CLK_SET_RATE_PARENT,
555	654	},
556	655	};
557	656
558		-static struct clk_fixed_factor meson8b_cpu_div3 = {
	657	+static struct clk_fixed_factor meson8b_cpu_in_div3 = {
559	658	.mult = 1,
560	659	.div = 3,
561	660	.hw.init = &(struct clk_init_data){
562		- .name = "cpu_div3",
	661	+ .name = "cpu_in_div3",
563	662	.ops = &clk_fixed_factor_ops,
564		- .parent_names = (const char *[]){ "cpu_in_sel" },
	663	+ .parent_hws = (const struct clk_hw *[]) {
	664	+ &meson8b_cpu_in_sel.hw
	665	+ },
565	666	.num_parents = 1,
566	667	.flags = CLK_SET_RATE_PARENT,
567	668	},
..	..	@@ -589,8 +690,10 @@
589	690	},
590	691	.hw.init = &(struct clk_init_data){
591	692	.name = "cpu_scale_div",
592		- .ops = &clk_regmap_divider_ro_ops,
593		- .parent_names = (const char *[]){ "cpu_in_sel" },
	693	+ .ops = &clk_regmap_divider_ops,
	694	+ .parent_hws = (const struct clk_hw *[]) {
	695	+ &meson8b_cpu_in_sel.hw
	696	+ },
594	697	.num_parents = 1,
595	698	.flags = CLK_SET_RATE_PARENT,
596	699	},
..	..	@@ -606,16 +709,18 @@
606	709	},
607	710	.hw.init = &(struct clk_init_data){
608	711	.name = "cpu_scale_out_sel",
609		- .ops = &clk_regmap_mux_ro_ops,
	712	+ .ops = &clk_regmap_mux_ops,
610	713	/*
611	714	* NOTE: We are skipping the parent with value 0x2 (which is
612		- * "cpu_div3") because it results in a duty cycle of 33% which
613		- * makes the system unstable and can result in a lockup of the
614		- * whole system.
	715	+ * meson8b_cpu_in_div3) because it results in a duty cycle of
	716	+ * 33% which makes the system unstable and can result in a
	717	+ * lockup of the whole system.
615	718	*/
616		- .parent_names = (const char *[]) { "cpu_in_sel",
617		- "cpu_div2",
618		- "cpu_scale_div" },
	719	+ .parent_hws = (const struct clk_hw *[]) {
	720	+ &meson8b_cpu_in_sel.hw,
	721	+ &meson8b_cpu_in_div2.hw,
	722	+ &meson8b_cpu_scale_div.hw,
	723	+ },
619	724	.num_parents = 3,
620	725	.flags = CLK_SET_RATE_PARENT,
621	726	},
..	..	@@ -629,9 +734,11 @@
629	734	},
630	735	.hw.init = &(struct clk_init_data){
631	736	.name = "cpu_clk",
632		- .ops = &clk_regmap_mux_ro_ops,
633		- .parent_names = (const char *[]){ "xtal",
634		- "cpu_scale_out_sel" },
	737	+ .ops = &clk_regmap_mux_ops,
	738	+ .parent_data = (const struct clk_parent_data[]) {
	739	+ { .fw_name = "xtal", .name = "xtal", .index = -1, },
	740	+ { .hw = &meson8b_cpu_scale_out_sel.hw, },
	741	+ },
635	742	.num_parents = 2,
636	743	.flags = (CLK_SET_RATE_PARENT \|
637	744	CLK_SET_RATE_NO_REPARENT \|
..	..	@@ -650,8 +757,13 @@
650	757	.name = "nand_clk_sel",
651	758	.ops = &clk_regmap_mux_ops,
652	759	/* FIXME all other parents are unknown: */
653		- .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
654		- "fclk_div5", "fclk_div7", "xtal" },
	760	+ .parent_data = (const struct clk_parent_data[]) {
	761	+ { .hw = &meson8b_fclk_div4.hw, },
	762	+ { .hw = &meson8b_fclk_div3.hw, },
	763	+ { .hw = &meson8b_fclk_div5.hw, },
	764	+ { .hw = &meson8b_fclk_div7.hw, },
	765	+ { .fw_name = "xtal", .name = "xtal", .index = -1, },
	766	+ },
655	767	.num_parents = 5,
656	768	.flags = CLK_SET_RATE_PARENT,
657	769	},
..	..	@@ -667,7 +779,9 @@
667	779	.hw.init = &(struct clk_init_data){
668	780	.name = "nand_clk_div",
669	781	.ops = &clk_regmap_divider_ops,
670		- .parent_names = (const char *[]){ "nand_clk_sel" },
	782	+ .parent_hws = (const struct clk_hw *[]) {
	783	+ &meson8b_nand_clk_sel.hw
	784	+ },
671	785	.num_parents = 1,
672	786	.flags = CLK_SET_RATE_PARENT,
673	787	},
..	..	@@ -681,11 +795,1832 @@
681	795	.hw.init = &(struct clk_init_data){
682	796	.name = "nand_clk_gate",
683	797	.ops = &clk_regmap_gate_ops,
684		- .parent_names = (const char *[]){ "nand_clk_div" },
	798	+ .parent_hws = (const struct clk_hw *[]) {
	799	+ &meson8b_nand_clk_div.hw
	800	+ },
685	801	.num_parents = 1,
686	802	.flags = CLK_SET_RATE_PARENT,
687	803	},
688	804	};
	805	+
	806	+static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
	807	+ .mult = 1,
	808	+ .div = 2,
	809	+ .hw.init = &(struct clk_init_data){
	810	+ .name = "cpu_clk_div2",
	811	+ .ops = &clk_fixed_factor_ops,
	812	+ .parent_hws = (const struct clk_hw *[]) {
	813	+ &meson8b_cpu_clk.hw
	814	+ },
	815	+ .num_parents = 1,
	816	+ },
	817	+};
	818	+
	819	+static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
	820	+ .mult = 1,
	821	+ .div = 3,
	822	+ .hw.init = &(struct clk_init_data){
	823	+ .name = "cpu_clk_div3",
	824	+ .ops = &clk_fixed_factor_ops,
	825	+ .parent_hws = (const struct clk_hw *[]) {
	826	+ &meson8b_cpu_clk.hw
	827	+ },
	828	+ .num_parents = 1,
	829	+ },
	830	+};
	831	+
	832	+static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
	833	+ .mult = 1,
	834	+ .div = 4,
	835	+ .hw.init = &(struct clk_init_data){
	836	+ .name = "cpu_clk_div4",
	837	+ .ops = &clk_fixed_factor_ops,
	838	+ .parent_hws = (const struct clk_hw *[]) {
	839	+ &meson8b_cpu_clk.hw
	840	+ },
	841	+ .num_parents = 1,
	842	+ },
	843	+};
	844	+
	845	+static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
	846	+ .mult = 1,
	847	+ .div = 5,
	848	+ .hw.init = &(struct clk_init_data){
	849	+ .name = "cpu_clk_div5",
	850	+ .ops = &clk_fixed_factor_ops,
	851	+ .parent_hws = (const struct clk_hw *[]) {
	852	+ &meson8b_cpu_clk.hw
	853	+ },
	854	+ .num_parents = 1,
	855	+ },
	856	+};
	857	+
	858	+static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
	859	+ .mult = 1,
	860	+ .div = 6,
	861	+ .hw.init = &(struct clk_init_data){
	862	+ .name = "cpu_clk_div6",
	863	+ .ops = &clk_fixed_factor_ops,
	864	+ .parent_hws = (const struct clk_hw *[]) {
	865	+ &meson8b_cpu_clk.hw
	866	+ },
	867	+ .num_parents = 1,
	868	+ },
	869	+};
	870	+
	871	+static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
	872	+ .mult = 1,
	873	+ .div = 7,
	874	+ .hw.init = &(struct clk_init_data){
	875	+ .name = "cpu_clk_div7",
	876	+ .ops = &clk_fixed_factor_ops,
	877	+ .parent_hws = (const struct clk_hw *[]) {
	878	+ &meson8b_cpu_clk.hw
	879	+ },
	880	+ .num_parents = 1,
	881	+ },
	882	+};
	883	+
	884	+static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
	885	+ .mult = 1,
	886	+ .div = 8,
	887	+ .hw.init = &(struct clk_init_data){
	888	+ .name = "cpu_clk_div8",
	889	+ .ops = &clk_fixed_factor_ops,
	890	+ .parent_hws = (const struct clk_hw *[]) {
	891	+ &meson8b_cpu_clk.hw
	892	+ },
	893	+ .num_parents = 1,
	894	+ },
	895	+};
	896	+
	897	+static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
	898	+static struct clk_regmap meson8b_apb_clk_sel = {
	899	+ .data = &(struct clk_regmap_mux_data){
	900	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	901	+ .mask = 0x7,
	902	+ .shift = 3,
	903	+ .table = mux_table_apb,
	904	+ },
	905	+ .hw.init = &(struct clk_init_data){
	906	+ .name = "apb_clk_sel",
	907	+ .ops = &clk_regmap_mux_ops,
	908	+ .parent_hws = (const struct clk_hw *[]) {
	909	+ &meson8b_cpu_clk_div2.hw,
	910	+ &meson8b_cpu_clk_div3.hw,
	911	+ &meson8b_cpu_clk_div4.hw,
	912	+ &meson8b_cpu_clk_div5.hw,
	913	+ &meson8b_cpu_clk_div6.hw,
	914	+ &meson8b_cpu_clk_div7.hw,
	915	+ &meson8b_cpu_clk_div8.hw,
	916	+ },
	917	+ .num_parents = 7,
	918	+ },
	919	+};
	920	+
	921	+static struct clk_regmap meson8b_apb_clk_gate = {
	922	+ .data = &(struct clk_regmap_gate_data){
	923	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	924	+ .bit_idx = 16,
	925	+ .flags = CLK_GATE_SET_TO_DISABLE,
	926	+ },
	927	+ .hw.init = &(struct clk_init_data){
	928	+ .name = "apb_clk_dis",
	929	+ .ops = &clk_regmap_gate_ro_ops,
	930	+ .parent_hws = (const struct clk_hw *[]) {
	931	+ &meson8b_apb_clk_sel.hw
	932	+ },
	933	+ .num_parents = 1,
	934	+ .flags = CLK_SET_RATE_PARENT,
	935	+ },
	936	+};
	937	+
	938	+static struct clk_regmap meson8b_periph_clk_sel = {
	939	+ .data = &(struct clk_regmap_mux_data){
	940	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	941	+ .mask = 0x7,
	942	+ .shift = 6,
	943	+ },
	944	+ .hw.init = &(struct clk_init_data){
	945	+ .name = "periph_clk_sel",
	946	+ .ops = &clk_regmap_mux_ops,
	947	+ .parent_hws = (const struct clk_hw *[]) {
	948	+ &meson8b_cpu_clk_div2.hw,
	949	+ &meson8b_cpu_clk_div3.hw,
	950	+ &meson8b_cpu_clk_div4.hw,
	951	+ &meson8b_cpu_clk_div5.hw,
	952	+ &meson8b_cpu_clk_div6.hw,
	953	+ &meson8b_cpu_clk_div7.hw,
	954	+ &meson8b_cpu_clk_div8.hw,
	955	+ },
	956	+ .num_parents = 7,
	957	+ },
	958	+};
	959	+
	960	+static struct clk_regmap meson8b_periph_clk_gate = {
	961	+ .data = &(struct clk_regmap_gate_data){
	962	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	963	+ .bit_idx = 17,
	964	+ .flags = CLK_GATE_SET_TO_DISABLE,
	965	+ },
	966	+ .hw.init = &(struct clk_init_data){
	967	+ .name = "periph_clk_dis",
	968	+ .ops = &clk_regmap_gate_ro_ops,
	969	+ .parent_hws = (const struct clk_hw *[]) {
	970	+ &meson8b_periph_clk_sel.hw
	971	+ },
	972	+ .num_parents = 1,
	973	+ .flags = CLK_SET_RATE_PARENT,
	974	+ },
	975	+};
	976	+
	977	+static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
	978	+static struct clk_regmap meson8b_axi_clk_sel = {
	979	+ .data = &(struct clk_regmap_mux_data){
	980	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	981	+ .mask = 0x7,
	982	+ .shift = 9,
	983	+ .table = mux_table_axi,
	984	+ },
	985	+ .hw.init = &(struct clk_init_data){
	986	+ .name = "axi_clk_sel",
	987	+ .ops = &clk_regmap_mux_ops,
	988	+ .parent_hws = (const struct clk_hw *[]) {
	989	+ &meson8b_cpu_clk_div2.hw,
	990	+ &meson8b_cpu_clk_div3.hw,
	991	+ &meson8b_cpu_clk_div4.hw,
	992	+ &meson8b_cpu_clk_div5.hw,
	993	+ &meson8b_cpu_clk_div6.hw,
	994	+ &meson8b_cpu_clk_div7.hw,
	995	+ &meson8b_cpu_clk_div8.hw,
	996	+ },
	997	+ .num_parents = 7,
	998	+ },
	999	+};
	1000	+
	1001	+static struct clk_regmap meson8b_axi_clk_gate = {
	1002	+ .data = &(struct clk_regmap_gate_data){
	1003	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	1004	+ .bit_idx = 18,
	1005	+ .flags = CLK_GATE_SET_TO_DISABLE,
	1006	+ },
	1007	+ .hw.init = &(struct clk_init_data){
	1008	+ .name = "axi_clk_dis",
	1009	+ .ops = &clk_regmap_gate_ro_ops,
	1010	+ .parent_hws = (const struct clk_hw *[]) {
	1011	+ &meson8b_axi_clk_sel.hw
	1012	+ },
	1013	+ .num_parents = 1,
	1014	+ .flags = CLK_SET_RATE_PARENT,
	1015	+ },
	1016	+};
	1017	+
	1018	+static struct clk_regmap meson8b_l2_dram_clk_sel = {
	1019	+ .data = &(struct clk_regmap_mux_data){
	1020	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	1021	+ .mask = 0x7,
	1022	+ .shift = 12,
	1023	+ },
	1024	+ .hw.init = &(struct clk_init_data){
	1025	+ .name = "l2_dram_clk_sel",
	1026	+ .ops = &clk_regmap_mux_ops,
	1027	+ .parent_hws = (const struct clk_hw *[]) {
	1028	+ &meson8b_cpu_clk_div2.hw,
	1029	+ &meson8b_cpu_clk_div3.hw,
	1030	+ &meson8b_cpu_clk_div4.hw,
	1031	+ &meson8b_cpu_clk_div5.hw,
	1032	+ &meson8b_cpu_clk_div6.hw,
	1033	+ &meson8b_cpu_clk_div7.hw,
	1034	+ &meson8b_cpu_clk_div8.hw,
	1035	+ },
	1036	+ .num_parents = 7,
	1037	+ },
	1038	+};
	1039	+
	1040	+static struct clk_regmap meson8b_l2_dram_clk_gate = {
	1041	+ .data = &(struct clk_regmap_gate_data){
	1042	+ .offset = HHI_SYS_CPU_CLK_CNTL1,
	1043	+ .bit_idx = 19,
	1044	+ .flags = CLK_GATE_SET_TO_DISABLE,
	1045	+ },
	1046	+ .hw.init = &(struct clk_init_data){
	1047	+ .name = "l2_dram_clk_dis",
	1048	+ .ops = &clk_regmap_gate_ro_ops,
	1049	+ .parent_hws = (const struct clk_hw *[]) {
	1050	+ &meson8b_l2_dram_clk_sel.hw
	1051	+ },
	1052	+ .num_parents = 1,
	1053	+ .flags = CLK_SET_RATE_PARENT,
	1054	+ },
	1055	+};
	1056	+
	1057	+static struct clk_regmap meson8b_vid_pll_in_sel = {
	1058	+ .data = &(struct clk_regmap_mux_data){
	1059	+ .offset = HHI_VID_DIVIDER_CNTL,
	1060	+ .mask = 0x1,
	1061	+ .shift = 15,
	1062	+ },
	1063	+ .hw.init = &(struct clk_init_data){
	1064	+ .name = "vid_pll_in_sel",
	1065	+ .ops = &clk_regmap_mux_ro_ops,
	1066	+ /*
	1067	+ * TODO: depending on the SoC there is also a second parent:
	1068	+ * Meson8: unknown
	1069	+ * Meson8b: hdmi_pll_dco
	1070	+ * Meson8m2: vid2_pll
	1071	+ */
	1072	+ .parent_hws = (const struct clk_hw *[]) {
	1073	+ &meson8b_hdmi_pll_lvds_out.hw
	1074	+ },
	1075	+ .num_parents = 1,
	1076	+ .flags = CLK_SET_RATE_PARENT,
	1077	+ },
	1078	+};
	1079	+
	1080	+static struct clk_regmap meson8b_vid_pll_in_en = {
	1081	+ .data = &(struct clk_regmap_gate_data){
	1082	+ .offset = HHI_VID_DIVIDER_CNTL,
	1083	+ .bit_idx = 16,
	1084	+ },
	1085	+ .hw.init = &(struct clk_init_data){
	1086	+ .name = "vid_pll_in_en",
	1087	+ .ops = &clk_regmap_gate_ro_ops,
	1088	+ .parent_hws = (const struct clk_hw *[]) {
	1089	+ &meson8b_vid_pll_in_sel.hw
	1090	+ },
	1091	+ .num_parents = 1,
	1092	+ .flags = CLK_SET_RATE_PARENT,
	1093	+ },
	1094	+};
	1095	+
	1096	+static struct clk_regmap meson8b_vid_pll_pre_div = {
	1097	+ .data = &(struct clk_regmap_div_data){
	1098	+ .offset = HHI_VID_DIVIDER_CNTL,
	1099	+ .shift = 4,
	1100	+ .width = 3,
	1101	+ },
	1102	+ .hw.init = &(struct clk_init_data){
	1103	+ .name = "vid_pll_pre_div",
	1104	+ .ops = &clk_regmap_divider_ro_ops,
	1105	+ .parent_hws = (const struct clk_hw *[]) {
	1106	+ &meson8b_vid_pll_in_en.hw
	1107	+ },
	1108	+ .num_parents = 1,
	1109	+ .flags = CLK_SET_RATE_PARENT,
	1110	+ },
	1111	+};
	1112	+
	1113	+static struct clk_regmap meson8b_vid_pll_post_div = {
	1114	+ .data = &(struct clk_regmap_div_data){
	1115	+ .offset = HHI_VID_DIVIDER_CNTL,
	1116	+ .shift = 12,
	1117	+ .width = 3,
	1118	+ },
	1119	+ .hw.init = &(struct clk_init_data){
	1120	+ .name = "vid_pll_post_div",
	1121	+ .ops = &clk_regmap_divider_ro_ops,
	1122	+ .parent_hws = (const struct clk_hw *[]) {
	1123	+ &meson8b_vid_pll_pre_div.hw
	1124	+ },
	1125	+ .num_parents = 1,
	1126	+ .flags = CLK_SET_RATE_PARENT,
	1127	+ },
	1128	+};
	1129	+
	1130	+static struct clk_regmap meson8b_vid_pll = {
	1131	+ .data = &(struct clk_regmap_mux_data){
	1132	+ .offset = HHI_VID_DIVIDER_CNTL,
	1133	+ .mask = 0x3,
	1134	+ .shift = 8,
	1135	+ },
	1136	+ .hw.init = &(struct clk_init_data){
	1137	+ .name = "vid_pll",
	1138	+ .ops = &clk_regmap_mux_ro_ops,
	1139	+ /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
	1140	+ .parent_hws = (const struct clk_hw *[]) {
	1141	+ &meson8b_vid_pll_pre_div.hw,
	1142	+ &meson8b_vid_pll_post_div.hw,
	1143	+ },
	1144	+ .num_parents = 2,
	1145	+ .flags = CLK_SET_RATE_PARENT,
	1146	+ },
	1147	+};
	1148	+
	1149	+static struct clk_regmap meson8b_vid_pll_final_div = {
	1150	+ .data = &(struct clk_regmap_div_data){
	1151	+ .offset = HHI_VID_CLK_DIV,
	1152	+ .shift = 0,
	1153	+ .width = 8,
	1154	+ },
	1155	+ .hw.init = &(struct clk_init_data){
	1156	+ .name = "vid_pll_final_div",
	1157	+ .ops = &clk_regmap_divider_ro_ops,
	1158	+ .parent_hws = (const struct clk_hw *[]) {
	1159	+ &meson8b_vid_pll.hw
	1160	+ },
	1161	+ .num_parents = 1,
	1162	+ .flags = CLK_SET_RATE_PARENT,
	1163	+ },
	1164	+};
	1165	+
	1166	+static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
	1167	+ &meson8b_vid_pll_final_div.hw,
	1168	+ &meson8b_fclk_div4.hw,
	1169	+ &meson8b_fclk_div3.hw,
	1170	+ &meson8b_fclk_div5.hw,
	1171	+ &meson8b_vid_pll_final_div.hw,
	1172	+ &meson8b_fclk_div7.hw,
	1173	+ &meson8b_mpll1.hw,
	1174	+};
	1175	+
	1176	+static struct clk_regmap meson8b_vclk_in_sel = {
	1177	+ .data = &(struct clk_regmap_mux_data){
	1178	+ .offset = HHI_VID_CLK_CNTL,
	1179	+ .mask = 0x7,
	1180	+ .shift = 16,
	1181	+ },
	1182	+ .hw.init = &(struct clk_init_data){
	1183	+ .name = "vclk_in_sel",
	1184	+ .ops = &clk_regmap_mux_ro_ops,
	1185	+ .parent_hws = meson8b_vclk_mux_parent_hws,
	1186	+ .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
	1187	+ .flags = CLK_SET_RATE_PARENT,
	1188	+ },
	1189	+};
	1190	+
	1191	+static struct clk_regmap meson8b_vclk_in_en = {
	1192	+ .data = &(struct clk_regmap_gate_data){
	1193	+ .offset = HHI_VID_CLK_DIV,
	1194	+ .bit_idx = 16,
	1195	+ },
	1196	+ .hw.init = &(struct clk_init_data){
	1197	+ .name = "vclk_in_en",
	1198	+ .ops = &clk_regmap_gate_ro_ops,
	1199	+ .parent_hws = (const struct clk_hw *[]) {
	1200	+ &meson8b_vclk_in_sel.hw
	1201	+ },
	1202	+ .num_parents = 1,
	1203	+ .flags = CLK_SET_RATE_PARENT,
	1204	+ },
	1205	+};
	1206	+
	1207	+static struct clk_regmap meson8b_vclk_en = {
	1208	+ .data = &(struct clk_regmap_gate_data){
	1209	+ .offset = HHI_VID_CLK_CNTL,
	1210	+ .bit_idx = 19,
	1211	+ },
	1212	+ .hw.init = &(struct clk_init_data){
	1213	+ .name = "vclk_en",
	1214	+ .ops = &clk_regmap_gate_ro_ops,
	1215	+ .parent_hws = (const struct clk_hw *[]) {
	1216	+ &meson8b_vclk_in_en.hw
	1217	+ },
	1218	+ .num_parents = 1,
	1219	+ .flags = CLK_SET_RATE_PARENT,
	1220	+ },
	1221	+};
	1222	+
	1223	+static struct clk_regmap meson8b_vclk_div1_gate = {
	1224	+ .data = &(struct clk_regmap_gate_data){
	1225	+ .offset = HHI_VID_CLK_CNTL,
	1226	+ .bit_idx = 0,
	1227	+ },
	1228	+ .hw.init = &(struct clk_init_data){
	1229	+ .name = "vclk_div1_en",
	1230	+ .ops = &clk_regmap_gate_ro_ops,
	1231	+ .parent_hws = (const struct clk_hw *[]) {
	1232	+ &meson8b_vclk_en.hw
	1233	+ },
	1234	+ .num_parents = 1,
	1235	+ .flags = CLK_SET_RATE_PARENT,
	1236	+ },
	1237	+};
	1238	+
	1239	+static struct clk_fixed_factor meson8b_vclk_div2_div = {
	1240	+ .mult = 1,
	1241	+ .div = 2,
	1242	+ .hw.init = &(struct clk_init_data){
	1243	+ .name = "vclk_div2",
	1244	+ .ops = &clk_fixed_factor_ops,
	1245	+ .parent_hws = (const struct clk_hw *[]) {
	1246	+ &meson8b_vclk_en.hw
	1247	+ },
	1248	+ .num_parents = 1,
	1249	+ .flags = CLK_SET_RATE_PARENT,
	1250	+ }
	1251	+};
	1252	+
	1253	+static struct clk_regmap meson8b_vclk_div2_div_gate = {
	1254	+ .data = &(struct clk_regmap_gate_data){
	1255	+ .offset = HHI_VID_CLK_CNTL,
	1256	+ .bit_idx = 1,
	1257	+ },
	1258	+ .hw.init = &(struct clk_init_data){
	1259	+ .name = "vclk_div2_en",
	1260	+ .ops = &clk_regmap_gate_ro_ops,
	1261	+ .parent_hws = (const struct clk_hw *[]) {
	1262	+ &meson8b_vclk_div2_div.hw
	1263	+ },
	1264	+ .num_parents = 1,
	1265	+ .flags = CLK_SET_RATE_PARENT,
	1266	+ },
	1267	+};
	1268	+
	1269	+static struct clk_fixed_factor meson8b_vclk_div4_div = {
	1270	+ .mult = 1,
	1271	+ .div = 4,
	1272	+ .hw.init = &(struct clk_init_data){
	1273	+ .name = "vclk_div4",
	1274	+ .ops = &clk_fixed_factor_ops,
	1275	+ .parent_hws = (const struct clk_hw *[]) {
	1276	+ &meson8b_vclk_en.hw
	1277	+ },
	1278	+ .num_parents = 1,
	1279	+ .flags = CLK_SET_RATE_PARENT,
	1280	+ }
	1281	+};
	1282	+
	1283	+static struct clk_regmap meson8b_vclk_div4_div_gate = {
	1284	+ .data = &(struct clk_regmap_gate_data){
	1285	+ .offset = HHI_VID_CLK_CNTL,
	1286	+ .bit_idx = 2,
	1287	+ },
	1288	+ .hw.init = &(struct clk_init_data){
	1289	+ .name = "vclk_div4_en",
	1290	+ .ops = &clk_regmap_gate_ro_ops,
	1291	+ .parent_hws = (const struct clk_hw *[]) {
	1292	+ &meson8b_vclk_div4_div.hw
	1293	+ },
	1294	+ .num_parents = 1,
	1295	+ .flags = CLK_SET_RATE_PARENT,
	1296	+ },
	1297	+};
	1298	+
	1299	+static struct clk_fixed_factor meson8b_vclk_div6_div = {
	1300	+ .mult = 1,
	1301	+ .div = 6,
	1302	+ .hw.init = &(struct clk_init_data){
	1303	+ .name = "vclk_div6",
	1304	+ .ops = &clk_fixed_factor_ops,
	1305	+ .parent_hws = (const struct clk_hw *[]) {
	1306	+ &meson8b_vclk_en.hw
	1307	+ },
	1308	+ .num_parents = 1,
	1309	+ .flags = CLK_SET_RATE_PARENT,
	1310	+ }
	1311	+};
	1312	+
	1313	+static struct clk_regmap meson8b_vclk_div6_div_gate = {
	1314	+ .data = &(struct clk_regmap_gate_data){
	1315	+ .offset = HHI_VID_CLK_CNTL,
	1316	+ .bit_idx = 3,
	1317	+ },
	1318	+ .hw.init = &(struct clk_init_data){
	1319	+ .name = "vclk_div6_en",
	1320	+ .ops = &clk_regmap_gate_ro_ops,
	1321	+ .parent_hws = (const struct clk_hw *[]) {
	1322	+ &meson8b_vclk_div6_div.hw
	1323	+ },
	1324	+ .num_parents = 1,
	1325	+ .flags = CLK_SET_RATE_PARENT,
	1326	+ },
	1327	+};
	1328	+
	1329	+static struct clk_fixed_factor meson8b_vclk_div12_div = {
	1330	+ .mult = 1,
	1331	+ .div = 12,
	1332	+ .hw.init = &(struct clk_init_data){
	1333	+ .name = "vclk_div12",
	1334	+ .ops = &clk_fixed_factor_ops,
	1335	+ .parent_hws = (const struct clk_hw *[]) {
	1336	+ &meson8b_vclk_en.hw
	1337	+ },
	1338	+ .num_parents = 1,
	1339	+ .flags = CLK_SET_RATE_PARENT,
	1340	+ }
	1341	+};
	1342	+
	1343	+static struct clk_regmap meson8b_vclk_div12_div_gate = {
	1344	+ .data = &(struct clk_regmap_gate_data){
	1345	+ .offset = HHI_VID_CLK_CNTL,
	1346	+ .bit_idx = 4,
	1347	+ },
	1348	+ .hw.init = &(struct clk_init_data){
	1349	+ .name = "vclk_div12_en",
	1350	+ .ops = &clk_regmap_gate_ro_ops,
	1351	+ .parent_hws = (const struct clk_hw *[]) {
	1352	+ &meson8b_vclk_div12_div.hw
	1353	+ },
	1354	+ .num_parents = 1,
	1355	+ .flags = CLK_SET_RATE_PARENT,
	1356	+ },
	1357	+};
	1358	+
	1359	+static struct clk_regmap meson8b_vclk2_in_sel = {
	1360	+ .data = &(struct clk_regmap_mux_data){
	1361	+ .offset = HHI_VIID_CLK_CNTL,
	1362	+ .mask = 0x7,
	1363	+ .shift = 16,
	1364	+ },
	1365	+ .hw.init = &(struct clk_init_data){
	1366	+ .name = "vclk2_in_sel",
	1367	+ .ops = &clk_regmap_mux_ro_ops,
	1368	+ .parent_hws = meson8b_vclk_mux_parent_hws,
	1369	+ .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
	1370	+ .flags = CLK_SET_RATE_PARENT,
	1371	+ },
	1372	+};
	1373	+
	1374	+static struct clk_regmap meson8b_vclk2_clk_in_en = {
	1375	+ .data = &(struct clk_regmap_gate_data){
	1376	+ .offset = HHI_VIID_CLK_DIV,
	1377	+ .bit_idx = 16,
	1378	+ },
	1379	+ .hw.init = &(struct clk_init_data){
	1380	+ .name = "vclk2_in_en",
	1381	+ .ops = &clk_regmap_gate_ro_ops,
	1382	+ .parent_hws = (const struct clk_hw *[]) {
	1383	+ &meson8b_vclk2_in_sel.hw
	1384	+ },
	1385	+ .num_parents = 1,
	1386	+ .flags = CLK_SET_RATE_PARENT,
	1387	+ },
	1388	+};
	1389	+
	1390	+static struct clk_regmap meson8b_vclk2_clk_en = {
	1391	+ .data = &(struct clk_regmap_gate_data){
	1392	+ .offset = HHI_VIID_CLK_DIV,
	1393	+ .bit_idx = 19,
	1394	+ },
	1395	+ .hw.init = &(struct clk_init_data){
	1396	+ .name = "vclk2_en",
	1397	+ .ops = &clk_regmap_gate_ro_ops,
	1398	+ .parent_hws = (const struct clk_hw *[]) {
	1399	+ &meson8b_vclk2_clk_in_en.hw
	1400	+ },
	1401	+ .num_parents = 1,
	1402	+ .flags = CLK_SET_RATE_PARENT,
	1403	+ },
	1404	+};
	1405	+
	1406	+static struct clk_regmap meson8b_vclk2_div1_gate = {
	1407	+ .data = &(struct clk_regmap_gate_data){
	1408	+ .offset = HHI_VIID_CLK_DIV,
	1409	+ .bit_idx = 0,
	1410	+ },
	1411	+ .hw.init = &(struct clk_init_data){
	1412	+ .name = "vclk2_div1_en",
	1413	+ .ops = &clk_regmap_gate_ro_ops,
	1414	+ .parent_hws = (const struct clk_hw *[]) {
	1415	+ &meson8b_vclk2_clk_en.hw
	1416	+ },
	1417	+ .num_parents = 1,
	1418	+ .flags = CLK_SET_RATE_PARENT,
	1419	+ },
	1420	+};
	1421	+
	1422	+static struct clk_fixed_factor meson8b_vclk2_div2_div = {
	1423	+ .mult = 1,
	1424	+ .div = 2,
	1425	+ .hw.init = &(struct clk_init_data){
	1426	+ .name = "vclk2_div2",
	1427	+ .ops = &clk_fixed_factor_ops,
	1428	+ .parent_hws = (const struct clk_hw *[]) {
	1429	+ &meson8b_vclk2_clk_en.hw
	1430	+ },
	1431	+ .num_parents = 1,
	1432	+ .flags = CLK_SET_RATE_PARENT,
	1433	+ }
	1434	+};
	1435	+
	1436	+static struct clk_regmap meson8b_vclk2_div2_div_gate = {
	1437	+ .data = &(struct clk_regmap_gate_data){
	1438	+ .offset = HHI_VIID_CLK_DIV,
	1439	+ .bit_idx = 1,
	1440	+ },
	1441	+ .hw.init = &(struct clk_init_data){
	1442	+ .name = "vclk2_div2_en",
	1443	+ .ops = &clk_regmap_gate_ro_ops,
	1444	+ .parent_hws = (const struct clk_hw *[]) {
	1445	+ &meson8b_vclk2_div2_div.hw
	1446	+ },
	1447	+ .num_parents = 1,
	1448	+ .flags = CLK_SET_RATE_PARENT,
	1449	+ },
	1450	+};
	1451	+
	1452	+static struct clk_fixed_factor meson8b_vclk2_div4_div = {
	1453	+ .mult = 1,
	1454	+ .div = 4,
	1455	+ .hw.init = &(struct clk_init_data){
	1456	+ .name = "vclk2_div4",
	1457	+ .ops = &clk_fixed_factor_ops,
	1458	+ .parent_hws = (const struct clk_hw *[]) {
	1459	+ &meson8b_vclk2_clk_en.hw
	1460	+ },
	1461	+ .num_parents = 1,
	1462	+ .flags = CLK_SET_RATE_PARENT,
	1463	+ }
	1464	+};
	1465	+
	1466	+static struct clk_regmap meson8b_vclk2_div4_div_gate = {
	1467	+ .data = &(struct clk_regmap_gate_data){
	1468	+ .offset = HHI_VIID_CLK_DIV,
	1469	+ .bit_idx = 2,
	1470	+ },
	1471	+ .hw.init = &(struct clk_init_data){
	1472	+ .name = "vclk2_div4_en",
	1473	+ .ops = &clk_regmap_gate_ro_ops,
	1474	+ .parent_hws = (const struct clk_hw *[]) {
	1475	+ &meson8b_vclk2_div4_div.hw
	1476	+ },
	1477	+ .num_parents = 1,
	1478	+ .flags = CLK_SET_RATE_PARENT,
	1479	+ },
	1480	+};
	1481	+
	1482	+static struct clk_fixed_factor meson8b_vclk2_div6_div = {
	1483	+ .mult = 1,
	1484	+ .div = 6,
	1485	+ .hw.init = &(struct clk_init_data){
	1486	+ .name = "vclk2_div6",
	1487	+ .ops = &clk_fixed_factor_ops,
	1488	+ .parent_hws = (const struct clk_hw *[]) {
	1489	+ &meson8b_vclk2_clk_en.hw
	1490	+ },
	1491	+ .num_parents = 1,
	1492	+ .flags = CLK_SET_RATE_PARENT,
	1493	+ }
	1494	+};
	1495	+
	1496	+static struct clk_regmap meson8b_vclk2_div6_div_gate = {
	1497	+ .data = &(struct clk_regmap_gate_data){
	1498	+ .offset = HHI_VIID_CLK_DIV,
	1499	+ .bit_idx = 3,
	1500	+ },
	1501	+ .hw.init = &(struct clk_init_data){
	1502	+ .name = "vclk2_div6_en",
	1503	+ .ops = &clk_regmap_gate_ro_ops,
	1504	+ .parent_hws = (const struct clk_hw *[]) {
	1505	+ &meson8b_vclk2_div6_div.hw
	1506	+ },
	1507	+ .num_parents = 1,
	1508	+ .flags = CLK_SET_RATE_PARENT,
	1509	+ },
	1510	+};
	1511	+
	1512	+static struct clk_fixed_factor meson8b_vclk2_div12_div = {
	1513	+ .mult = 1,
	1514	+ .div = 12,
	1515	+ .hw.init = &(struct clk_init_data){
	1516	+ .name = "vclk2_div12",
	1517	+ .ops = &clk_fixed_factor_ops,
	1518	+ .parent_hws = (const struct clk_hw *[]) {
	1519	+ &meson8b_vclk2_clk_en.hw
	1520	+ },
	1521	+ .num_parents = 1,
	1522	+ .flags = CLK_SET_RATE_PARENT,
	1523	+ }
	1524	+};
	1525	+
	1526	+static struct clk_regmap meson8b_vclk2_div12_div_gate = {
	1527	+ .data = &(struct clk_regmap_gate_data){
	1528	+ .offset = HHI_VIID_CLK_DIV,
	1529	+ .bit_idx = 4,
	1530	+ },
	1531	+ .hw.init = &(struct clk_init_data){
	1532	+ .name = "vclk2_div12_en",
	1533	+ .ops = &clk_regmap_gate_ro_ops,
	1534	+ .parent_hws = (const struct clk_hw *[]) {
	1535	+ &meson8b_vclk2_div12_div.hw
	1536	+ },
	1537	+ .num_parents = 1,
	1538	+ .flags = CLK_SET_RATE_PARENT,
	1539	+ },
	1540	+};
	1541	+
	1542	+static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
	1543	+ &meson8b_vclk_div1_gate.hw,
	1544	+ &meson8b_vclk_div2_div_gate.hw,
	1545	+ &meson8b_vclk_div4_div_gate.hw,
	1546	+ &meson8b_vclk_div6_div_gate.hw,
	1547	+ &meson8b_vclk_div12_div_gate.hw,
	1548	+};
	1549	+
	1550	+static struct clk_regmap meson8b_cts_enct_sel = {
	1551	+ .data = &(struct clk_regmap_mux_data){
	1552	+ .offset = HHI_VID_CLK_DIV,
	1553	+ .mask = 0xf,
	1554	+ .shift = 20,
	1555	+ },
	1556	+ .hw.init = &(struct clk_init_data){
	1557	+ .name = "cts_enct_sel",
	1558	+ .ops = &clk_regmap_mux_ro_ops,
	1559	+ .parent_hws = meson8b_vclk_enc_mux_parent_hws,
	1560	+ .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
	1561	+ .flags = CLK_SET_RATE_PARENT,
	1562	+ },
	1563	+};
	1564	+
	1565	+static struct clk_regmap meson8b_cts_enct = {
	1566	+ .data = &(struct clk_regmap_gate_data){
	1567	+ .offset = HHI_VID_CLK_CNTL2,
	1568	+ .bit_idx = 1,
	1569	+ },
	1570	+ .hw.init = &(struct clk_init_data){
	1571	+ .name = "cts_enct",
	1572	+ .ops = &clk_regmap_gate_ro_ops,
	1573	+ .parent_hws = (const struct clk_hw *[]) {
	1574	+ &meson8b_cts_enct_sel.hw
	1575	+ },
	1576	+ .num_parents = 1,
	1577	+ .flags = CLK_SET_RATE_PARENT,
	1578	+ },
	1579	+};
	1580	+
	1581	+static struct clk_regmap meson8b_cts_encp_sel = {
	1582	+ .data = &(struct clk_regmap_mux_data){
	1583	+ .offset = HHI_VID_CLK_DIV,
	1584	+ .mask = 0xf,
	1585	+ .shift = 24,
	1586	+ },
	1587	+ .hw.init = &(struct clk_init_data){
	1588	+ .name = "cts_encp_sel",
	1589	+ .ops = &clk_regmap_mux_ro_ops,
	1590	+ .parent_hws = meson8b_vclk_enc_mux_parent_hws,
	1591	+ .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
	1592	+ .flags = CLK_SET_RATE_PARENT,
	1593	+ },
	1594	+};
	1595	+
	1596	+static struct clk_regmap meson8b_cts_encp = {
	1597	+ .data = &(struct clk_regmap_gate_data){
	1598	+ .offset = HHI_VID_CLK_CNTL2,
	1599	+ .bit_idx = 2,
	1600	+ },
	1601	+ .hw.init = &(struct clk_init_data){
	1602	+ .name = "cts_encp",
	1603	+ .ops = &clk_regmap_gate_ro_ops,
	1604	+ .parent_hws = (const struct clk_hw *[]) {
	1605	+ &meson8b_cts_encp_sel.hw
	1606	+ },
	1607	+ .num_parents = 1,
	1608	+ .flags = CLK_SET_RATE_PARENT,
	1609	+ },
	1610	+};
	1611	+
	1612	+static struct clk_regmap meson8b_cts_enci_sel = {
	1613	+ .data = &(struct clk_regmap_mux_data){
	1614	+ .offset = HHI_VID_CLK_DIV,
	1615	+ .mask = 0xf,
	1616	+ .shift = 28,
	1617	+ },
	1618	+ .hw.init = &(struct clk_init_data){
	1619	+ .name = "cts_enci_sel",
	1620	+ .ops = &clk_regmap_mux_ro_ops,
	1621	+ .parent_hws = meson8b_vclk_enc_mux_parent_hws,
	1622	+ .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
	1623	+ .flags = CLK_SET_RATE_PARENT,
	1624	+ },
	1625	+};
	1626	+
	1627	+static struct clk_regmap meson8b_cts_enci = {
	1628	+ .data = &(struct clk_regmap_gate_data){
	1629	+ .offset = HHI_VID_CLK_CNTL2,
	1630	+ .bit_idx = 0,
	1631	+ },
	1632	+ .hw.init = &(struct clk_init_data){
	1633	+ .name = "cts_enci",
	1634	+ .ops = &clk_regmap_gate_ro_ops,
	1635	+ .parent_hws = (const struct clk_hw *[]) {
	1636	+ &meson8b_cts_enci_sel.hw
	1637	+ },
	1638	+ .num_parents = 1,
	1639	+ .flags = CLK_SET_RATE_PARENT,
	1640	+ },
	1641	+};
	1642	+
	1643	+static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
	1644	+ .data = &(struct clk_regmap_mux_data){
	1645	+ .offset = HHI_HDMI_CLK_CNTL,
	1646	+ .mask = 0xf,
	1647	+ .shift = 16,
	1648	+ },
	1649	+ .hw.init = &(struct clk_init_data){
	1650	+ .name = "hdmi_tx_pixel_sel",
	1651	+ .ops = &clk_regmap_mux_ro_ops,
	1652	+ .parent_hws = meson8b_vclk_enc_mux_parent_hws,
	1653	+ .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
	1654	+ .flags = CLK_SET_RATE_PARENT,
	1655	+ },
	1656	+};
	1657	+
	1658	+static struct clk_regmap meson8b_hdmi_tx_pixel = {
	1659	+ .data = &(struct clk_regmap_gate_data){
	1660	+ .offset = HHI_VID_CLK_CNTL2,
	1661	+ .bit_idx = 5,
	1662	+ },
	1663	+ .hw.init = &(struct clk_init_data){
	1664	+ .name = "hdmi_tx_pixel",
	1665	+ .ops = &clk_regmap_gate_ro_ops,
	1666	+ .parent_hws = (const struct clk_hw *[]) {
	1667	+ &meson8b_hdmi_tx_pixel_sel.hw
	1668	+ },
	1669	+ .num_parents = 1,
	1670	+ .flags = CLK_SET_RATE_PARENT,
	1671	+ },
	1672	+};
	1673	+
	1674	+static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
	1675	+ &meson8b_vclk2_div1_gate.hw,
	1676	+ &meson8b_vclk2_div2_div_gate.hw,
	1677	+ &meson8b_vclk2_div4_div_gate.hw,
	1678	+ &meson8b_vclk2_div6_div_gate.hw,
	1679	+ &meson8b_vclk2_div12_div_gate.hw,
	1680	+};
	1681	+
	1682	+static struct clk_regmap meson8b_cts_encl_sel = {
	1683	+ .data = &(struct clk_regmap_mux_data){
	1684	+ .offset = HHI_VIID_CLK_DIV,
	1685	+ .mask = 0xf,
	1686	+ .shift = 12,
	1687	+ },
	1688	+ .hw.init = &(struct clk_init_data){
	1689	+ .name = "cts_encl_sel",
	1690	+ .ops = &clk_regmap_mux_ro_ops,
	1691	+ .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
	1692	+ .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
	1693	+ .flags = CLK_SET_RATE_PARENT,
	1694	+ },
	1695	+};
	1696	+
	1697	+static struct clk_regmap meson8b_cts_encl = {
	1698	+ .data = &(struct clk_regmap_gate_data){
	1699	+ .offset = HHI_VID_CLK_CNTL2,
	1700	+ .bit_idx = 3,
	1701	+ },
	1702	+ .hw.init = &(struct clk_init_data){
	1703	+ .name = "cts_encl",
	1704	+ .ops = &clk_regmap_gate_ro_ops,
	1705	+ .parent_hws = (const struct clk_hw *[]) {
	1706	+ &meson8b_cts_encl_sel.hw
	1707	+ },
	1708	+ .num_parents = 1,
	1709	+ .flags = CLK_SET_RATE_PARENT,
	1710	+ },
	1711	+};
	1712	+
	1713	+static struct clk_regmap meson8b_cts_vdac0_sel = {
	1714	+ .data = &(struct clk_regmap_mux_data){
	1715	+ .offset = HHI_VIID_CLK_DIV,
	1716	+ .mask = 0xf,
	1717	+ .shift = 28,
	1718	+ },
	1719	+ .hw.init = &(struct clk_init_data){
	1720	+ .name = "cts_vdac0_sel",
	1721	+ .ops = &clk_regmap_mux_ro_ops,
	1722	+ .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
	1723	+ .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
	1724	+ .flags = CLK_SET_RATE_PARENT,
	1725	+ },
	1726	+};
	1727	+
	1728	+static struct clk_regmap meson8b_cts_vdac0 = {
	1729	+ .data = &(struct clk_regmap_gate_data){
	1730	+ .offset = HHI_VID_CLK_CNTL2,
	1731	+ .bit_idx = 4,
	1732	+ },
	1733	+ .hw.init = &(struct clk_init_data){
	1734	+ .name = "cts_vdac0",
	1735	+ .ops = &clk_regmap_gate_ro_ops,
	1736	+ .parent_hws = (const struct clk_hw *[]) {
	1737	+ &meson8b_cts_vdac0_sel.hw
	1738	+ },
	1739	+ .num_parents = 1,
	1740	+ .flags = CLK_SET_RATE_PARENT,
	1741	+ },
	1742	+};
	1743	+
	1744	+static struct clk_regmap meson8b_hdmi_sys_sel = {
	1745	+ .data = &(struct clk_regmap_mux_data){
	1746	+ .offset = HHI_HDMI_CLK_CNTL,
	1747	+ .mask = 0x3,
	1748	+ .shift = 9,
	1749	+ .flags = CLK_MUX_ROUND_CLOSEST,
	1750	+ },
	1751	+ .hw.init = &(struct clk_init_data){
	1752	+ .name = "hdmi_sys_sel",
	1753	+ .ops = &clk_regmap_mux_ops,
	1754	+ /* FIXME: all other parents are unknown */
	1755	+ .parent_data = &(const struct clk_parent_data) {
	1756	+ .fw_name = "xtal",
	1757	+ .name = "xtal",
	1758	+ .index = -1,
	1759	+ },
	1760	+ .num_parents = 1,
	1761	+ .flags = CLK_SET_RATE_NO_REPARENT,
	1762	+ },
	1763	+};
	1764	+
	1765	+static struct clk_regmap meson8b_hdmi_sys_div = {
	1766	+ .data = &(struct clk_regmap_div_data){
	1767	+ .offset = HHI_HDMI_CLK_CNTL,
	1768	+ .shift = 0,
	1769	+ .width = 7,
	1770	+ },
	1771	+ .hw.init = &(struct clk_init_data){
	1772	+ .name = "hdmi_sys_div",
	1773	+ .ops = &clk_regmap_divider_ops,
	1774	+ .parent_hws = (const struct clk_hw *[]) {
	1775	+ &meson8b_hdmi_sys_sel.hw
	1776	+ },
	1777	+ .num_parents = 1,
	1778	+ .flags = CLK_SET_RATE_PARENT,
	1779	+ },
	1780	+};
	1781	+
	1782	+static struct clk_regmap meson8b_hdmi_sys = {
	1783	+ .data = &(struct clk_regmap_gate_data){
	1784	+ .offset = HHI_HDMI_CLK_CNTL,
	1785	+ .bit_idx = 8,
	1786	+ },
	1787	+ .hw.init = &(struct clk_init_data) {
	1788	+ .name = "hdmi_sys",
	1789	+ .ops = &clk_regmap_gate_ops,
	1790	+ .parent_hws = (const struct clk_hw *[]) {
	1791	+ &meson8b_hdmi_sys_div.hw
	1792	+ },
	1793	+ .num_parents = 1,
	1794	+ .flags = CLK_SET_RATE_PARENT,
	1795	+ },
	1796	+};
	1797	+
	1798	+/*
	1799	+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
	1800	+ * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
	1801	+ * actually manage this glitch-free mux because it does top-to-bottom
	1802	+ * updates the each clock tree and switches to the "inactive" one when
	1803	+ * CLK_SET_RATE_GATE is set.
	1804	+ * Meson8 only has mali_0 and no glitch-free mux.
	1805	+ */
	1806	+static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
	1807	+ { .fw_name = "xtal", .name = "xtal", .index = -1, },
	1808	+ { .hw = &meson8b_mpll2.hw, },
	1809	+ { .hw = &meson8b_mpll1.hw, },
	1810	+ { .hw = &meson8b_fclk_div7.hw, },
	1811	+ { .hw = &meson8b_fclk_div4.hw, },
	1812	+ { .hw = &meson8b_fclk_div3.hw, },
	1813	+ { .hw = &meson8b_fclk_div5.hw, },
	1814	+};
	1815	+
	1816	+static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
	1817	+
	1818	+static struct clk_regmap meson8b_mali_0_sel = {
	1819	+ .data = &(struct clk_regmap_mux_data){
	1820	+ .offset = HHI_MALI_CLK_CNTL,
	1821	+ .mask = 0x7,
	1822	+ .shift = 9,
	1823	+ .table = meson8b_mali_0_1_mux_table,
	1824	+ },
	1825	+ .hw.init = &(struct clk_init_data){
	1826	+ .name = "mali_0_sel",
	1827	+ .ops = &clk_regmap_mux_ops,
	1828	+ .parent_data = meson8b_mali_0_1_parent_data,
	1829	+ .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
	1830	+ /*
	1831	+ * Don't propagate rate changes up because the only changeable
	1832	+ * parents are mpll1 and mpll2 but we need those for audio and
	1833	+ * RGMII (Ethernet). We don't want to change the audio or
	1834	+ * Ethernet clocks when setting the GPU frequency.
	1835	+ */
	1836	+ .flags = 0,
	1837	+ },
	1838	+};
	1839	+
	1840	+static struct clk_regmap meson8b_mali_0_div = {
	1841	+ .data = &(struct clk_regmap_div_data){
	1842	+ .offset = HHI_MALI_CLK_CNTL,
	1843	+ .shift = 0,
	1844	+ .width = 7,
	1845	+ },
	1846	+ .hw.init = &(struct clk_init_data){
	1847	+ .name = "mali_0_div",
	1848	+ .ops = &clk_regmap_divider_ops,
	1849	+ .parent_hws = (const struct clk_hw *[]) {
	1850	+ &meson8b_mali_0_sel.hw
	1851	+ },
	1852	+ .num_parents = 1,
	1853	+ .flags = CLK_SET_RATE_PARENT,
	1854	+ },
	1855	+};
	1856	+
	1857	+static struct clk_regmap meson8b_mali_0 = {
	1858	+ .data = &(struct clk_regmap_gate_data){
	1859	+ .offset = HHI_MALI_CLK_CNTL,
	1860	+ .bit_idx = 8,
	1861	+ },
	1862	+ .hw.init = &(struct clk_init_data){
	1863	+ .name = "mali_0",
	1864	+ .ops = &clk_regmap_gate_ops,
	1865	+ .parent_hws = (const struct clk_hw *[]) {
	1866	+ &meson8b_mali_0_div.hw
	1867	+ },
	1868	+ .num_parents = 1,
	1869	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
	1870	+ },
	1871	+};
	1872	+
	1873	+static struct clk_regmap meson8b_mali_1_sel = {
	1874	+ .data = &(struct clk_regmap_mux_data){
	1875	+ .offset = HHI_MALI_CLK_CNTL,
	1876	+ .mask = 0x7,
	1877	+ .shift = 25,
	1878	+ .table = meson8b_mali_0_1_mux_table,
	1879	+ },
	1880	+ .hw.init = &(struct clk_init_data){
	1881	+ .name = "mali_1_sel",
	1882	+ .ops = &clk_regmap_mux_ops,
	1883	+ .parent_data = meson8b_mali_0_1_parent_data,
	1884	+ .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
	1885	+ /*
	1886	+ * Don't propagate rate changes up because the only changeable
	1887	+ * parents are mpll1 and mpll2 but we need those for audio and
	1888	+ * RGMII (Ethernet). We don't want to change the audio or
	1889	+ * Ethernet clocks when setting the GPU frequency.
	1890	+ */
	1891	+ .flags = 0,
	1892	+ },
	1893	+};
	1894	+
	1895	+static struct clk_regmap meson8b_mali_1_div = {
	1896	+ .data = &(struct clk_regmap_div_data){
	1897	+ .offset = HHI_MALI_CLK_CNTL,
	1898	+ .shift = 16,
	1899	+ .width = 7,
	1900	+ },
	1901	+ .hw.init = &(struct clk_init_data){
	1902	+ .name = "mali_1_div",
	1903	+ .ops = &clk_regmap_divider_ops,
	1904	+ .parent_hws = (const struct clk_hw *[]) {
	1905	+ &meson8b_mali_1_sel.hw
	1906	+ },
	1907	+ .num_parents = 1,
	1908	+ .flags = CLK_SET_RATE_PARENT,
	1909	+ },
	1910	+};
	1911	+
	1912	+static struct clk_regmap meson8b_mali_1 = {
	1913	+ .data = &(struct clk_regmap_gate_data){
	1914	+ .offset = HHI_MALI_CLK_CNTL,
	1915	+ .bit_idx = 24,
	1916	+ },
	1917	+ .hw.init = &(struct clk_init_data){
	1918	+ .name = "mali_1",
	1919	+ .ops = &clk_regmap_gate_ops,
	1920	+ .parent_hws = (const struct clk_hw *[]) {
	1921	+ &meson8b_mali_1_div.hw
	1922	+ },
	1923	+ .num_parents = 1,
	1924	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
	1925	+ },
	1926	+};
	1927	+
	1928	+static struct clk_regmap meson8b_mali = {
	1929	+ .data = &(struct clk_regmap_mux_data){
	1930	+ .offset = HHI_MALI_CLK_CNTL,
	1931	+ .mask = 1,
	1932	+ .shift = 31,
	1933	+ },
	1934	+ .hw.init = &(struct clk_init_data){
	1935	+ .name = "mali",
	1936	+ .ops = &clk_regmap_mux_ops,
	1937	+ .parent_hws = (const struct clk_hw *[]) {
	1938	+ &meson8b_mali_0.hw,
	1939	+ &meson8b_mali_1.hw,
	1940	+ },
	1941	+ .num_parents = 2,
	1942	+ .flags = CLK_SET_RATE_PARENT,
	1943	+ },
	1944	+};
	1945	+
	1946	+static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
	1947	+ { .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 },
	1948	+ { .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 },
	1949	+ { .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 },
	1950	+ { .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 },
	1951	+};
	1952	+
	1953	+static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
	1954	+ PLL_PARAMS(182, 3),
	1955	+ { /* sentinel */ },
	1956	+};
	1957	+
	1958	+static struct clk_regmap meson8m2_gp_pll_dco = {
	1959	+ .data = &(struct meson_clk_pll_data){
	1960	+ .en = {
	1961	+ .reg_off = HHI_GP_PLL_CNTL,
	1962	+ .shift = 30,
	1963	+ .width = 1,
	1964	+ },
	1965	+ .m = {
	1966	+ .reg_off = HHI_GP_PLL_CNTL,
	1967	+ .shift = 0,
	1968	+ .width = 9,
	1969	+ },
	1970	+ .n = {
	1971	+ .reg_off = HHI_GP_PLL_CNTL,
	1972	+ .shift = 9,
	1973	+ .width = 5,
	1974	+ },
	1975	+ .l = {
	1976	+ .reg_off = HHI_GP_PLL_CNTL,
	1977	+ .shift = 31,
	1978	+ .width = 1,
	1979	+ },
	1980	+ .rst = {
	1981	+ .reg_off = HHI_GP_PLL_CNTL,
	1982	+ .shift = 29,
	1983	+ .width = 1,
	1984	+ },
	1985	+ .table = meson8m2_gp_pll_params_table,
	1986	+ .init_regs = meson8m2_gp_pll_init_regs,
	1987	+ .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
	1988	+ },
	1989	+ .hw.init = &(struct clk_init_data){
	1990	+ .name = "gp_pll_dco",
	1991	+ .ops = &meson_clk_pll_ops,
	1992	+ .parent_data = &(const struct clk_parent_data) {
	1993	+ .fw_name = "xtal",
	1994	+ .name = "xtal",
	1995	+ .index = -1,
	1996	+ },
	1997	+ .num_parents = 1,
	1998	+ },
	1999	+};
	2000	+
	2001	+static struct clk_regmap meson8m2_gp_pll = {
	2002	+ .data = &(struct clk_regmap_div_data){
	2003	+ .offset = HHI_GP_PLL_CNTL,
	2004	+ .shift = 16,
	2005	+ .width = 2,
	2006	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	2007	+ },
	2008	+ .hw.init = &(struct clk_init_data){
	2009	+ .name = "gp_pll",
	2010	+ .ops = &clk_regmap_divider_ops,
	2011	+ .parent_hws = (const struct clk_hw *[]) {
	2012	+ &meson8m2_gp_pll_dco.hw
	2013	+ },
	2014	+ .num_parents = 1,
	2015	+ .flags = CLK_SET_RATE_PARENT,
	2016	+ },
	2017	+};
	2018	+
	2019	+static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
	2020	+ &meson8b_fclk_div4.hw,
	2021	+ &meson8b_fclk_div3.hw,
	2022	+ &meson8b_fclk_div5.hw,
	2023	+ &meson8b_fclk_div7.hw,
	2024	+};
	2025	+
	2026	+static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
	2027	+ &meson8b_fclk_div4.hw,
	2028	+ &meson8b_fclk_div3.hw,
	2029	+ &meson8b_fclk_div5.hw,
	2030	+ &meson8m2_gp_pll.hw,
	2031	+};
	2032	+
	2033	+static struct clk_regmap meson8b_vpu_0_sel = {
	2034	+ .data = &(struct clk_regmap_mux_data){
	2035	+ .offset = HHI_VPU_CLK_CNTL,
	2036	+ .mask = 0x3,
	2037	+ .shift = 9,
	2038	+ },
	2039	+ .hw.init = &(struct clk_init_data){
	2040	+ .name = "vpu_0_sel",
	2041	+ .ops = &clk_regmap_mux_ops,
	2042	+ .parent_hws = meson8b_vpu_0_1_parent_hws,
	2043	+ .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
	2044	+ .flags = CLK_SET_RATE_PARENT,
	2045	+ },
	2046	+};
	2047	+
	2048	+static struct clk_regmap meson8m2_vpu_0_sel = {
	2049	+ .data = &(struct clk_regmap_mux_data){
	2050	+ .offset = HHI_VPU_CLK_CNTL,
	2051	+ .mask = 0x3,
	2052	+ .shift = 9,
	2053	+ },
	2054	+ .hw.init = &(struct clk_init_data){
	2055	+ .name = "vpu_0_sel",
	2056	+ .ops = &clk_regmap_mux_ops,
	2057	+ .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
	2058	+ .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
	2059	+ .flags = CLK_SET_RATE_PARENT,
	2060	+ },
	2061	+};
	2062	+
	2063	+static struct clk_regmap meson8b_vpu_0_div = {
	2064	+ .data = &(struct clk_regmap_div_data){
	2065	+ .offset = HHI_VPU_CLK_CNTL,
	2066	+ .shift = 0,
	2067	+ .width = 7,
	2068	+ },
	2069	+ .hw.init = &(struct clk_init_data){
	2070	+ .name = "vpu_0_div",
	2071	+ .ops = &clk_regmap_divider_ops,
	2072	+ .parent_data = &(const struct clk_parent_data) {
	2073	+ /*
	2074	+ * Note:
	2075	+ * meson8b and meson8m2 have different vpu_0_sels (with
	2076	+ * different struct clk_hw). We fallback to the global
	2077	+ * naming string mechanism so vpu_0_div picks up the
	2078	+ * appropriate one.
	2079	+ */
	2080	+ .name = "vpu_0_sel",
	2081	+ .index = -1,
	2082	+ },
	2083	+ .num_parents = 1,
	2084	+ .flags = CLK_SET_RATE_PARENT,
	2085	+ },
	2086	+};
	2087	+
	2088	+static struct clk_regmap meson8b_vpu_0 = {
	2089	+ .data = &(struct clk_regmap_gate_data){
	2090	+ .offset = HHI_VPU_CLK_CNTL,
	2091	+ .bit_idx = 8,
	2092	+ },
	2093	+ .hw.init = &(struct clk_init_data) {
	2094	+ .name = "vpu_0",
	2095	+ .ops = &clk_regmap_gate_ops,
	2096	+ .parent_hws = (const struct clk_hw *[]) {
	2097	+ &meson8b_vpu_0_div.hw
	2098	+ },
	2099	+ .num_parents = 1,
	2100	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
	2101	+ },
	2102	+};
	2103	+
	2104	+static struct clk_regmap meson8b_vpu_1_sel = {
	2105	+ .data = &(struct clk_regmap_mux_data){
	2106	+ .offset = HHI_VPU_CLK_CNTL,
	2107	+ .mask = 0x3,
	2108	+ .shift = 25,
	2109	+ },
	2110	+ .hw.init = &(struct clk_init_data){
	2111	+ .name = "vpu_1_sel",
	2112	+ .ops = &clk_regmap_mux_ops,
	2113	+ .parent_hws = meson8b_vpu_0_1_parent_hws,
	2114	+ .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
	2115	+ .flags = CLK_SET_RATE_PARENT,
	2116	+ },
	2117	+};
	2118	+
	2119	+static struct clk_regmap meson8m2_vpu_1_sel = {
	2120	+ .data = &(struct clk_regmap_mux_data){
	2121	+ .offset = HHI_VPU_CLK_CNTL,
	2122	+ .mask = 0x3,
	2123	+ .shift = 25,
	2124	+ },
	2125	+ .hw.init = &(struct clk_init_data){
	2126	+ .name = "vpu_1_sel",
	2127	+ .ops = &clk_regmap_mux_ops,
	2128	+ .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
	2129	+ .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
	2130	+ .flags = CLK_SET_RATE_PARENT,
	2131	+ },
	2132	+};
	2133	+
	2134	+static struct clk_regmap meson8b_vpu_1_div = {
	2135	+ .data = &(struct clk_regmap_div_data){
	2136	+ .offset = HHI_VPU_CLK_CNTL,
	2137	+ .shift = 16,
	2138	+ .width = 7,
	2139	+ },
	2140	+ .hw.init = &(struct clk_init_data){
	2141	+ .name = "vpu_1_div",
	2142	+ .ops = &clk_regmap_divider_ops,
	2143	+ .parent_data = &(const struct clk_parent_data) {
	2144	+ /*
	2145	+ * Note:
	2146	+ * meson8b and meson8m2 have different vpu_1_sels (with
	2147	+ * different struct clk_hw). We fallback to the global
	2148	+ * naming string mechanism so vpu_1_div picks up the
	2149	+ * appropriate one.
	2150	+ */
	2151	+ .name = "vpu_1_sel",
	2152	+ .index = -1,
	2153	+ },
	2154	+ .num_parents = 1,
	2155	+ .flags = CLK_SET_RATE_PARENT,
	2156	+ },
	2157	+};
	2158	+
	2159	+static struct clk_regmap meson8b_vpu_1 = {
	2160	+ .data = &(struct clk_regmap_gate_data){
	2161	+ .offset = HHI_VPU_CLK_CNTL,
	2162	+ .bit_idx = 24,
	2163	+ },
	2164	+ .hw.init = &(struct clk_init_data) {
	2165	+ .name = "vpu_1",
	2166	+ .ops = &clk_regmap_gate_ops,
	2167	+ .parent_hws = (const struct clk_hw *[]) {
	2168	+ &meson8b_vpu_1_div.hw
	2169	+ },
	2170	+ .num_parents = 1,
	2171	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
	2172	+ },
	2173	+};
	2174	+
	2175	+/*
	2176	+ * The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
	2177	+ * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
	2178	+ * actually manage this glitch-free mux because it does top-to-bottom
	2179	+ * updates the each clock tree and switches to the "inactive" one when
	2180	+ * CLK_SET_RATE_GATE is set.
	2181	+ * Meson8 only has vpu_0 and no glitch-free mux.
	2182	+ */
	2183	+static struct clk_regmap meson8b_vpu = {
	2184	+ .data = &(struct clk_regmap_mux_data){
	2185	+ .offset = HHI_VPU_CLK_CNTL,
	2186	+ .mask = 1,
	2187	+ .shift = 31,
	2188	+ },
	2189	+ .hw.init = &(struct clk_init_data){
	2190	+ .name = "vpu",
	2191	+ .ops = &clk_regmap_mux_ops,
	2192	+ .parent_hws = (const struct clk_hw *[]) {
	2193	+ &meson8b_vpu_0.hw,
	2194	+ &meson8b_vpu_1.hw,
	2195	+ },
	2196	+ .num_parents = 2,
	2197	+ .flags = CLK_SET_RATE_PARENT,
	2198	+ },
	2199	+};
	2200	+
	2201	+static const struct clk_hw *meson8b_vdec_parent_hws[] = {
	2202	+ &meson8b_fclk_div4.hw,
	2203	+ &meson8b_fclk_div3.hw,
	2204	+ &meson8b_fclk_div5.hw,
	2205	+ &meson8b_fclk_div7.hw,
	2206	+ &meson8b_mpll2.hw,
	2207	+ &meson8b_mpll1.hw,
	2208	+};
	2209	+
	2210	+static struct clk_regmap meson8b_vdec_1_sel = {
	2211	+ .data = &(struct clk_regmap_mux_data){
	2212	+ .offset = HHI_VDEC_CLK_CNTL,
	2213	+ .mask = 0x3,
	2214	+ .shift = 9,
	2215	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2216	+ },
	2217	+ .hw.init = &(struct clk_init_data){
	2218	+ .name = "vdec_1_sel",
	2219	+ .ops = &clk_regmap_mux_ops,
	2220	+ .parent_hws = meson8b_vdec_parent_hws,
	2221	+ .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
	2222	+ .flags = CLK_SET_RATE_PARENT,
	2223	+ },
	2224	+};
	2225	+
	2226	+static struct clk_regmap meson8b_vdec_1_1_div = {
	2227	+ .data = &(struct clk_regmap_div_data){
	2228	+ .offset = HHI_VDEC_CLK_CNTL,
	2229	+ .shift = 0,
	2230	+ .width = 7,
	2231	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2232	+ },
	2233	+ .hw.init = &(struct clk_init_data){
	2234	+ .name = "vdec_1_1_div",
	2235	+ .ops = &clk_regmap_divider_ops,
	2236	+ .parent_hws = (const struct clk_hw *[]) {
	2237	+ &meson8b_vdec_1_sel.hw
	2238	+ },
	2239	+ .num_parents = 1,
	2240	+ .flags = CLK_SET_RATE_PARENT,
	2241	+ },
	2242	+};
	2243	+
	2244	+static struct clk_regmap meson8b_vdec_1_1 = {
	2245	+ .data = &(struct clk_regmap_gate_data){
	2246	+ .offset = HHI_VDEC_CLK_CNTL,
	2247	+ .bit_idx = 8,
	2248	+ },
	2249	+ .hw.init = &(struct clk_init_data) {
	2250	+ .name = "vdec_1_1",
	2251	+ .ops = &clk_regmap_gate_ops,
	2252	+ .parent_hws = (const struct clk_hw *[]) {
	2253	+ &meson8b_vdec_1_1_div.hw
	2254	+ },
	2255	+ .num_parents = 1,
	2256	+ .flags = CLK_SET_RATE_PARENT,
	2257	+ },
	2258	+};
	2259	+
	2260	+static struct clk_regmap meson8b_vdec_1_2_div = {
	2261	+ .data = &(struct clk_regmap_div_data){
	2262	+ .offset = HHI_VDEC3_CLK_CNTL,
	2263	+ .shift = 0,
	2264	+ .width = 7,
	2265	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2266	+ },
	2267	+ .hw.init = &(struct clk_init_data){
	2268	+ .name = "vdec_1_2_div",
	2269	+ .ops = &clk_regmap_divider_ops,
	2270	+ .parent_hws = (const struct clk_hw *[]) {
	2271	+ &meson8b_vdec_1_sel.hw
	2272	+ },
	2273	+ .num_parents = 1,
	2274	+ .flags = CLK_SET_RATE_PARENT,
	2275	+ },
	2276	+};
	2277	+
	2278	+static struct clk_regmap meson8b_vdec_1_2 = {
	2279	+ .data = &(struct clk_regmap_gate_data){
	2280	+ .offset = HHI_VDEC3_CLK_CNTL,
	2281	+ .bit_idx = 8,
	2282	+ },
	2283	+ .hw.init = &(struct clk_init_data) {
	2284	+ .name = "vdec_1_2",
	2285	+ .ops = &clk_regmap_gate_ops,
	2286	+ .parent_hws = (const struct clk_hw *[]) {
	2287	+ &meson8b_vdec_1_2_div.hw
	2288	+ },
	2289	+ .num_parents = 1,
	2290	+ .flags = CLK_SET_RATE_PARENT,
	2291	+ },
	2292	+};
	2293	+
	2294	+static struct clk_regmap meson8b_vdec_1 = {
	2295	+ .data = &(struct clk_regmap_mux_data){
	2296	+ .offset = HHI_VDEC3_CLK_CNTL,
	2297	+ .mask = 0x1,
	2298	+ .shift = 15,
	2299	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2300	+ },
	2301	+ .hw.init = &(struct clk_init_data){
	2302	+ .name = "vdec_1",
	2303	+ .ops = &clk_regmap_mux_ops,
	2304	+ .parent_hws = (const struct clk_hw *[]) {
	2305	+ &meson8b_vdec_1_1.hw,
	2306	+ &meson8b_vdec_1_2.hw,
	2307	+ },
	2308	+ .num_parents = 2,
	2309	+ .flags = CLK_SET_RATE_PARENT,
	2310	+ },
	2311	+};
	2312	+
	2313	+static struct clk_regmap meson8b_vdec_hcodec_sel = {
	2314	+ .data = &(struct clk_regmap_mux_data){
	2315	+ .offset = HHI_VDEC_CLK_CNTL,
	2316	+ .mask = 0x3,
	2317	+ .shift = 25,
	2318	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2319	+ },
	2320	+ .hw.init = &(struct clk_init_data){
	2321	+ .name = "vdec_hcodec_sel",
	2322	+ .ops = &clk_regmap_mux_ops,
	2323	+ .parent_hws = meson8b_vdec_parent_hws,
	2324	+ .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
	2325	+ .flags = CLK_SET_RATE_PARENT,
	2326	+ },
	2327	+};
	2328	+
	2329	+static struct clk_regmap meson8b_vdec_hcodec_div = {
	2330	+ .data = &(struct clk_regmap_div_data){
	2331	+ .offset = HHI_VDEC_CLK_CNTL,
	2332	+ .shift = 16,
	2333	+ .width = 7,
	2334	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2335	+ },
	2336	+ .hw.init = &(struct clk_init_data){
	2337	+ .name = "vdec_hcodec_div",
	2338	+ .ops = &clk_regmap_divider_ops,
	2339	+ .parent_hws = (const struct clk_hw *[]) {
	2340	+ &meson8b_vdec_hcodec_sel.hw
	2341	+ },
	2342	+ .num_parents = 1,
	2343	+ .flags = CLK_SET_RATE_PARENT,
	2344	+ },
	2345	+};
	2346	+
	2347	+static struct clk_regmap meson8b_vdec_hcodec = {
	2348	+ .data = &(struct clk_regmap_gate_data){
	2349	+ .offset = HHI_VDEC_CLK_CNTL,
	2350	+ .bit_idx = 24,
	2351	+ },
	2352	+ .hw.init = &(struct clk_init_data) {
	2353	+ .name = "vdec_hcodec",
	2354	+ .ops = &clk_regmap_gate_ops,
	2355	+ .parent_hws = (const struct clk_hw *[]) {
	2356	+ &meson8b_vdec_hcodec_div.hw
	2357	+ },
	2358	+ .num_parents = 1,
	2359	+ .flags = CLK_SET_RATE_PARENT,
	2360	+ },
	2361	+};
	2362	+
	2363	+static struct clk_regmap meson8b_vdec_2_sel = {
	2364	+ .data = &(struct clk_regmap_mux_data){
	2365	+ .offset = HHI_VDEC2_CLK_CNTL,
	2366	+ .mask = 0x3,
	2367	+ .shift = 9,
	2368	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2369	+ },
	2370	+ .hw.init = &(struct clk_init_data){
	2371	+ .name = "vdec_2_sel",
	2372	+ .ops = &clk_regmap_mux_ops,
	2373	+ .parent_hws = meson8b_vdec_parent_hws,
	2374	+ .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
	2375	+ .flags = CLK_SET_RATE_PARENT,
	2376	+ },
	2377	+};
	2378	+
	2379	+static struct clk_regmap meson8b_vdec_2_div = {
	2380	+ .data = &(struct clk_regmap_div_data){
	2381	+ .offset = HHI_VDEC2_CLK_CNTL,
	2382	+ .shift = 0,
	2383	+ .width = 7,
	2384	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2385	+ },
	2386	+ .hw.init = &(struct clk_init_data){
	2387	+ .name = "vdec_2_div",
	2388	+ .ops = &clk_regmap_divider_ops,
	2389	+ .parent_hws = (const struct clk_hw *[]) {
	2390	+ &meson8b_vdec_2_sel.hw
	2391	+ },
	2392	+ .num_parents = 1,
	2393	+ .flags = CLK_SET_RATE_PARENT,
	2394	+ },
	2395	+};
	2396	+
	2397	+static struct clk_regmap meson8b_vdec_2 = {
	2398	+ .data = &(struct clk_regmap_gate_data){
	2399	+ .offset = HHI_VDEC2_CLK_CNTL,
	2400	+ .bit_idx = 8,
	2401	+ },
	2402	+ .hw.init = &(struct clk_init_data) {
	2403	+ .name = "vdec_2",
	2404	+ .ops = &clk_regmap_gate_ops,
	2405	+ .parent_hws = (const struct clk_hw *[]) {
	2406	+ &meson8b_vdec_2_div.hw
	2407	+ },
	2408	+ .num_parents = 1,
	2409	+ .flags = CLK_SET_RATE_PARENT,
	2410	+ },
	2411	+};
	2412	+
	2413	+static struct clk_regmap meson8b_vdec_hevc_sel = {
	2414	+ .data = &(struct clk_regmap_mux_data){
	2415	+ .offset = HHI_VDEC2_CLK_CNTL,
	2416	+ .mask = 0x3,
	2417	+ .shift = 25,
	2418	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2419	+ },
	2420	+ .hw.init = &(struct clk_init_data){
	2421	+ .name = "vdec_hevc_sel",
	2422	+ .ops = &clk_regmap_mux_ops,
	2423	+ .parent_hws = meson8b_vdec_parent_hws,
	2424	+ .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
	2425	+ .flags = CLK_SET_RATE_PARENT,
	2426	+ },
	2427	+};
	2428	+
	2429	+static struct clk_regmap meson8b_vdec_hevc_div = {
	2430	+ .data = &(struct clk_regmap_div_data){
	2431	+ .offset = HHI_VDEC2_CLK_CNTL,
	2432	+ .shift = 16,
	2433	+ .width = 7,
	2434	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2435	+ },
	2436	+ .hw.init = &(struct clk_init_data){
	2437	+ .name = "vdec_hevc_div",
	2438	+ .ops = &clk_regmap_divider_ops,
	2439	+ .parent_hws = (const struct clk_hw *[]) {
	2440	+ &meson8b_vdec_hevc_sel.hw
	2441	+ },
	2442	+ .num_parents = 1,
	2443	+ .flags = CLK_SET_RATE_PARENT,
	2444	+ },
	2445	+};
	2446	+
	2447	+static struct clk_regmap meson8b_vdec_hevc_en = {
	2448	+ .data = &(struct clk_regmap_gate_data){
	2449	+ .offset = HHI_VDEC2_CLK_CNTL,
	2450	+ .bit_idx = 24,
	2451	+ },
	2452	+ .hw.init = &(struct clk_init_data) {
	2453	+ .name = "vdec_hevc_en",
	2454	+ .ops = &clk_regmap_gate_ops,
	2455	+ .parent_hws = (const struct clk_hw *[]) {
	2456	+ &meson8b_vdec_hevc_div.hw
	2457	+ },
	2458	+ .num_parents = 1,
	2459	+ .flags = CLK_SET_RATE_PARENT,
	2460	+ },
	2461	+};
	2462	+
	2463	+static struct clk_regmap meson8b_vdec_hevc = {
	2464	+ .data = &(struct clk_regmap_mux_data){
	2465	+ .offset = HHI_VDEC2_CLK_CNTL,
	2466	+ .mask = 0x1,
	2467	+ .shift = 31,
	2468	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2469	+ },
	2470	+ .hw.init = &(struct clk_init_data){
	2471	+ .name = "vdec_hevc",
	2472	+ .ops = &clk_regmap_mux_ops,
	2473	+ /* TODO: The second parent is currently unknown */
	2474	+ .parent_hws = (const struct clk_hw *[]) {
	2475	+ &meson8b_vdec_hevc_en.hw
	2476	+ },
	2477	+ .num_parents = 1,
	2478	+ .flags = CLK_SET_RATE_PARENT,
	2479	+ },
	2480	+};
	2481	+
	2482	+/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
	2483	+static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
	2484	+ &meson8b_mpll0.hw,
	2485	+ &meson8b_mpll1.hw,
	2486	+ &meson8b_mpll2.hw
	2487	+};
	2488	+
	2489	+static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
	2490	+
	2491	+static struct clk_regmap meson8b_cts_amclk_sel = {
	2492	+ .data = &(struct clk_regmap_mux_data){
	2493	+ .offset = HHI_AUD_CLK_CNTL,
	2494	+ .mask = 0x3,
	2495	+ .shift = 9,
	2496	+ .table = meson8b_cts_amclk_mux_table,
	2497	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2498	+ },
	2499	+ .hw.init = &(struct clk_init_data){
	2500	+ .name = "cts_amclk_sel",
	2501	+ .ops = &clk_regmap_mux_ops,
	2502	+ .parent_hws = meson8b_cts_amclk_parent_hws,
	2503	+ .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
	2504	+ },
	2505	+};
	2506	+
	2507	+static struct clk_regmap meson8b_cts_amclk_div = {
	2508	+ .data = &(struct clk_regmap_div_data) {
	2509	+ .offset = HHI_AUD_CLK_CNTL,
	2510	+ .shift = 0,
	2511	+ .width = 8,
	2512	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2513	+ },
	2514	+ .hw.init = &(struct clk_init_data){
	2515	+ .name = "cts_amclk_div",
	2516	+ .ops = &clk_regmap_divider_ops,
	2517	+ .parent_hws = (const struct clk_hw *[]) {
	2518	+ &meson8b_cts_amclk_sel.hw
	2519	+ },
	2520	+ .num_parents = 1,
	2521	+ .flags = CLK_SET_RATE_PARENT,
	2522	+ },
	2523	+};
	2524	+
	2525	+static struct clk_regmap meson8b_cts_amclk = {
	2526	+ .data = &(struct clk_regmap_gate_data){
	2527	+ .offset = HHI_AUD_CLK_CNTL,
	2528	+ .bit_idx = 8,
	2529	+ },
	2530	+ .hw.init = &(struct clk_init_data){
	2531	+ .name = "cts_amclk",
	2532	+ .ops = &clk_regmap_gate_ops,
	2533	+ .parent_hws = (const struct clk_hw *[]) {
	2534	+ &meson8b_cts_amclk_div.hw
	2535	+ },
	2536	+ .num_parents = 1,
	2537	+ .flags = CLK_SET_RATE_PARENT,
	2538	+ },
	2539	+};
	2540	+
	2541	+/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
	2542	+static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
	2543	+ &meson8b_mpll0.hw,
	2544	+ &meson8b_mpll1.hw,
	2545	+ &meson8b_mpll2.hw
	2546	+};
	2547	+
	2548	+static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
	2549	+
	2550	+static struct clk_regmap meson8b_cts_mclk_i958_sel = {
	2551	+ .data = &(struct clk_regmap_mux_data){
	2552	+ .offset = HHI_AUD_CLK_CNTL2,
	2553	+ .mask = 0x3,
	2554	+ .shift = 25,
	2555	+ .table = meson8b_cts_mclk_i958_mux_table,
	2556	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2557	+ },
	2558	+ .hw.init = &(struct clk_init_data) {
	2559	+ .name = "cts_mclk_i958_sel",
	2560	+ .ops = &clk_regmap_mux_ops,
	2561	+ .parent_hws = meson8b_cts_mclk_i958_parent_hws,
	2562	+ .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
	2563	+ },
	2564	+};
	2565	+
	2566	+static struct clk_regmap meson8b_cts_mclk_i958_div = {
	2567	+ .data = &(struct clk_regmap_div_data){
	2568	+ .offset = HHI_AUD_CLK_CNTL2,
	2569	+ .shift = 16,
	2570	+ .width = 8,
	2571	+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
	2572	+ },
	2573	+ .hw.init = &(struct clk_init_data) {
	2574	+ .name = "cts_mclk_i958_div",
	2575	+ .ops = &clk_regmap_divider_ops,
	2576	+ .parent_hws = (const struct clk_hw *[]) {
	2577	+ &meson8b_cts_mclk_i958_sel.hw
	2578	+ },
	2579	+ .num_parents = 1,
	2580	+ .flags = CLK_SET_RATE_PARENT,
	2581	+ },
	2582	+};
	2583	+
	2584	+static struct clk_regmap meson8b_cts_mclk_i958 = {
	2585	+ .data = &(struct clk_regmap_gate_data){
	2586	+ .offset = HHI_AUD_CLK_CNTL2,
	2587	+ .bit_idx = 24,
	2588	+ },
	2589	+ .hw.init = &(struct clk_init_data){
	2590	+ .name = "cts_mclk_i958",
	2591	+ .ops = &clk_regmap_gate_ops,
	2592	+ .parent_hws = (const struct clk_hw *[]) {
	2593	+ &meson8b_cts_mclk_i958_div.hw
	2594	+ },
	2595	+ .num_parents = 1,
	2596	+ .flags = CLK_SET_RATE_PARENT,
	2597	+ },
	2598	+};
	2599	+
	2600	+static struct clk_regmap meson8b_cts_i958 = {
	2601	+ .data = &(struct clk_regmap_mux_data){
	2602	+ .offset = HHI_AUD_CLK_CNTL2,
	2603	+ .mask = 0x1,
	2604	+ .shift = 27,
	2605	+ },
	2606	+ .hw.init = &(struct clk_init_data){
	2607	+ .name = "cts_i958",
	2608	+ .ops = &clk_regmap_mux_ops,
	2609	+ .parent_hws = (const struct clk_hw *[]) {
	2610	+ &meson8b_cts_amclk.hw,
	2611	+ &meson8b_cts_mclk_i958.hw
	2612	+ },
	2613	+ .num_parents = 2,
	2614	+ /*
	2615	+ * The parent is specific to origin of the audio data. Let the
	2616	+ * consumer choose the appropriate parent.
	2617	+ */
	2618	+ .flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
	2619	+ },
	2620	+};
	2621	+
	2622	+#define MESON_GATE(_name, _reg, _bit) \
	2623	+ MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
689	2624
690	2625	/* Everything Else (EE) domain gates */
691	2626
..	..	@@ -712,14 +2647,6 @@
712	2647	static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
713	2648	static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
714	2649	static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
715		-static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
716		-static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
717		-static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
718		-static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
719		-static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
720		-static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
721		-static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
722		-static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
723	2650	static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
724	2651	static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
725	2652	static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
..	..	@@ -766,12 +2693,232 @@
766	2693	static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
767	2694	static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
768	2695
	2696	+/* AIU gates */
	2697	+#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
	2698	+ MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
	2699	+
	2700	+static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
	2701	+static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
	2702	+static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
	2703	+static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
	2704	+static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
	2705	+static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
	2706	+static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
	2707	+static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
	2708	+
769	2709	/* Always On (AO) domain gates */
770	2710
771	2711	static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
772	2712	static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
773	2713	static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
774	2714	static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
	2715	+
	2716	+static struct clk_hw_onecell_data meson8_hw_onecell_data = {
	2717	+ .hws = {
	2718	+ [CLKID_XTAL] = &meson8b_xtal.hw,
	2719	+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
	2720	+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
	2721	+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
	2722	+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
	2723	+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
	2724	+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
	2725	+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
	2726	+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
	2727	+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
	2728	+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
	2729	+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
	2730	+ [CLKID_CLK81] = &meson8b_clk81.hw,
	2731	+ [CLKID_DDR] = &meson8b_ddr.hw,
	2732	+ [CLKID_DOS] = &meson8b_dos.hw,
	2733	+ [CLKID_ISA] = &meson8b_isa.hw,
	2734	+ [CLKID_PL301] = &meson8b_pl301.hw,
	2735	+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
	2736	+ [CLKID_SPICC] = &meson8b_spicc.hw,
	2737	+ [CLKID_I2C] = &meson8b_i2c.hw,
	2738	+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
	2739	+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
	2740	+ [CLKID_RNG0] = &meson8b_rng0.hw,
	2741	+ [CLKID_UART0] = &meson8b_uart0.hw,
	2742	+ [CLKID_SDHC] = &meson8b_sdhc.hw,
	2743	+ [CLKID_STREAM] = &meson8b_stream.hw,
	2744	+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
	2745	+ [CLKID_SDIO] = &meson8b_sdio.hw,
	2746	+ [CLKID_ABUF] = &meson8b_abuf.hw,
	2747	+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
	2748	+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
	2749	+ [CLKID_SPI] = &meson8b_spi.hw,
	2750	+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
	2751	+ [CLKID_ETH] = &meson8b_eth.hw,
	2752	+ [CLKID_DEMUX] = &meson8b_demux.hw,
	2753	+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
	2754	+ [CLKID_IEC958] = &meson8b_iec958.hw,
	2755	+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
	2756	+ [CLKID_AMCLK] = &meson8b_amclk.hw,
	2757	+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
	2758	+ [CLKID_MIXER] = &meson8b_mixer.hw,
	2759	+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
	2760	+ [CLKID_ADC] = &meson8b_adc.hw,
	2761	+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
	2762	+ [CLKID_AIU] = &meson8b_aiu.hw,
	2763	+ [CLKID_UART1] = &meson8b_uart1.hw,
	2764	+ [CLKID_G2D] = &meson8b_g2d.hw,
	2765	+ [CLKID_USB0] = &meson8b_usb0.hw,
	2766	+ [CLKID_USB1] = &meson8b_usb1.hw,
	2767	+ [CLKID_RESET] = &meson8b_reset.hw,
	2768	+ [CLKID_NAND] = &meson8b_nand.hw,
	2769	+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
	2770	+ [CLKID_USB] = &meson8b_usb.hw,
	2771	+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
	2772	+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
	2773	+ [CLKID_EFUSE] = &meson8b_efuse.hw,
	2774	+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
	2775	+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
	2776	+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
	2777	+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
	2778	+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
	2779	+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
	2780	+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
	2781	+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
	2782	+ [CLKID_DVIN] = &meson8b_dvin.hw,
	2783	+ [CLKID_UART2] = &meson8b_uart2.hw,
	2784	+ [CLKID_SANA] = &meson8b_sana.hw,
	2785	+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
	2786	+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
	2787	+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
	2788	+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
	2789	+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
	2790	+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
	2791	+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
	2792	+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
	2793	+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
	2794	+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
	2795	+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
	2796	+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
	2797	+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
	2798	+ [CLKID_RNG1] = &meson8b_rng1.hw,
	2799	+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
	2800	+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
	2801	+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
	2802	+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
	2803	+ [CLKID_EDP] = &meson8b_edp.hw,
	2804	+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
	2805	+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
	2806	+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
	2807	+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
	2808	+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
	2809	+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
	2810	+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
	2811	+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
	2812	+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
	2813	+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
	2814	+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
	2815	+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
	2816	+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
	2817	+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
	2818	+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
	2819	+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
	2820	+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
	2821	+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
	2822	+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
	2823	+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
	2824	+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
	2825	+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
	2826	+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
	2827	+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
	2828	+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
	2829	+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
	2830	+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
	2831	+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
	2832	+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
	2833	+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
	2834	+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
	2835	+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
	2836	+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
	2837	+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
	2838	+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
	2839	+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
	2840	+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
	2841	+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
	2842	+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
	2843	+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
	2844	+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
	2845	+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
	2846	+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
	2847	+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
	2848	+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
	2849	+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
	2850	+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
	2851	+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
	2852	+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
	2853	+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
	2854	+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
	2855	+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
	2856	+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
	2857	+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
	2858	+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
	2859	+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
	2860	+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
	2861	+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
	2862	+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
	2863	+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
	2864	+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
	2865	+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
	2866	+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
	2867	+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
	2868	+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
	2869	+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
	2870	+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
	2871	+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
	2872	+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
	2873	+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
	2874	+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
	2875	+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
	2876	+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
	2877	+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
	2878	+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
	2879	+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
	2880	+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
	2881	+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
	2882	+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
	2883	+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
	2884	+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
	2885	+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
	2886	+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
	2887	+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
	2888	+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
	2889	+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
	2890	+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
	2891	+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
	2892	+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
	2893	+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
	2894	+ [CLKID_MALI] = &meson8b_mali_0.hw,
	2895	+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
	2896	+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
	2897	+ [CLKID_VPU] = &meson8b_vpu_0.hw,
	2898	+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
	2899	+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
	2900	+ [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
	2901	+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
	2902	+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
	2903	+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
	2904	+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
	2905	+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
	2906	+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
	2907	+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
	2908	+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
	2909	+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
	2910	+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
	2911	+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
	2912	+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
	2913	+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
	2914	+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
	2915	+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
	2916	+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
	2917	+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
	2918	+ [CLK_NR_CLKS] = NULL,
	2919	+ },
	2920	+ .num = CLK_NR_CLKS,
	2921	+};
775	2922
776	2923	static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
777	2924	.hws = {
..	..	@@ -872,8 +3019,8 @@
872	3019	[CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
873	3020	[CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
874	3021	[CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
875		- [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw,
876		- [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw,
	3022	+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
	3023	+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
877	3024	[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
878	3025	[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
879	3026	[CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
..	..	@@ -885,6 +3032,327 @@
885	3032	[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
886	3033	[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
887	3034	[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
	3035	+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
	3036	+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
	3037	+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
	3038	+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
	3039	+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
	3040	+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
	3041	+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
	3042	+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
	3043	+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
	3044	+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
	3045	+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
	3046	+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
	3047	+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
	3048	+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
	3049	+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
	3050	+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
	3051	+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
	3052	+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
	3053	+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
	3054	+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
	3055	+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
	3056	+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
	3057	+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
	3058	+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
	3059	+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
	3060	+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
	3061	+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
	3062	+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
	3063	+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
	3064	+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
	3065	+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
	3066	+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
	3067	+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
	3068	+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
	3069	+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
	3070	+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
	3071	+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
	3072	+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
	3073	+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
	3074	+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
	3075	+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
	3076	+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
	3077	+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
	3078	+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
	3079	+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
	3080	+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
	3081	+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
	3082	+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
	3083	+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
	3084	+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
	3085	+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
	3086	+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
	3087	+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
	3088	+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
	3089	+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
	3090	+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
	3091	+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
	3092	+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
	3093	+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
	3094	+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
	3095	+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
	3096	+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
	3097	+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
	3098	+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
	3099	+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
	3100	+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
	3101	+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
	3102	+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
	3103	+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
	3104	+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
	3105	+ [CLKID_MALI] = &meson8b_mali.hw,
	3106	+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
	3107	+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
	3108	+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
	3109	+ [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
	3110	+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
	3111	+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
	3112	+ [CLKID_VPU] = &meson8b_vpu.hw,
	3113	+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
	3114	+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
	3115	+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
	3116	+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
	3117	+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
	3118	+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
	3119	+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
	3120	+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
	3121	+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
	3122	+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
	3123	+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
	3124	+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
	3125	+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
	3126	+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
	3127	+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
	3128	+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
	3129	+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
	3130	+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
	3131	+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
	3132	+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
	3133	+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
	3134	+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
	3135	+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
	3136	+ [CLK_NR_CLKS] = NULL,
	3137	+ },
	3138	+ .num = CLK_NR_CLKS,
	3139	+};
	3140	+
	3141	+static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
	3142	+ .hws = {
	3143	+ [CLKID_XTAL] = &meson8b_xtal.hw,
	3144	+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
	3145	+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
	3146	+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
	3147	+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
	3148	+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
	3149	+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
	3150	+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
	3151	+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
	3152	+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
	3153	+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
	3154	+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
	3155	+ [CLKID_CLK81] = &meson8b_clk81.hw,
	3156	+ [CLKID_DDR] = &meson8b_ddr.hw,
	3157	+ [CLKID_DOS] = &meson8b_dos.hw,
	3158	+ [CLKID_ISA] = &meson8b_isa.hw,
	3159	+ [CLKID_PL301] = &meson8b_pl301.hw,
	3160	+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
	3161	+ [CLKID_SPICC] = &meson8b_spicc.hw,
	3162	+ [CLKID_I2C] = &meson8b_i2c.hw,
	3163	+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
	3164	+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
	3165	+ [CLKID_RNG0] = &meson8b_rng0.hw,
	3166	+ [CLKID_UART0] = &meson8b_uart0.hw,
	3167	+ [CLKID_SDHC] = &meson8b_sdhc.hw,
	3168	+ [CLKID_STREAM] = &meson8b_stream.hw,
	3169	+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
	3170	+ [CLKID_SDIO] = &meson8b_sdio.hw,
	3171	+ [CLKID_ABUF] = &meson8b_abuf.hw,
	3172	+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
	3173	+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
	3174	+ [CLKID_SPI] = &meson8b_spi.hw,
	3175	+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
	3176	+ [CLKID_ETH] = &meson8b_eth.hw,
	3177	+ [CLKID_DEMUX] = &meson8b_demux.hw,
	3178	+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
	3179	+ [CLKID_IEC958] = &meson8b_iec958.hw,
	3180	+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
	3181	+ [CLKID_AMCLK] = &meson8b_amclk.hw,
	3182	+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
	3183	+ [CLKID_MIXER] = &meson8b_mixer.hw,
	3184	+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
	3185	+ [CLKID_ADC] = &meson8b_adc.hw,
	3186	+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
	3187	+ [CLKID_AIU] = &meson8b_aiu.hw,
	3188	+ [CLKID_UART1] = &meson8b_uart1.hw,
	3189	+ [CLKID_G2D] = &meson8b_g2d.hw,
	3190	+ [CLKID_USB0] = &meson8b_usb0.hw,
	3191	+ [CLKID_USB1] = &meson8b_usb1.hw,
	3192	+ [CLKID_RESET] = &meson8b_reset.hw,
	3193	+ [CLKID_NAND] = &meson8b_nand.hw,
	3194	+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
	3195	+ [CLKID_USB] = &meson8b_usb.hw,
	3196	+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
	3197	+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
	3198	+ [CLKID_EFUSE] = &meson8b_efuse.hw,
	3199	+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
	3200	+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
	3201	+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
	3202	+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
	3203	+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
	3204	+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
	3205	+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
	3206	+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
	3207	+ [CLKID_DVIN] = &meson8b_dvin.hw,
	3208	+ [CLKID_UART2] = &meson8b_uart2.hw,
	3209	+ [CLKID_SANA] = &meson8b_sana.hw,
	3210	+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
	3211	+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
	3212	+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
	3213	+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
	3214	+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
	3215	+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
	3216	+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
	3217	+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
	3218	+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
	3219	+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
	3220	+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
	3221	+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
	3222	+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
	3223	+ [CLKID_RNG1] = &meson8b_rng1.hw,
	3224	+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
	3225	+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
	3226	+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
	3227	+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
	3228	+ [CLKID_EDP] = &meson8b_edp.hw,
	3229	+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
	3230	+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
	3231	+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
	3232	+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
	3233	+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
	3234	+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
	3235	+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
	3236	+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
	3237	+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
	3238	+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
	3239	+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
	3240	+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
	3241	+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
	3242	+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
	3243	+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
	3244	+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
	3245	+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
	3246	+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
	3247	+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
	3248	+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
	3249	+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
	3250	+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
	3251	+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
	3252	+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
	3253	+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
	3254	+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
	3255	+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
	3256	+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
	3257	+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
	3258	+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
	3259	+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
	3260	+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
	3261	+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
	3262	+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
	3263	+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
	3264	+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
	3265	+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
	3266	+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
	3267	+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
	3268	+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
	3269	+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
	3270	+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
	3271	+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
	3272	+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
	3273	+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
	3274	+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
	3275	+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
	3276	+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
	3277	+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
	3278	+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
	3279	+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
	3280	+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
	3281	+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
	3282	+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
	3283	+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
	3284	+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
	3285	+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
	3286	+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
	3287	+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
	3288	+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
	3289	+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
	3290	+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
	3291	+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
	3292	+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
	3293	+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
	3294	+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
	3295	+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
	3296	+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
	3297	+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
	3298	+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
	3299	+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
	3300	+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
	3301	+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
	3302	+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
	3303	+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
	3304	+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
	3305	+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
	3306	+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
	3307	+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
	3308	+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
	3309	+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
	3310	+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
	3311	+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
	3312	+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
	3313	+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
	3314	+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
	3315	+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
	3316	+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
	3317	+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
	3318	+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
	3319	+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
	3320	+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
	3321	+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
	3322	+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
	3323	+ [CLKID_MALI] = &meson8b_mali.hw,
	3324	+ [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
	3325	+ [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
	3326	+ [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
	3327	+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
	3328	+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
	3329	+ [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
	3330	+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
	3331	+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
	3332	+ [CLKID_VPU] = &meson8b_vpu.hw,
	3333	+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
	3334	+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
	3335	+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
	3336	+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
	3337	+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
	3338	+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
	3339	+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
	3340	+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
	3341	+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
	3342	+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
	3343	+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
	3344	+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
	3345	+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
	3346	+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
	3347	+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
	3348	+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
	3349	+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
	3350	+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
	3351	+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
	3352	+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
	3353	+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
	3354	+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
	3355	+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
888	3356	[CLK_NR_CLKS] = NULL,
889	3357	},
890	3358	.num = CLK_NR_CLKS,
..	..	@@ -978,7 +3446,6 @@
978	3446	&meson8b_mpll1_div,
979	3447	&meson8b_mpll2_div,
980	3448	&meson8b_fixed_pll,
981		- &meson8b_vid_pll,
982	3449	&meson8b_sys_pll,
983	3450	&meson8b_cpu_in_sel,
984	3451	&meson8b_cpu_scale_div,
..	..	@@ -993,59 +3460,183 @@
993	3460	&meson8b_nand_clk_sel,
994	3461	&meson8b_nand_clk_div,
995	3462	&meson8b_nand_clk_gate,
	3463	+ &meson8b_fixed_pll_dco,
	3464	+ &meson8b_hdmi_pll_dco,
	3465	+ &meson8b_sys_pll_dco,
	3466	+ &meson8b_apb_clk_sel,
	3467	+ &meson8b_apb_clk_gate,
	3468	+ &meson8b_periph_clk_sel,
	3469	+ &meson8b_periph_clk_gate,
	3470	+ &meson8b_axi_clk_sel,
	3471	+ &meson8b_axi_clk_gate,
	3472	+ &meson8b_l2_dram_clk_sel,
	3473	+ &meson8b_l2_dram_clk_gate,
	3474	+ &meson8b_hdmi_pll_lvds_out,
	3475	+ &meson8b_hdmi_pll_hdmi_out,
	3476	+ &meson8b_vid_pll_in_sel,
	3477	+ &meson8b_vid_pll_in_en,
	3478	+ &meson8b_vid_pll_pre_div,
	3479	+ &meson8b_vid_pll_post_div,
	3480	+ &meson8b_vid_pll,
	3481	+ &meson8b_vid_pll_final_div,
	3482	+ &meson8b_vclk_in_sel,
	3483	+ &meson8b_vclk_in_en,
	3484	+ &meson8b_vclk_en,
	3485	+ &meson8b_vclk_div1_gate,
	3486	+ &meson8b_vclk_div2_div_gate,
	3487	+ &meson8b_vclk_div4_div_gate,
	3488	+ &meson8b_vclk_div6_div_gate,
	3489	+ &meson8b_vclk_div12_div_gate,
	3490	+ &meson8b_vclk2_in_sel,
	3491	+ &meson8b_vclk2_clk_in_en,
	3492	+ &meson8b_vclk2_clk_en,
	3493	+ &meson8b_vclk2_div1_gate,
	3494	+ &meson8b_vclk2_div2_div_gate,
	3495	+ &meson8b_vclk2_div4_div_gate,
	3496	+ &meson8b_vclk2_div6_div_gate,
	3497	+ &meson8b_vclk2_div12_div_gate,
	3498	+ &meson8b_cts_enct_sel,
	3499	+ &meson8b_cts_enct,
	3500	+ &meson8b_cts_encp_sel,
	3501	+ &meson8b_cts_encp,
	3502	+ &meson8b_cts_enci_sel,
	3503	+ &meson8b_cts_enci,
	3504	+ &meson8b_hdmi_tx_pixel_sel,
	3505	+ &meson8b_hdmi_tx_pixel,
	3506	+ &meson8b_cts_encl_sel,
	3507	+ &meson8b_cts_encl,
	3508	+ &meson8b_cts_vdac0_sel,
	3509	+ &meson8b_cts_vdac0,
	3510	+ &meson8b_hdmi_sys_sel,
	3511	+ &meson8b_hdmi_sys_div,
	3512	+ &meson8b_hdmi_sys,
	3513	+ &meson8b_mali_0_sel,
	3514	+ &meson8b_mali_0_div,
	3515	+ &meson8b_mali_0,
	3516	+ &meson8b_mali_1_sel,
	3517	+ &meson8b_mali_1_div,
	3518	+ &meson8b_mali_1,
	3519	+ &meson8b_mali,
	3520	+ &meson8m2_gp_pll_dco,
	3521	+ &meson8m2_gp_pll,
	3522	+ &meson8b_vpu_0_sel,
	3523	+ &meson8m2_vpu_0_sel,
	3524	+ &meson8b_vpu_0_div,
	3525	+ &meson8b_vpu_0,
	3526	+ &meson8b_vpu_1_sel,
	3527	+ &meson8m2_vpu_1_sel,
	3528	+ &meson8b_vpu_1_div,
	3529	+ &meson8b_vpu_1,
	3530	+ &meson8b_vpu,
	3531	+ &meson8b_vdec_1_sel,
	3532	+ &meson8b_vdec_1_1_div,
	3533	+ &meson8b_vdec_1_1,
	3534	+ &meson8b_vdec_1_2_div,
	3535	+ &meson8b_vdec_1_2,
	3536	+ &meson8b_vdec_1,
	3537	+ &meson8b_vdec_hcodec_sel,
	3538	+ &meson8b_vdec_hcodec_div,
	3539	+ &meson8b_vdec_hcodec,
	3540	+ &meson8b_vdec_2_sel,
	3541	+ &meson8b_vdec_2_div,
	3542	+ &meson8b_vdec_2,
	3543	+ &meson8b_vdec_hevc_sel,
	3544	+ &meson8b_vdec_hevc_div,
	3545	+ &meson8b_vdec_hevc_en,
	3546	+ &meson8b_vdec_hevc,
	3547	+ &meson8b_cts_amclk,
	3548	+ &meson8b_cts_amclk_sel,
	3549	+ &meson8b_cts_amclk_div,
	3550	+ &meson8b_cts_mclk_i958_sel,
	3551	+ &meson8b_cts_mclk_i958_div,
	3552	+ &meson8b_cts_mclk_i958,
	3553	+ &meson8b_cts_i958,
996	3554	};
997	3555
998	3556	static const struct meson8b_clk_reset_line {
999	3557	u32 reg;
1000	3558	u8 bit_idx;
	3559	+ bool active_low;
1001	3560	} meson8b_clk_reset_bits[] = {
1002	3561	[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
1003		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
	3562	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3563	+ .bit_idx = 30,
	3564	+ .active_low = false,
1004	3565	},
1005	3566	[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
1006		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
	3567	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3568	+ .bit_idx = 29,
	3569	+ .active_low = false,
1007	3570	},
1008	3571	[CLKC_RESET_SCU_SOFT_RESET] = {
1009		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
	3572	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3573	+ .bit_idx = 28,
	3574	+ .active_low = false,
1010	3575	},
1011	3576	[CLKC_RESET_CPU3_SOFT_RESET] = {
1012		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
	3577	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3578	+ .bit_idx = 27,
	3579	+ .active_low = false,
1013	3580	},
1014	3581	[CLKC_RESET_CPU2_SOFT_RESET] = {
1015		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
	3582	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3583	+ .bit_idx = 26,
	3584	+ .active_low = false,
1016	3585	},
1017	3586	[CLKC_RESET_CPU1_SOFT_RESET] = {
1018		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
	3587	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3588	+ .bit_idx = 25,
	3589	+ .active_low = false,
1019	3590	},
1020	3591	[CLKC_RESET_CPU0_SOFT_RESET] = {
1021		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
	3592	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3593	+ .bit_idx = 24,
	3594	+ .active_low = false,
1022	3595	},
1023	3596	[CLKC_RESET_A5_GLOBAL_RESET] = {
1024		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
	3597	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3598	+ .bit_idx = 18,
	3599	+ .active_low = false,
1025	3600	},
1026	3601	[CLKC_RESET_A5_AXI_SOFT_RESET] = {
1027		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
	3602	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3603	+ .bit_idx = 17,
	3604	+ .active_low = false,
1028	3605	},
1029	3606	[CLKC_RESET_A5_ABP_SOFT_RESET] = {
1030		- .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
	3607	+ .reg = HHI_SYS_CPU_CLK_CNTL0,
	3608	+ .bit_idx = 16,
	3609	+ .active_low = false,
1031	3610	},
1032	3611	[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
1033		- .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
	3612	+ .reg = HHI_SYS_CPU_CLK_CNTL1,
	3613	+ .bit_idx = 30,
	3614	+ .active_low = false,
1034	3615	},
1035	3616	[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
1036		- .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
	3617	+ .reg = HHI_VID_CLK_CNTL,
	3618	+ .bit_idx = 15,
	3619	+ .active_low = false,
1037	3620	},
1038	3621	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
1039		- .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
	3622	+ .reg = HHI_VID_DIVIDER_CNTL,
	3623	+ .bit_idx = 7,
	3624	+ .active_low = false,
1040	3625	},
1041	3626	[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
1042		- .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
	3627	+ .reg = HHI_VID_DIVIDER_CNTL,
	3628	+ .bit_idx = 3,
	3629	+ .active_low = false,
1043	3630	},
1044	3631	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
1045		- .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
	3632	+ .reg = HHI_VID_DIVIDER_CNTL,
	3633	+ .bit_idx = 1,
	3634	+ .active_low = true,
1046	3635	},
1047	3636	[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
1048		- .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
	3637	+ .reg = HHI_VID_DIVIDER_CNTL,
	3638	+ .bit_idx = 0,
	3639	+ .active_low = true,
1049	3640	},
1050	3641	};
1051	3642
..	..	@@ -1054,23 +3645,22 @@
1054	3645	{
1055	3646	struct meson8b_clk_reset *meson8b_clk_reset =
1056	3647	container_of(rcdev, struct meson8b_clk_reset, reset);
1057		- unsigned long flags;
1058	3648	const struct meson8b_clk_reset_line *reset;
1059		- u32 val;
	3649	+ unsigned int value = 0;
	3650	+ unsigned long flags;
1060	3651
1061	3652	if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
1062	3653	return -EINVAL;
1063	3654
1064	3655	reset = &meson8b_clk_reset_bits[id];
1065	3656
	3657	+ if (assert != reset->active_low)
	3658	+ value = BIT(reset->bit_idx);
	3659	+
1066	3660	spin_lock_irqsave(&meson_clk_lock, flags);
1067	3661
1068		- val = readl(meson8b_clk_reset->base + reset->reg);
1069		- if (assert)
1070		- val \|= BIT(reset->bit_idx);
1071		- else
1072		- val &= ~BIT(reset->bit_idx);
1073		- writel(val, meson8b_clk_reset->base + reset->reg);
	3662	+ regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
	3663	+ BIT(reset->bit_idx), value);
1074	3664
1075	3665	spin_unlock_irqrestore(&meson_clk_lock, flags);
1076	3666
..	..	@@ -1094,74 +3684,80 @@
1094	3684	.deassert = meson8b_clk_reset_deassert,
1095	3685	};
1096	3686
	3687	+struct meson8b_nb_data {
	3688	+ struct notifier_block nb;
	3689	+ struct clk_hw *cpu_clk;
	3690	+};
	3691	+
	3692	+static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
	3693	+ unsigned long event, void *data)
	3694	+{
	3695	+ struct meson8b_nb_data *nb_data =
	3696	+ container_of(nb, struct meson8b_nb_data, nb);
	3697	+ struct clk_hw *parent_clk;
	3698	+ int ret;
	3699	+
	3700	+ switch (event) {
	3701	+ case PRE_RATE_CHANGE:
	3702	+ /* xtal */
	3703	+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
	3704	+ break;
	3705	+
	3706	+ case POST_RATE_CHANGE:
	3707	+ /* cpu_scale_out_sel */
	3708	+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
	3709	+ break;
	3710	+
	3711	+ default:
	3712	+ return NOTIFY_DONE;
	3713	+ }
	3714	+
	3715	+ ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
	3716	+ if (ret)
	3717	+ return notifier_from_errno(ret);
	3718	+
	3719	+ udelay(100);
	3720	+
	3721	+ return NOTIFY_OK;
	3722	+}
	3723	+
	3724	+static struct meson8b_nb_data meson8b_cpu_nb_data = {
	3725	+ .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
	3726	+};
	3727	+
1097	3728	static const struct regmap_config clkc_regmap_config = {
1098	3729	.reg_bits = 32,
1099	3730	.val_bits = 32,
1100	3731	.reg_stride = 4,
1101	3732	};
1102	3733
1103		-static int meson8b_clkc_probe(struct platform_device *pdev)
1104		-{
1105		- int ret, i;
1106		- struct device *dev = &pdev->dev;
1107		- struct regmap *map;
1108		-
1109		- if (!clk_base)
1110		- return -ENXIO;
1111		-
1112		- map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
1113		- if (IS_ERR(map))
1114		- return PTR_ERR(map);
1115		-
1116		- /* Populate regmap for the regmap backed clocks */
1117		- for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
1118		- meson8b_clk_regmaps[i]->map = map;
1119		-
1120		- /*
1121		- * register all clks
1122		- * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
1123		- */
1124		- for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
1125		- /* array might be sparse */
1126		- if (!meson8b_hw_onecell_data.hws[i])
1127		- continue;
1128		-
1129		- ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]);
1130		- if (ret)
1131		- return ret;
1132		- }
1133		-
1134		- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1135		- &meson8b_hw_onecell_data);
1136		-}
1137		-
1138		-static const struct of_device_id meson8b_clkc_match_table[] = {
1139		- { .compatible = "amlogic,meson8-clkc" },
1140		- { .compatible = "amlogic,meson8b-clkc" },
1141		- { .compatible = "amlogic,meson8m2-clkc" },
1142		- { }
1143		-};
1144		-
1145		-static struct platform_driver meson8b_driver = {
1146		- .probe = meson8b_clkc_probe,
1147		- .driver = {
1148		- .name = "meson8b-clkc",
1149		- .of_match_table = meson8b_clkc_match_table,
1150		- },
1151		-};
1152		-
1153		-builtin_platform_driver(meson8b_driver);
1154		-
1155		-static void __init meson8b_clkc_reset_init(struct device_node *np)
	3734	+static void __init meson8b_clkc_init_common(struct device_node *np,
	3735	+ struct clk_hw_onecell_data *clk_hw_onecell_data)
1156	3736	{
1157	3737	struct meson8b_clk_reset *rstc;
1158		- int ret;
	3738	+ struct device_node *parent_np;
	3739	+ const char *notifier_clk_name;
	3740	+ struct clk *notifier_clk;
	3741	+ void __iomem *clk_base;
	3742	+ struct regmap *map;
	3743	+ int i, ret;
1159	3744
1160		- /* Generic clocks, PLLs and some of the reset-bits */
1161		- clk_base = of_iomap(np, 1);
1162		- if (!clk_base) {
1163		- pr_err("%s: Unable to map clk base\n", __func__);
1164		- return;
	3745	+ parent_np = of_get_parent(np);
	3746	+ map = syscon_node_to_regmap(parent_np);
	3747	+ of_node_put(parent_np);
	3748	+ if (IS_ERR(map)) {
	3749	+ pr_info("failed to get HHI regmap - Trying obsolete regs\n");
	3750	+
	3751	+ /* Generic clocks, PLLs and some of the reset-bits */
	3752	+ clk_base = of_iomap(np, 1);
	3753	+ if (!clk_base) {
	3754	+ pr_err("%s: Unable to map clk base\n", __func__);
	3755	+ return;
	3756	+ }
	3757	+
	3758	+ map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
	3759	+ if (IS_ERR(map))
	3760	+ return;
1165	3761	}
1166	3762
1167	3763	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
..	..	@@ -1169,7 +3765,7 @@
1169	3765	return;
1170	3766
1171	3767	/* Reset Controller */
1172		- rstc->base = clk_base;
	3768	+ rstc->regmap = map;
1173	3769	rstc->reset.ops = &meson8b_clk_reset_ops;
1174	3770	rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
1175	3771	rstc->reset.of_node = np;
..	..	@@ -1179,11 +3775,71 @@
1179	3775	__func__, ret);
1180	3776	return;
1181	3777	}
	3778	+
	3779	+ /* Populate regmap for the regmap backed clocks */
	3780	+ for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
	3781	+ meson8b_clk_regmaps[i]->map = map;
	3782	+
	3783	+ /*
	3784	+ * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
	3785	+ * XTAL clock as input.
	3786	+ */
	3787	+ if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
	3788	+ i = CLKID_PLL_FIXED;
	3789	+ else
	3790	+ i = CLKID_XTAL;
	3791	+
	3792	+ /* register all clks */
	3793	+ for (; i < CLK_NR_CLKS; i++) {
	3794	+ /* array might be sparse */
	3795	+ if (!clk_hw_onecell_data->hws[i])
	3796	+ continue;
	3797	+
	3798	+ ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
	3799	+ if (ret)
	3800	+ return;
	3801	+ }
	3802	+
	3803	+ meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
	3804	+
	3805	+ /*
	3806	+ * FIXME we shouldn't program the muxes in notifier handlers. The
	3807	+ * tricky programming sequence will be handled by the forthcoming
	3808	+ * coordinated clock rates mechanism once that feature is released.
	3809	+ */
	3810	+ notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
	3811	+ notifier_clk = __clk_lookup(notifier_clk_name);
	3812	+ ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
	3813	+ if (ret) {
	3814	+ pr_err("%s: failed to register the CPU clock notifier\n",
	3815	+ __func__);
	3816	+ return;
	3817	+ }
	3818	+
	3819	+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
	3820	+ clk_hw_onecell_data);
	3821	+ if (ret)
	3822	+ pr_err("%s: failed to register clock provider\n", __func__);
	3823	+}
	3824	+
	3825	+static void __init meson8_clkc_init(struct device_node *np)
	3826	+{
	3827	+ return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
	3828	+}
	3829	+
	3830	+static void __init meson8b_clkc_init(struct device_node *np)
	3831	+{
	3832	+ return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
	3833	+}
	3834	+
	3835	+static void __init meson8m2_clkc_init(struct device_node *np)
	3836	+{
	3837	+ return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
1182	3838	}
1183	3839
1184	3840	CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
1185		- meson8b_clkc_reset_init);
	3841	+ meson8_clkc_init);
1186	3842	CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
1187		- meson8b_clkc_reset_init);
	3843	+ meson8b_clkc_init);
1188	3844	CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
1189		- meson8b_clkc_reset_init);
	3845	+ meson8m2_clkc_init);