forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2
kernel/drivers/clk/meson/axg.c
....@@ -9,21 +9,27 @@
99 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
1010 */
1111
12
-#include <linux/clk.h>
1312 #include <linux/clk-provider.h>
1413 #include <linux/init.h>
1514 #include <linux/of_device.h>
16
-#include <linux/mfd/syscon.h>
1715 #include <linux/platform_device.h>
18
-#include <linux/regmap.h>
16
+#include <linux/module.h>
1917
20
-#include "clkc.h"
18
+#include "clk-regmap.h"
19
+#include "clk-pll.h"
20
+#include "clk-mpll.h"
2121 #include "axg.h"
22
+#include "meson-eeclk.h"
2223
2324 static DEFINE_SPINLOCK(meson_clk_lock);
2425
25
-static struct clk_regmap axg_fixed_pll = {
26
+static struct clk_regmap axg_fixed_pll_dco = {
2627 .data = &(struct meson_clk_pll_data){
28
+ .en = {
29
+ .reg_off = HHI_MPLL_CNTL,
30
+ .shift = 30,
31
+ .width = 1,
32
+ },
2733 .m = {
2834 .reg_off = HHI_MPLL_CNTL,
2935 .shift = 0,
....@@ -33,11 +39,6 @@
3339 .reg_off = HHI_MPLL_CNTL,
3440 .shift = 9,
3541 .width = 5,
36
- },
37
- .od = {
38
- .reg_off = HHI_MPLL_CNTL,
39
- .shift = 16,
40
- .width = 2,
4142 },
4243 .frac = {
4344 .reg_off = HHI_MPLL_CNTL2,
....@@ -56,15 +57,43 @@
5657 },
5758 },
5859 .hw.init = &(struct clk_init_data){
59
- .name = "fixed_pll",
60
+ .name = "fixed_pll_dco",
6061 .ops = &meson_clk_pll_ro_ops,
61
- .parent_names = (const char *[]){ "xtal" },
62
+ .parent_data = &(const struct clk_parent_data) {
63
+ .fw_name = "xtal",
64
+ },
6265 .num_parents = 1,
6366 },
6467 };
6568
66
-static struct clk_regmap axg_sys_pll = {
69
+static struct clk_regmap axg_fixed_pll = {
70
+ .data = &(struct clk_regmap_div_data){
71
+ .offset = HHI_MPLL_CNTL,
72
+ .shift = 16,
73
+ .width = 2,
74
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
75
+ },
76
+ .hw.init = &(struct clk_init_data){
77
+ .name = "fixed_pll",
78
+ .ops = &clk_regmap_divider_ro_ops,
79
+ .parent_hws = (const struct clk_hw *[]) {
80
+ &axg_fixed_pll_dco.hw
81
+ },
82
+ .num_parents = 1,
83
+ /*
84
+ * This clock won't ever change at runtime so
85
+ * CLK_SET_RATE_PARENT is not required
86
+ */
87
+ },
88
+};
89
+
90
+static struct clk_regmap axg_sys_pll_dco = {
6791 .data = &(struct meson_clk_pll_data){
92
+ .en = {
93
+ .reg_off = HHI_SYS_PLL_CNTL,
94
+ .shift = 30,
95
+ .width = 1,
96
+ },
6897 .m = {
6998 .reg_off = HHI_SYS_PLL_CNTL,
7099 .shift = 0,
....@@ -74,11 +103,6 @@
74103 .reg_off = HHI_SYS_PLL_CNTL,
75104 .shift = 9,
76105 .width = 5,
77
- },
78
- .od = {
79
- .reg_off = HHI_SYS_PLL_CNTL,
80
- .shift = 16,
81
- .width = 2,
82106 },
83107 .l = {
84108 .reg_off = HHI_SYS_PLL_CNTL,
....@@ -92,101 +116,63 @@
92116 },
93117 },
94118 .hw.init = &(struct clk_init_data){
95
- .name = "sys_pll",
119
+ .name = "sys_pll_dco",
96120 .ops = &meson_clk_pll_ro_ops,
97
- .parent_names = (const char *[]){ "xtal" },
121
+ .parent_data = &(const struct clk_parent_data) {
122
+ .fw_name = "xtal",
123
+ },
98124 .num_parents = 1,
99125 },
100126 };
101127
102
-static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
103
- PLL_RATE(240000000, 40, 1, 2),
104
- PLL_RATE(246000000, 41, 1, 2),
105
- PLL_RATE(252000000, 42, 1, 2),
106
- PLL_RATE(258000000, 43, 1, 2),
107
- PLL_RATE(264000000, 44, 1, 2),
108
- PLL_RATE(270000000, 45, 1, 2),
109
- PLL_RATE(276000000, 46, 1, 2),
110
- PLL_RATE(282000000, 47, 1, 2),
111
- PLL_RATE(288000000, 48, 1, 2),
112
- PLL_RATE(294000000, 49, 1, 2),
113
- PLL_RATE(300000000, 50, 1, 2),
114
- PLL_RATE(306000000, 51, 1, 2),
115
- PLL_RATE(312000000, 52, 1, 2),
116
- PLL_RATE(318000000, 53, 1, 2),
117
- PLL_RATE(324000000, 54, 1, 2),
118
- PLL_RATE(330000000, 55, 1, 2),
119
- PLL_RATE(336000000, 56, 1, 2),
120
- PLL_RATE(342000000, 57, 1, 2),
121
- PLL_RATE(348000000, 58, 1, 2),
122
- PLL_RATE(354000000, 59, 1, 2),
123
- PLL_RATE(360000000, 60, 1, 2),
124
- PLL_RATE(366000000, 61, 1, 2),
125
- PLL_RATE(372000000, 62, 1, 2),
126
- PLL_RATE(378000000, 63, 1, 2),
127
- PLL_RATE(384000000, 64, 1, 2),
128
- PLL_RATE(390000000, 65, 1, 3),
129
- PLL_RATE(396000000, 66, 1, 3),
130
- PLL_RATE(402000000, 67, 1, 3),
131
- PLL_RATE(408000000, 68, 1, 3),
132
- PLL_RATE(480000000, 40, 1, 1),
133
- PLL_RATE(492000000, 41, 1, 1),
134
- PLL_RATE(504000000, 42, 1, 1),
135
- PLL_RATE(516000000, 43, 1, 1),
136
- PLL_RATE(528000000, 44, 1, 1),
137
- PLL_RATE(540000000, 45, 1, 1),
138
- PLL_RATE(552000000, 46, 1, 1),
139
- PLL_RATE(564000000, 47, 1, 1),
140
- PLL_RATE(576000000, 48, 1, 1),
141
- PLL_RATE(588000000, 49, 1, 1),
142
- PLL_RATE(600000000, 50, 1, 1),
143
- PLL_RATE(612000000, 51, 1, 1),
144
- PLL_RATE(624000000, 52, 1, 1),
145
- PLL_RATE(636000000, 53, 1, 1),
146
- PLL_RATE(648000000, 54, 1, 1),
147
- PLL_RATE(660000000, 55, 1, 1),
148
- PLL_RATE(672000000, 56, 1, 1),
149
- PLL_RATE(684000000, 57, 1, 1),
150
- PLL_RATE(696000000, 58, 1, 1),
151
- PLL_RATE(708000000, 59, 1, 1),
152
- PLL_RATE(720000000, 60, 1, 1),
153
- PLL_RATE(732000000, 61, 1, 1),
154
- PLL_RATE(744000000, 62, 1, 1),
155
- PLL_RATE(756000000, 63, 1, 1),
156
- PLL_RATE(768000000, 64, 1, 1),
157
- PLL_RATE(780000000, 65, 1, 1),
158
- PLL_RATE(792000000, 66, 1, 1),
159
- PLL_RATE(804000000, 67, 1, 1),
160
- PLL_RATE(816000000, 68, 1, 1),
161
- PLL_RATE(960000000, 40, 1, 0),
162
- PLL_RATE(984000000, 41, 1, 0),
163
- PLL_RATE(1008000000, 42, 1, 0),
164
- PLL_RATE(1032000000, 43, 1, 0),
165
- PLL_RATE(1056000000, 44, 1, 0),
166
- PLL_RATE(1080000000, 45, 1, 0),
167
- PLL_RATE(1104000000, 46, 1, 0),
168
- PLL_RATE(1128000000, 47, 1, 0),
169
- PLL_RATE(1152000000, 48, 1, 0),
170
- PLL_RATE(1176000000, 49, 1, 0),
171
- PLL_RATE(1200000000, 50, 1, 0),
172
- PLL_RATE(1224000000, 51, 1, 0),
173
- PLL_RATE(1248000000, 52, 1, 0),
174
- PLL_RATE(1272000000, 53, 1, 0),
175
- PLL_RATE(1296000000, 54, 1, 0),
176
- PLL_RATE(1320000000, 55, 1, 0),
177
- PLL_RATE(1344000000, 56, 1, 0),
178
- PLL_RATE(1368000000, 57, 1, 0),
179
- PLL_RATE(1392000000, 58, 1, 0),
180
- PLL_RATE(1416000000, 59, 1, 0),
181
- PLL_RATE(1440000000, 60, 1, 0),
182
- PLL_RATE(1464000000, 61, 1, 0),
183
- PLL_RATE(1488000000, 62, 1, 0),
184
- PLL_RATE(1512000000, 63, 1, 0),
185
- PLL_RATE(1536000000, 64, 1, 0),
186
- PLL_RATE(1560000000, 65, 1, 0),
187
- PLL_RATE(1584000000, 66, 1, 0),
188
- PLL_RATE(1608000000, 67, 1, 0),
189
- PLL_RATE(1632000000, 68, 1, 0),
128
+static struct clk_regmap axg_sys_pll = {
129
+ .data = &(struct clk_regmap_div_data){
130
+ .offset = HHI_SYS_PLL_CNTL,
131
+ .shift = 16,
132
+ .width = 2,
133
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
134
+ },
135
+ .hw.init = &(struct clk_init_data){
136
+ .name = "sys_pll",
137
+ .ops = &clk_regmap_divider_ro_ops,
138
+ .parent_hws = (const struct clk_hw *[]) {
139
+ &axg_sys_pll_dco.hw
140
+ },
141
+ .num_parents = 1,
142
+ .flags = CLK_SET_RATE_PARENT,
143
+ },
144
+};
145
+
146
+static const struct pll_params_table axg_gp0_pll_params_table[] = {
147
+ PLL_PARAMS(40, 1),
148
+ PLL_PARAMS(41, 1),
149
+ PLL_PARAMS(42, 1),
150
+ PLL_PARAMS(43, 1),
151
+ PLL_PARAMS(44, 1),
152
+ PLL_PARAMS(45, 1),
153
+ PLL_PARAMS(46, 1),
154
+ PLL_PARAMS(47, 1),
155
+ PLL_PARAMS(48, 1),
156
+ PLL_PARAMS(49, 1),
157
+ PLL_PARAMS(50, 1),
158
+ PLL_PARAMS(51, 1),
159
+ PLL_PARAMS(52, 1),
160
+ PLL_PARAMS(53, 1),
161
+ PLL_PARAMS(54, 1),
162
+ PLL_PARAMS(55, 1),
163
+ PLL_PARAMS(56, 1),
164
+ PLL_PARAMS(57, 1),
165
+ PLL_PARAMS(58, 1),
166
+ PLL_PARAMS(59, 1),
167
+ PLL_PARAMS(60, 1),
168
+ PLL_PARAMS(61, 1),
169
+ PLL_PARAMS(62, 1),
170
+ PLL_PARAMS(63, 1),
171
+ PLL_PARAMS(64, 1),
172
+ PLL_PARAMS(65, 1),
173
+ PLL_PARAMS(66, 1),
174
+ PLL_PARAMS(67, 1),
175
+ PLL_PARAMS(68, 1),
190176 { /* sentinel */ },
191177 };
192178
....@@ -196,11 +182,15 @@
196182 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
197183 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
198184 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
199
- { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
200185 };
201186
202
-static struct clk_regmap axg_gp0_pll = {
187
+static struct clk_regmap axg_gp0_pll_dco = {
203188 .data = &(struct meson_clk_pll_data){
189
+ .en = {
190
+ .reg_off = HHI_GP0_PLL_CNTL,
191
+ .shift = 30,
192
+ .width = 1,
193
+ },
204194 .m = {
205195 .reg_off = HHI_GP0_PLL_CNTL,
206196 .shift = 0,
....@@ -210,11 +200,6 @@
210200 .reg_off = HHI_GP0_PLL_CNTL,
211201 .shift = 9,
212202 .width = 5,
213
- },
214
- .od = {
215
- .reg_off = HHI_GP0_PLL_CNTL,
216
- .shift = 16,
217
- .width = 2,
218203 },
219204 .frac = {
220205 .reg_off = HHI_GP0_PLL_CNTL1,
....@@ -231,15 +216,35 @@
231216 .shift = 29,
232217 .width = 1,
233218 },
234
- .table = axg_gp0_pll_rate_table,
219
+ .table = axg_gp0_pll_params_table,
235220 .init_regs = axg_gp0_init_regs,
236221 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
237222 },
238223 .hw.init = &(struct clk_init_data){
239
- .name = "gp0_pll",
224
+ .name = "gp0_pll_dco",
240225 .ops = &meson_clk_pll_ops,
241
- .parent_names = (const char *[]){ "xtal" },
226
+ .parent_data = &(const struct clk_parent_data) {
227
+ .fw_name = "xtal",
228
+ },
242229 .num_parents = 1,
230
+ },
231
+};
232
+
233
+static struct clk_regmap axg_gp0_pll = {
234
+ .data = &(struct clk_regmap_div_data){
235
+ .offset = HHI_GP0_PLL_CNTL,
236
+ .shift = 16,
237
+ .width = 2,
238
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
239
+ },
240
+ .hw.init = &(struct clk_init_data){
241
+ .name = "gp0_pll",
242
+ .ops = &clk_regmap_divider_ops,
243
+ .parent_hws = (const struct clk_hw *[]) {
244
+ &axg_gp0_pll_dco.hw
245
+ },
246
+ .num_parents = 1,
247
+ .flags = CLK_SET_RATE_PARENT,
243248 },
244249 };
245250
....@@ -249,11 +254,15 @@
249254 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
250255 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
251256 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
252
- { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
253257 };
254258
255
-static struct clk_regmap axg_hifi_pll = {
259
+static struct clk_regmap axg_hifi_pll_dco = {
256260 .data = &(struct meson_clk_pll_data){
261
+ .en = {
262
+ .reg_off = HHI_HIFI_PLL_CNTL,
263
+ .shift = 30,
264
+ .width = 1,
265
+ },
257266 .m = {
258267 .reg_off = HHI_HIFI_PLL_CNTL,
259268 .shift = 0,
....@@ -263,11 +272,6 @@
263272 .reg_off = HHI_HIFI_PLL_CNTL,
264273 .shift = 9,
265274 .width = 5,
266
- },
267
- .od = {
268
- .reg_off = HHI_HIFI_PLL_CNTL,
269
- .shift = 16,
270
- .width = 2,
271275 },
272276 .frac = {
273277 .reg_off = HHI_HIFI_PLL_CNTL5,
....@@ -284,16 +288,36 @@
284288 .shift = 29,
285289 .width = 1,
286290 },
287
- .table = axg_gp0_pll_rate_table,
291
+ .table = axg_gp0_pll_params_table,
288292 .init_regs = axg_hifi_init_regs,
289293 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
290294 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
291295 },
292296 .hw.init = &(struct clk_init_data){
293
- .name = "hifi_pll",
297
+ .name = "hifi_pll_dco",
294298 .ops = &meson_clk_pll_ops,
295
- .parent_names = (const char *[]){ "xtal" },
299
+ .parent_data = &(const struct clk_parent_data) {
300
+ .fw_name = "xtal",
301
+ },
296302 .num_parents = 1,
303
+ },
304
+};
305
+
306
+static struct clk_regmap axg_hifi_pll = {
307
+ .data = &(struct clk_regmap_div_data){
308
+ .offset = HHI_HIFI_PLL_CNTL,
309
+ .shift = 16,
310
+ .width = 2,
311
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
312
+ },
313
+ .hw.init = &(struct clk_init_data){
314
+ .name = "hifi_pll",
315
+ .ops = &clk_regmap_divider_ops,
316
+ .parent_hws = (const struct clk_hw *[]) {
317
+ &axg_hifi_pll_dco.hw
318
+ },
319
+ .num_parents = 1,
320
+ .flags = CLK_SET_RATE_PARENT,
297321 },
298322 };
299323
....@@ -303,7 +327,7 @@
303327 .hw.init = &(struct clk_init_data){
304328 .name = "fclk_div2_div",
305329 .ops = &clk_fixed_factor_ops,
306
- .parent_names = (const char *[]){ "fixed_pll" },
330
+ .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
307331 .num_parents = 1,
308332 },
309333 };
....@@ -316,7 +340,9 @@
316340 .hw.init = &(struct clk_init_data){
317341 .name = "fclk_div2",
318342 .ops = &clk_regmap_gate_ops,
319
- .parent_names = (const char *[]){ "fclk_div2_div" },
343
+ .parent_hws = (const struct clk_hw *[]) {
344
+ &axg_fclk_div2_div.hw
345
+ },
320346 .num_parents = 1,
321347 .flags = CLK_IS_CRITICAL,
322348 },
....@@ -328,7 +354,7 @@
328354 .hw.init = &(struct clk_init_data){
329355 .name = "fclk_div3_div",
330356 .ops = &clk_fixed_factor_ops,
331
- .parent_names = (const char *[]){ "fixed_pll" },
357
+ .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
332358 .num_parents = 1,
333359 },
334360 };
....@@ -341,7 +367,9 @@
341367 .hw.init = &(struct clk_init_data){
342368 .name = "fclk_div3",
343369 .ops = &clk_regmap_gate_ops,
344
- .parent_names = (const char *[]){ "fclk_div3_div" },
370
+ .parent_hws = (const struct clk_hw *[]) {
371
+ &axg_fclk_div3_div.hw
372
+ },
345373 .num_parents = 1,
346374 /*
347375 * FIXME:
....@@ -364,7 +392,7 @@
364392 .hw.init = &(struct clk_init_data){
365393 .name = "fclk_div4_div",
366394 .ops = &clk_fixed_factor_ops,
367
- .parent_names = (const char *[]){ "fixed_pll" },
395
+ .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
368396 .num_parents = 1,
369397 },
370398 };
....@@ -377,7 +405,9 @@
377405 .hw.init = &(struct clk_init_data){
378406 .name = "fclk_div4",
379407 .ops = &clk_regmap_gate_ops,
380
- .parent_names = (const char *[]){ "fclk_div4_div" },
408
+ .parent_hws = (const struct clk_hw *[]) {
409
+ &axg_fclk_div4_div.hw
410
+ },
381411 .num_parents = 1,
382412 },
383413 };
....@@ -388,7 +418,7 @@
388418 .hw.init = &(struct clk_init_data){
389419 .name = "fclk_div5_div",
390420 .ops = &clk_fixed_factor_ops,
391
- .parent_names = (const char *[]){ "fixed_pll" },
421
+ .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
392422 .num_parents = 1,
393423 },
394424 };
....@@ -401,7 +431,9 @@
401431 .hw.init = &(struct clk_init_data){
402432 .name = "fclk_div5",
403433 .ops = &clk_regmap_gate_ops,
404
- .parent_names = (const char *[]){ "fclk_div5_div" },
434
+ .parent_hws = (const struct clk_hw *[]) {
435
+ &axg_fclk_div5_div.hw
436
+ },
405437 .num_parents = 1,
406438 },
407439 };
....@@ -412,7 +444,9 @@
412444 .hw.init = &(struct clk_init_data){
413445 .name = "fclk_div7_div",
414446 .ops = &clk_fixed_factor_ops,
415
- .parent_names = (const char *[]){ "fixed_pll" },
447
+ .parent_hws = (const struct clk_hw *[]) {
448
+ &axg_fixed_pll.hw
449
+ },
416450 .num_parents = 1,
417451 },
418452 };
....@@ -425,7 +459,9 @@
425459 .hw.init = &(struct clk_init_data){
426460 .name = "fclk_div7",
427461 .ops = &clk_regmap_gate_ops,
428
- .parent_names = (const char *[]){ "fclk_div7_div" },
462
+ .parent_hws = (const struct clk_hw *[]) {
463
+ &axg_fclk_div7_div.hw
464
+ },
429465 .num_parents = 1,
430466 },
431467 };
....@@ -439,7 +475,9 @@
439475 .hw.init = &(struct clk_init_data){
440476 .name = "mpll_prediv",
441477 .ops = &clk_regmap_divider_ro_ops,
442
- .parent_names = (const char *[]){ "fixed_pll" },
478
+ .parent_hws = (const struct clk_hw *[]) {
479
+ &axg_fixed_pll.hw
480
+ },
443481 .num_parents = 1,
444482 },
445483 };
....@@ -472,7 +510,9 @@
472510 .hw.init = &(struct clk_init_data){
473511 .name = "mpll0_div",
474512 .ops = &meson_clk_mpll_ops,
475
- .parent_names = (const char *[]){ "mpll_prediv" },
513
+ .parent_hws = (const struct clk_hw *[]) {
514
+ &axg_mpll_prediv.hw
515
+ },
476516 .num_parents = 1,
477517 },
478518 };
....@@ -485,7 +525,9 @@
485525 .hw.init = &(struct clk_init_data){
486526 .name = "mpll0",
487527 .ops = &clk_regmap_gate_ops,
488
- .parent_names = (const char *[]){ "mpll0_div" },
528
+ .parent_hws = (const struct clk_hw *[]) {
529
+ &axg_mpll0_div.hw
530
+ },
489531 .num_parents = 1,
490532 .flags = CLK_SET_RATE_PARENT,
491533 },
....@@ -519,7 +561,9 @@
519561 .hw.init = &(struct clk_init_data){
520562 .name = "mpll1_div",
521563 .ops = &meson_clk_mpll_ops,
522
- .parent_names = (const char *[]){ "mpll_prediv" },
564
+ .parent_hws = (const struct clk_hw *[]) {
565
+ &axg_mpll_prediv.hw
566
+ },
523567 .num_parents = 1,
524568 },
525569 };
....@@ -532,7 +576,9 @@
532576 .hw.init = &(struct clk_init_data){
533577 .name = "mpll1",
534578 .ops = &clk_regmap_gate_ops,
535
- .parent_names = (const char *[]){ "mpll1_div" },
579
+ .parent_hws = (const struct clk_hw *[]) {
580
+ &axg_mpll1_div.hw
581
+ },
536582 .num_parents = 1,
537583 .flags = CLK_SET_RATE_PARENT,
538584 },
....@@ -571,7 +617,9 @@
571617 .hw.init = &(struct clk_init_data){
572618 .name = "mpll2_div",
573619 .ops = &meson_clk_mpll_ops,
574
- .parent_names = (const char *[]){ "mpll_prediv" },
620
+ .parent_hws = (const struct clk_hw *[]) {
621
+ &axg_mpll_prediv.hw
622
+ },
575623 .num_parents = 1,
576624 },
577625 };
....@@ -584,7 +632,9 @@
584632 .hw.init = &(struct clk_init_data){
585633 .name = "mpll2",
586634 .ops = &clk_regmap_gate_ops,
587
- .parent_names = (const char *[]){ "mpll2_div" },
635
+ .parent_hws = (const struct clk_hw *[]) {
636
+ &axg_mpll2_div.hw
637
+ },
588638 .num_parents = 1,
589639 .flags = CLK_SET_RATE_PARENT,
590640 },
....@@ -618,7 +668,9 @@
618668 .hw.init = &(struct clk_init_data){
619669 .name = "mpll3_div",
620670 .ops = &meson_clk_mpll_ops,
621
- .parent_names = (const char *[]){ "mpll_prediv" },
671
+ .parent_hws = (const struct clk_hw *[]) {
672
+ &axg_mpll_prediv.hw
673
+ },
622674 .num_parents = 1,
623675 },
624676 };
....@@ -631,35 +683,39 @@
631683 .hw.init = &(struct clk_init_data){
632684 .name = "mpll3",
633685 .ops = &clk_regmap_gate_ops,
634
- .parent_names = (const char *[]){ "mpll3_div" },
686
+ .parent_hws = (const struct clk_hw *[]) {
687
+ &axg_mpll3_div.hw
688
+ },
635689 .num_parents = 1,
636690 .flags = CLK_SET_RATE_PARENT,
637691 },
638692 };
639693
640
-static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
694
+static const struct pll_params_table axg_pcie_pll_params_table[] = {
641695 {
642
- .rate = 100000000,
643
- .m = 200,
644
- .n = 3,
645
- .od = 1,
646
- .od2 = 3,
696
+ .m = 200,
697
+ .n = 3,
647698 },
648699 { /* sentinel */ },
649700 };
650701
651702 static const struct reg_sequence axg_pcie_init_regs[] = {
652
- { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
653703 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
654704 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
655705 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
656706 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
657707 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
658708 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
709
+ { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
659710 };
660711
661
-static struct clk_regmap axg_pcie_pll = {
712
+static struct clk_regmap axg_pcie_pll_dco = {
662713 .data = &(struct meson_clk_pll_data){
714
+ .en = {
715
+ .reg_off = HHI_PCIE_PLL_CNTL,
716
+ .shift = 30,
717
+ .width = 1,
718
+ },
663719 .m = {
664720 .reg_off = HHI_PCIE_PLL_CNTL,
665721 .shift = 0,
....@@ -669,16 +725,6 @@
669725 .reg_off = HHI_PCIE_PLL_CNTL,
670726 .shift = 9,
671727 .width = 5,
672
- },
673
- .od = {
674
- .reg_off = HHI_PCIE_PLL_CNTL,
675
- .shift = 16,
676
- .width = 2,
677
- },
678
- .od2 = {
679
- .reg_off = HHI_PCIE_PLL_CNTL6,
680
- .shift = 6,
681
- .width = 2,
682728 },
683729 .frac = {
684730 .reg_off = HHI_PCIE_PLL_CNTL1,
....@@ -695,15 +741,53 @@
695741 .shift = 29,
696742 .width = 1,
697743 },
698
- .table = axg_pcie_pll_rate_table,
744
+ .table = axg_pcie_pll_params_table,
699745 .init_regs = axg_pcie_init_regs,
700746 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
701747 },
702748 .hw.init = &(struct clk_init_data){
703
- .name = "pcie_pll",
749
+ .name = "pcie_pll_dco",
704750 .ops = &meson_clk_pll_ops,
705
- .parent_names = (const char *[]){ "xtal" },
751
+ .parent_data = &(const struct clk_parent_data) {
752
+ .fw_name = "xtal",
753
+ },
706754 .num_parents = 1,
755
+ },
756
+};
757
+
758
+static struct clk_regmap axg_pcie_pll_od = {
759
+ .data = &(struct clk_regmap_div_data){
760
+ .offset = HHI_PCIE_PLL_CNTL,
761
+ .shift = 16,
762
+ .width = 2,
763
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
764
+ },
765
+ .hw.init = &(struct clk_init_data){
766
+ .name = "pcie_pll_od",
767
+ .ops = &clk_regmap_divider_ops,
768
+ .parent_hws = (const struct clk_hw *[]) {
769
+ &axg_pcie_pll_dco.hw
770
+ },
771
+ .num_parents = 1,
772
+ .flags = CLK_SET_RATE_PARENT,
773
+ },
774
+};
775
+
776
+static struct clk_regmap axg_pcie_pll = {
777
+ .data = &(struct clk_regmap_div_data){
778
+ .offset = HHI_PCIE_PLL_CNTL6,
779
+ .shift = 6,
780
+ .width = 2,
781
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
782
+ },
783
+ .hw.init = &(struct clk_init_data){
784
+ .name = "pcie_pll",
785
+ .ops = &clk_regmap_divider_ops,
786
+ .parent_hws = (const struct clk_hw *[]) {
787
+ &axg_pcie_pll_od.hw
788
+ },
789
+ .num_parents = 1,
790
+ .flags = CLK_SET_RATE_PARENT,
707791 },
708792 };
709793
....@@ -718,7 +802,7 @@
718802 .hw.init = &(struct clk_init_data){
719803 .name = "pcie_mux",
720804 .ops = &clk_regmap_mux_ops,
721
- .parent_names = (const char *[]){ "pcie_pll" },
805
+ .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
722806 .num_parents = 1,
723807 .flags = CLK_SET_RATE_PARENT,
724808 },
....@@ -735,7 +819,7 @@
735819 .hw.init = &(struct clk_init_data){
736820 .name = "pcie_ref",
737821 .ops = &clk_regmap_mux_ops,
738
- .parent_names = (const char *[]){ "pcie_mux" },
822
+ .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
739823 .num_parents = 1,
740824 .flags = CLK_SET_RATE_PARENT,
741825 },
....@@ -749,7 +833,7 @@
749833 .hw.init = &(struct clk_init_data) {
750834 .name = "pcie_cml_en0",
751835 .ops = &clk_regmap_gate_ops,
752
- .parent_names = (const char *[]){ "pcie_ref" },
836
+ .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
753837 .num_parents = 1,
754838 .flags = CLK_SET_RATE_PARENT,
755839
....@@ -764,16 +848,21 @@
764848 .hw.init = &(struct clk_init_data) {
765849 .name = "pcie_cml_en1",
766850 .ops = &clk_regmap_gate_ops,
767
- .parent_names = (const char *[]){ "pcie_ref" },
851
+ .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
768852 .num_parents = 1,
769853 .flags = CLK_SET_RATE_PARENT,
770854 },
771855 };
772856
773857 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
774
-static const char * const clk81_parent_names[] = {
775
- "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
776
- "fclk_div3", "fclk_div5"
858
+static const struct clk_parent_data clk81_parent_data[] = {
859
+ { .fw_name = "xtal", },
860
+ { .hw = &axg_fclk_div7.hw },
861
+ { .hw = &axg_mpll1.hw },
862
+ { .hw = &axg_mpll2.hw },
863
+ { .hw = &axg_fclk_div4.hw },
864
+ { .hw = &axg_fclk_div3.hw },
865
+ { .hw = &axg_fclk_div5.hw },
777866 };
778867
779868 static struct clk_regmap axg_mpeg_clk_sel = {
....@@ -786,8 +875,8 @@
786875 .hw.init = &(struct clk_init_data){
787876 .name = "mpeg_clk_sel",
788877 .ops = &clk_regmap_mux_ro_ops,
789
- .parent_names = clk81_parent_names,
790
- .num_parents = ARRAY_SIZE(clk81_parent_names),
878
+ .parent_data = clk81_parent_data,
879
+ .num_parents = ARRAY_SIZE(clk81_parent_data),
791880 },
792881 };
793882
....@@ -800,7 +889,9 @@
800889 .hw.init = &(struct clk_init_data){
801890 .name = "mpeg_clk_div",
802891 .ops = &clk_regmap_divider_ops,
803
- .parent_names = (const char *[]){ "mpeg_clk_sel" },
892
+ .parent_hws = (const struct clk_hw *[]) {
893
+ &axg_mpeg_clk_sel.hw
894
+ },
804895 .num_parents = 1,
805896 .flags = CLK_SET_RATE_PARENT,
806897 },
....@@ -814,15 +905,20 @@
814905 .hw.init = &(struct clk_init_data){
815906 .name = "clk81",
816907 .ops = &clk_regmap_gate_ops,
817
- .parent_names = (const char *[]){ "mpeg_clk_div" },
908
+ .parent_hws = (const struct clk_hw *[]) {
909
+ &axg_mpeg_clk_div.hw
910
+ },
818911 .num_parents = 1,
819912 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
820913 },
821914 };
822915
823
-static const char * const axg_sd_emmc_clk0_parent_names[] = {
824
- "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
825
-
916
+static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
917
+ { .fw_name = "xtal", },
918
+ { .hw = &axg_fclk_div2.hw },
919
+ { .hw = &axg_fclk_div3.hw },
920
+ { .hw = &axg_fclk_div5.hw },
921
+ { .hw = &axg_fclk_div7.hw },
826922 /*
827923 * Following these parent clocks, we should also have had mpll2, mpll3
828924 * and gp0_pll but these clocks are too precious to be used here. All
....@@ -841,8 +937,8 @@
841937 .hw.init = &(struct clk_init_data) {
842938 .name = "sd_emmc_b_clk0_sel",
843939 .ops = &clk_regmap_mux_ops,
844
- .parent_names = axg_sd_emmc_clk0_parent_names,
845
- .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
940
+ .parent_data = axg_sd_emmc_clk0_parent_data,
941
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
846942 .flags = CLK_SET_RATE_PARENT,
847943 },
848944 };
....@@ -857,7 +953,9 @@
857953 .hw.init = &(struct clk_init_data) {
858954 .name = "sd_emmc_b_clk0_div",
859955 .ops = &clk_regmap_divider_ops,
860
- .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
956
+ .parent_hws = (const struct clk_hw *[]) {
957
+ &axg_sd_emmc_b_clk0_sel.hw
958
+ },
861959 .num_parents = 1,
862960 .flags = CLK_SET_RATE_PARENT,
863961 },
....@@ -871,7 +969,9 @@
871969 .hw.init = &(struct clk_init_data){
872970 .name = "sd_emmc_b_clk0",
873971 .ops = &clk_regmap_gate_ops,
874
- .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
972
+ .parent_hws = (const struct clk_hw *[]) {
973
+ &axg_sd_emmc_b_clk0_div.hw
974
+ },
875975 .num_parents = 1,
876976 .flags = CLK_SET_RATE_PARENT,
877977 },
....@@ -887,8 +987,8 @@
887987 .hw.init = &(struct clk_init_data) {
888988 .name = "sd_emmc_c_clk0_sel",
889989 .ops = &clk_regmap_mux_ops,
890
- .parent_names = axg_sd_emmc_clk0_parent_names,
891
- .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
990
+ .parent_data = axg_sd_emmc_clk0_parent_data,
991
+ .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
892992 .flags = CLK_SET_RATE_PARENT,
893993 },
894994 };
....@@ -903,7 +1003,9 @@
9031003 .hw.init = &(struct clk_init_data) {
9041004 .name = "sd_emmc_c_clk0_div",
9051005 .ops = &clk_regmap_divider_ops,
906
- .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1006
+ .parent_hws = (const struct clk_hw *[]) {
1007
+ &axg_sd_emmc_c_clk0_sel.hw
1008
+ },
9071009 .num_parents = 1,
9081010 .flags = CLK_SET_RATE_PARENT,
9091011 },
....@@ -917,7 +1019,9 @@
9171019 .hw.init = &(struct clk_init_data){
9181020 .name = "sd_emmc_c_clk0",
9191021 .ops = &clk_regmap_gate_ops,
920
- .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1022
+ .parent_hws = (const struct clk_hw *[]) {
1023
+ &axg_sd_emmc_c_clk0_div.hw
1024
+ },
9211025 .num_parents = 1,
9221026 .flags = CLK_SET_RATE_PARENT,
9231027 },
....@@ -925,9 +1029,18 @@
9251029
9261030 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9271031 9, 10, 11, 13, 14, };
928
-static const char * const gen_clk_parent_names[] = {
929
- "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
930
- "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
1032
+static const struct clk_parent_data gen_clk_parent_data[] = {
1033
+ { .fw_name = "xtal", },
1034
+ { .hw = &axg_hifi_pll.hw },
1035
+ { .hw = &axg_mpll0.hw },
1036
+ { .hw = &axg_mpll1.hw },
1037
+ { .hw = &axg_mpll2.hw },
1038
+ { .hw = &axg_mpll3.hw },
1039
+ { .hw = &axg_fclk_div4.hw },
1040
+ { .hw = &axg_fclk_div3.hw },
1041
+ { .hw = &axg_fclk_div5.hw },
1042
+ { .hw = &axg_fclk_div7.hw },
1043
+ { .hw = &axg_gp0_pll.hw },
9311044 };
9321045
9331046 static struct clk_regmap axg_gen_clk_sel = {
....@@ -946,8 +1059,8 @@
9461059 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
9471060 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
9481061 */
949
- .parent_names = gen_clk_parent_names,
950
- .num_parents = ARRAY_SIZE(gen_clk_parent_names),
1062
+ .parent_data = gen_clk_parent_data,
1063
+ .num_parents = ARRAY_SIZE(gen_clk_parent_data),
9511064 },
9521065 };
9531066
....@@ -960,7 +1073,9 @@
9601073 .hw.init = &(struct clk_init_data){
9611074 .name = "gen_clk_div",
9621075 .ops = &clk_regmap_divider_ops,
963
- .parent_names = (const char *[]){ "gen_clk_sel" },
1076
+ .parent_hws = (const struct clk_hw *[]) {
1077
+ &axg_gen_clk_sel.hw
1078
+ },
9641079 .num_parents = 1,
9651080 .flags = CLK_SET_RATE_PARENT,
9661081 },
....@@ -974,11 +1089,16 @@
9741089 .hw.init = &(struct clk_init_data){
9751090 .name = "gen_clk",
9761091 .ops = &clk_regmap_gate_ops,
977
- .parent_names = (const char *[]){ "gen_clk_div" },
1092
+ .parent_hws = (const struct clk_hw *[]) {
1093
+ &axg_gen_clk_div.hw
1094
+ },
9781095 .num_parents = 1,
9791096 .flags = CLK_SET_RATE_PARENT,
9801097 },
9811098 };
1099
+
1100
+#define MESON_GATE(_name, _reg, _bit) \
1101
+ MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
9821102
9831103 /* Everything Else (EE) domain gates */
9841104 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
....@@ -1121,6 +1241,12 @@
11211241 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
11221242 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
11231243 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1244
+ [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1245
+ [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1246
+ [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1247
+ [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1248
+ [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1249
+ [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
11241250 [NR_CLKS] = NULL,
11251251 },
11261252 .num = NR_CLKS,
....@@ -1199,6 +1325,8 @@
11991325 &axg_fclk_div4,
12001326 &axg_fclk_div5,
12011327 &axg_fclk_div7,
1328
+ &axg_pcie_pll_dco,
1329
+ &axg_pcie_pll_od,
12021330 &axg_pcie_pll,
12031331 &axg_pcie_mux,
12041332 &axg_pcie_ref,
....@@ -1208,52 +1336,34 @@
12081336 &axg_gen_clk_sel,
12091337 &axg_gen_clk_div,
12101338 &axg_gen_clk,
1339
+ &axg_fixed_pll_dco,
1340
+ &axg_sys_pll_dco,
1341
+ &axg_gp0_pll_dco,
1342
+ &axg_hifi_pll_dco,
1343
+ &axg_pcie_pll_dco,
1344
+ &axg_pcie_pll_od,
12111345 };
1346
+
1347
+static const struct meson_eeclkc_data axg_clkc_data = {
1348
+ .regmap_clks = axg_clk_regmaps,
1349
+ .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1350
+ .hw_onecell_data = &axg_hw_onecell_data,
1351
+};
1352
+
12121353
12131354 static const struct of_device_id clkc_match_table[] = {
1214
- { .compatible = "amlogic,axg-clkc" },
1355
+ { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
12151356 {}
12161357 };
1217
-
1218
-static int axg_clkc_probe(struct platform_device *pdev)
1219
-{
1220
- struct device *dev = &pdev->dev;
1221
- struct regmap *map;
1222
- int ret, i;
1223
-
1224
- /* Get the hhi system controller node if available */
1225
- map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1226
- if (IS_ERR(map)) {
1227
- dev_err(dev, "failed to get HHI regmap\n");
1228
- return PTR_ERR(map);
1229
- }
1230
-
1231
- /* Populate regmap for the regmap backed clocks */
1232
- for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
1233
- axg_clk_regmaps[i]->map = map;
1234
-
1235
- for (i = 0; i < axg_hw_onecell_data.num; i++) {
1236
- /* array might be sparse */
1237
- if (!axg_hw_onecell_data.hws[i])
1238
- continue;
1239
-
1240
- ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
1241
- if (ret) {
1242
- dev_err(dev, "Clock registration failed\n");
1243
- return ret;
1244
- }
1245
- }
1246
-
1247
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1248
- &axg_hw_onecell_data);
1249
-}
1358
+MODULE_DEVICE_TABLE(of, clkc_match_table);
12501359
12511360 static struct platform_driver axg_driver = {
1252
- .probe = axg_clkc_probe,
1361
+ .probe = meson_eeclkc_probe,
12531362 .driver = {
12541363 .name = "axg-clkc",
12551364 .of_match_table = clkc_match_table,
12561365 },
12571366 };
12581367
1259
-builtin_platform_driver(axg_driver);
1368
+module_platform_driver(axg_driver);
1369
+MODULE_LICENSE("GPL v2");