.. | .. |
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9 | 9 | * Author: Qiufang Dai <qiufang.dai@amlogic.com> |
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10 | 10 | */ |
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11 | 11 | |
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12 | | -#include <linux/clk.h> |
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13 | 12 | #include <linux/clk-provider.h> |
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14 | 13 | #include <linux/init.h> |
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15 | 14 | #include <linux/of_device.h> |
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16 | | -#include <linux/mfd/syscon.h> |
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17 | 15 | #include <linux/platform_device.h> |
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18 | | -#include <linux/regmap.h> |
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| 16 | +#include <linux/module.h> |
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19 | 17 | |
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20 | | -#include "clkc.h" |
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| 18 | +#include "clk-regmap.h" |
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| 19 | +#include "clk-pll.h" |
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| 20 | +#include "clk-mpll.h" |
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21 | 21 | #include "axg.h" |
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| 22 | +#include "meson-eeclk.h" |
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22 | 23 | |
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23 | 24 | static DEFINE_SPINLOCK(meson_clk_lock); |
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24 | 25 | |
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25 | | -static struct clk_regmap axg_fixed_pll = { |
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| 26 | +static struct clk_regmap axg_fixed_pll_dco = { |
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26 | 27 | .data = &(struct meson_clk_pll_data){ |
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| 28 | + .en = { |
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| 29 | + .reg_off = HHI_MPLL_CNTL, |
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| 30 | + .shift = 30, |
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| 31 | + .width = 1, |
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| 32 | + }, |
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27 | 33 | .m = { |
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28 | 34 | .reg_off = HHI_MPLL_CNTL, |
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29 | 35 | .shift = 0, |
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.. | .. |
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33 | 39 | .reg_off = HHI_MPLL_CNTL, |
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34 | 40 | .shift = 9, |
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35 | 41 | .width = 5, |
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36 | | - }, |
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37 | | - .od = { |
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38 | | - .reg_off = HHI_MPLL_CNTL, |
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39 | | - .shift = 16, |
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40 | | - .width = 2, |
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41 | 42 | }, |
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42 | 43 | .frac = { |
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43 | 44 | .reg_off = HHI_MPLL_CNTL2, |
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.. | .. |
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56 | 57 | }, |
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57 | 58 | }, |
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58 | 59 | .hw.init = &(struct clk_init_data){ |
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59 | | - .name = "fixed_pll", |
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| 60 | + .name = "fixed_pll_dco", |
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60 | 61 | .ops = &meson_clk_pll_ro_ops, |
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61 | | - .parent_names = (const char *[]){ "xtal" }, |
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| 62 | + .parent_data = &(const struct clk_parent_data) { |
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| 63 | + .fw_name = "xtal", |
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| 64 | + }, |
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62 | 65 | .num_parents = 1, |
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63 | 66 | }, |
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64 | 67 | }; |
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65 | 68 | |
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66 | | -static struct clk_regmap axg_sys_pll = { |
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| 69 | +static struct clk_regmap axg_fixed_pll = { |
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| 70 | + .data = &(struct clk_regmap_div_data){ |
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| 71 | + .offset = HHI_MPLL_CNTL, |
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| 72 | + .shift = 16, |
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| 73 | + .width = 2, |
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| 74 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
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| 75 | + }, |
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| 76 | + .hw.init = &(struct clk_init_data){ |
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| 77 | + .name = "fixed_pll", |
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| 78 | + .ops = &clk_regmap_divider_ro_ops, |
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| 79 | + .parent_hws = (const struct clk_hw *[]) { |
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| 80 | + &axg_fixed_pll_dco.hw |
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| 81 | + }, |
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| 82 | + .num_parents = 1, |
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| 83 | + /* |
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| 84 | + * This clock won't ever change at runtime so |
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| 85 | + * CLK_SET_RATE_PARENT is not required |
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| 86 | + */ |
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| 87 | + }, |
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| 88 | +}; |
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| 89 | + |
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| 90 | +static struct clk_regmap axg_sys_pll_dco = { |
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67 | 91 | .data = &(struct meson_clk_pll_data){ |
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| 92 | + .en = { |
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| 93 | + .reg_off = HHI_SYS_PLL_CNTL, |
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| 94 | + .shift = 30, |
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| 95 | + .width = 1, |
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| 96 | + }, |
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68 | 97 | .m = { |
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69 | 98 | .reg_off = HHI_SYS_PLL_CNTL, |
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70 | 99 | .shift = 0, |
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.. | .. |
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74 | 103 | .reg_off = HHI_SYS_PLL_CNTL, |
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75 | 104 | .shift = 9, |
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76 | 105 | .width = 5, |
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77 | | - }, |
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78 | | - .od = { |
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79 | | - .reg_off = HHI_SYS_PLL_CNTL, |
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80 | | - .shift = 16, |
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81 | | - .width = 2, |
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82 | 106 | }, |
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83 | 107 | .l = { |
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84 | 108 | .reg_off = HHI_SYS_PLL_CNTL, |
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.. | .. |
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92 | 116 | }, |
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93 | 117 | }, |
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94 | 118 | .hw.init = &(struct clk_init_data){ |
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95 | | - .name = "sys_pll", |
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| 119 | + .name = "sys_pll_dco", |
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96 | 120 | .ops = &meson_clk_pll_ro_ops, |
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97 | | - .parent_names = (const char *[]){ "xtal" }, |
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| 121 | + .parent_data = &(const struct clk_parent_data) { |
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| 122 | + .fw_name = "xtal", |
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| 123 | + }, |
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98 | 124 | .num_parents = 1, |
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99 | 125 | }, |
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100 | 126 | }; |
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101 | 127 | |
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102 | | -static const struct pll_rate_table axg_gp0_pll_rate_table[] = { |
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103 | | - PLL_RATE(240000000, 40, 1, 2), |
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104 | | - PLL_RATE(246000000, 41, 1, 2), |
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105 | | - PLL_RATE(252000000, 42, 1, 2), |
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106 | | - PLL_RATE(258000000, 43, 1, 2), |
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107 | | - PLL_RATE(264000000, 44, 1, 2), |
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108 | | - PLL_RATE(270000000, 45, 1, 2), |
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109 | | - PLL_RATE(276000000, 46, 1, 2), |
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110 | | - PLL_RATE(282000000, 47, 1, 2), |
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111 | | - PLL_RATE(288000000, 48, 1, 2), |
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112 | | - PLL_RATE(294000000, 49, 1, 2), |
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113 | | - PLL_RATE(300000000, 50, 1, 2), |
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114 | | - PLL_RATE(306000000, 51, 1, 2), |
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115 | | - PLL_RATE(312000000, 52, 1, 2), |
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116 | | - PLL_RATE(318000000, 53, 1, 2), |
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117 | | - PLL_RATE(324000000, 54, 1, 2), |
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118 | | - PLL_RATE(330000000, 55, 1, 2), |
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119 | | - PLL_RATE(336000000, 56, 1, 2), |
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120 | | - PLL_RATE(342000000, 57, 1, 2), |
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121 | | - PLL_RATE(348000000, 58, 1, 2), |
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122 | | - PLL_RATE(354000000, 59, 1, 2), |
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123 | | - PLL_RATE(360000000, 60, 1, 2), |
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124 | | - PLL_RATE(366000000, 61, 1, 2), |
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125 | | - PLL_RATE(372000000, 62, 1, 2), |
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126 | | - PLL_RATE(378000000, 63, 1, 2), |
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127 | | - PLL_RATE(384000000, 64, 1, 2), |
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128 | | - PLL_RATE(390000000, 65, 1, 3), |
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129 | | - PLL_RATE(396000000, 66, 1, 3), |
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130 | | - PLL_RATE(402000000, 67, 1, 3), |
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131 | | - PLL_RATE(408000000, 68, 1, 3), |
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132 | | - PLL_RATE(480000000, 40, 1, 1), |
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133 | | - PLL_RATE(492000000, 41, 1, 1), |
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134 | | - PLL_RATE(504000000, 42, 1, 1), |
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135 | | - PLL_RATE(516000000, 43, 1, 1), |
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136 | | - PLL_RATE(528000000, 44, 1, 1), |
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137 | | - PLL_RATE(540000000, 45, 1, 1), |
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138 | | - PLL_RATE(552000000, 46, 1, 1), |
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139 | | - PLL_RATE(564000000, 47, 1, 1), |
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140 | | - PLL_RATE(576000000, 48, 1, 1), |
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141 | | - PLL_RATE(588000000, 49, 1, 1), |
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142 | | - PLL_RATE(600000000, 50, 1, 1), |
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143 | | - PLL_RATE(612000000, 51, 1, 1), |
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144 | | - PLL_RATE(624000000, 52, 1, 1), |
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145 | | - PLL_RATE(636000000, 53, 1, 1), |
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146 | | - PLL_RATE(648000000, 54, 1, 1), |
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147 | | - PLL_RATE(660000000, 55, 1, 1), |
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148 | | - PLL_RATE(672000000, 56, 1, 1), |
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149 | | - PLL_RATE(684000000, 57, 1, 1), |
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150 | | - PLL_RATE(696000000, 58, 1, 1), |
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151 | | - PLL_RATE(708000000, 59, 1, 1), |
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152 | | - PLL_RATE(720000000, 60, 1, 1), |
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153 | | - PLL_RATE(732000000, 61, 1, 1), |
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154 | | - PLL_RATE(744000000, 62, 1, 1), |
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155 | | - PLL_RATE(756000000, 63, 1, 1), |
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156 | | - PLL_RATE(768000000, 64, 1, 1), |
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157 | | - PLL_RATE(780000000, 65, 1, 1), |
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158 | | - PLL_RATE(792000000, 66, 1, 1), |
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159 | | - PLL_RATE(804000000, 67, 1, 1), |
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160 | | - PLL_RATE(816000000, 68, 1, 1), |
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161 | | - PLL_RATE(960000000, 40, 1, 0), |
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162 | | - PLL_RATE(984000000, 41, 1, 0), |
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163 | | - PLL_RATE(1008000000, 42, 1, 0), |
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164 | | - PLL_RATE(1032000000, 43, 1, 0), |
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165 | | - PLL_RATE(1056000000, 44, 1, 0), |
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166 | | - PLL_RATE(1080000000, 45, 1, 0), |
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167 | | - PLL_RATE(1104000000, 46, 1, 0), |
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168 | | - PLL_RATE(1128000000, 47, 1, 0), |
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169 | | - PLL_RATE(1152000000, 48, 1, 0), |
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170 | | - PLL_RATE(1176000000, 49, 1, 0), |
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171 | | - PLL_RATE(1200000000, 50, 1, 0), |
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172 | | - PLL_RATE(1224000000, 51, 1, 0), |
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173 | | - PLL_RATE(1248000000, 52, 1, 0), |
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174 | | - PLL_RATE(1272000000, 53, 1, 0), |
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175 | | - PLL_RATE(1296000000, 54, 1, 0), |
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176 | | - PLL_RATE(1320000000, 55, 1, 0), |
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177 | | - PLL_RATE(1344000000, 56, 1, 0), |
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178 | | - PLL_RATE(1368000000, 57, 1, 0), |
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179 | | - PLL_RATE(1392000000, 58, 1, 0), |
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180 | | - PLL_RATE(1416000000, 59, 1, 0), |
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181 | | - PLL_RATE(1440000000, 60, 1, 0), |
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182 | | - PLL_RATE(1464000000, 61, 1, 0), |
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183 | | - PLL_RATE(1488000000, 62, 1, 0), |
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184 | | - PLL_RATE(1512000000, 63, 1, 0), |
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185 | | - PLL_RATE(1536000000, 64, 1, 0), |
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186 | | - PLL_RATE(1560000000, 65, 1, 0), |
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187 | | - PLL_RATE(1584000000, 66, 1, 0), |
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188 | | - PLL_RATE(1608000000, 67, 1, 0), |
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189 | | - PLL_RATE(1632000000, 68, 1, 0), |
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| 128 | +static struct clk_regmap axg_sys_pll = { |
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| 129 | + .data = &(struct clk_regmap_div_data){ |
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| 130 | + .offset = HHI_SYS_PLL_CNTL, |
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| 131 | + .shift = 16, |
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| 132 | + .width = 2, |
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| 133 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
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| 134 | + }, |
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| 135 | + .hw.init = &(struct clk_init_data){ |
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| 136 | + .name = "sys_pll", |
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| 137 | + .ops = &clk_regmap_divider_ro_ops, |
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| 138 | + .parent_hws = (const struct clk_hw *[]) { |
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| 139 | + &axg_sys_pll_dco.hw |
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| 140 | + }, |
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| 141 | + .num_parents = 1, |
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| 142 | + .flags = CLK_SET_RATE_PARENT, |
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| 143 | + }, |
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| 144 | +}; |
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| 145 | + |
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| 146 | +static const struct pll_params_table axg_gp0_pll_params_table[] = { |
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| 147 | + PLL_PARAMS(40, 1), |
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| 148 | + PLL_PARAMS(41, 1), |
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| 149 | + PLL_PARAMS(42, 1), |
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| 150 | + PLL_PARAMS(43, 1), |
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| 151 | + PLL_PARAMS(44, 1), |
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| 152 | + PLL_PARAMS(45, 1), |
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| 153 | + PLL_PARAMS(46, 1), |
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| 154 | + PLL_PARAMS(47, 1), |
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| 155 | + PLL_PARAMS(48, 1), |
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| 156 | + PLL_PARAMS(49, 1), |
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| 157 | + PLL_PARAMS(50, 1), |
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| 158 | + PLL_PARAMS(51, 1), |
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| 159 | + PLL_PARAMS(52, 1), |
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| 160 | + PLL_PARAMS(53, 1), |
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| 161 | + PLL_PARAMS(54, 1), |
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| 162 | + PLL_PARAMS(55, 1), |
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| 163 | + PLL_PARAMS(56, 1), |
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| 164 | + PLL_PARAMS(57, 1), |
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| 165 | + PLL_PARAMS(58, 1), |
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| 166 | + PLL_PARAMS(59, 1), |
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| 167 | + PLL_PARAMS(60, 1), |
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| 168 | + PLL_PARAMS(61, 1), |
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| 169 | + PLL_PARAMS(62, 1), |
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| 170 | + PLL_PARAMS(63, 1), |
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| 171 | + PLL_PARAMS(64, 1), |
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| 172 | + PLL_PARAMS(65, 1), |
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| 173 | + PLL_PARAMS(66, 1), |
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| 174 | + PLL_PARAMS(67, 1), |
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| 175 | + PLL_PARAMS(68, 1), |
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190 | 176 | { /* sentinel */ }, |
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191 | 177 | }; |
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192 | 178 | |
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.. | .. |
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196 | 182 | { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, |
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197 | 183 | { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, |
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198 | 184 | { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, |
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199 | | - { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, |
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200 | 185 | }; |
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201 | 186 | |
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202 | | -static struct clk_regmap axg_gp0_pll = { |
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| 187 | +static struct clk_regmap axg_gp0_pll_dco = { |
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203 | 188 | .data = &(struct meson_clk_pll_data){ |
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| 189 | + .en = { |
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| 190 | + .reg_off = HHI_GP0_PLL_CNTL, |
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| 191 | + .shift = 30, |
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| 192 | + .width = 1, |
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| 193 | + }, |
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204 | 194 | .m = { |
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205 | 195 | .reg_off = HHI_GP0_PLL_CNTL, |
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206 | 196 | .shift = 0, |
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.. | .. |
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210 | 200 | .reg_off = HHI_GP0_PLL_CNTL, |
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211 | 201 | .shift = 9, |
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212 | 202 | .width = 5, |
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213 | | - }, |
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214 | | - .od = { |
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215 | | - .reg_off = HHI_GP0_PLL_CNTL, |
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216 | | - .shift = 16, |
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217 | | - .width = 2, |
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218 | 203 | }, |
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219 | 204 | .frac = { |
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220 | 205 | .reg_off = HHI_GP0_PLL_CNTL1, |
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.. | .. |
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231 | 216 | .shift = 29, |
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232 | 217 | .width = 1, |
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233 | 218 | }, |
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234 | | - .table = axg_gp0_pll_rate_table, |
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| 219 | + .table = axg_gp0_pll_params_table, |
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235 | 220 | .init_regs = axg_gp0_init_regs, |
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236 | 221 | .init_count = ARRAY_SIZE(axg_gp0_init_regs), |
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237 | 222 | }, |
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238 | 223 | .hw.init = &(struct clk_init_data){ |
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239 | | - .name = "gp0_pll", |
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| 224 | + .name = "gp0_pll_dco", |
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240 | 225 | .ops = &meson_clk_pll_ops, |
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241 | | - .parent_names = (const char *[]){ "xtal" }, |
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| 226 | + .parent_data = &(const struct clk_parent_data) { |
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| 227 | + .fw_name = "xtal", |
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| 228 | + }, |
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242 | 229 | .num_parents = 1, |
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| 230 | + }, |
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| 231 | +}; |
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| 232 | + |
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| 233 | +static struct clk_regmap axg_gp0_pll = { |
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| 234 | + .data = &(struct clk_regmap_div_data){ |
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| 235 | + .offset = HHI_GP0_PLL_CNTL, |
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| 236 | + .shift = 16, |
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| 237 | + .width = 2, |
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| 238 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
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| 239 | + }, |
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| 240 | + .hw.init = &(struct clk_init_data){ |
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| 241 | + .name = "gp0_pll", |
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| 242 | + .ops = &clk_regmap_divider_ops, |
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| 243 | + .parent_hws = (const struct clk_hw *[]) { |
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| 244 | + &axg_gp0_pll_dco.hw |
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| 245 | + }, |
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| 246 | + .num_parents = 1, |
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| 247 | + .flags = CLK_SET_RATE_PARENT, |
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243 | 248 | }, |
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244 | 249 | }; |
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245 | 250 | |
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.. | .. |
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249 | 254 | { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, |
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250 | 255 | { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, |
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251 | 256 | { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, |
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252 | | - { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 }, |
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253 | 257 | }; |
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254 | 258 | |
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255 | | -static struct clk_regmap axg_hifi_pll = { |
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| 259 | +static struct clk_regmap axg_hifi_pll_dco = { |
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256 | 260 | .data = &(struct meson_clk_pll_data){ |
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| 261 | + .en = { |
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| 262 | + .reg_off = HHI_HIFI_PLL_CNTL, |
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| 263 | + .shift = 30, |
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| 264 | + .width = 1, |
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| 265 | + }, |
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257 | 266 | .m = { |
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258 | 267 | .reg_off = HHI_HIFI_PLL_CNTL, |
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259 | 268 | .shift = 0, |
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.. | .. |
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263 | 272 | .reg_off = HHI_HIFI_PLL_CNTL, |
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264 | 273 | .shift = 9, |
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265 | 274 | .width = 5, |
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266 | | - }, |
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267 | | - .od = { |
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268 | | - .reg_off = HHI_HIFI_PLL_CNTL, |
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269 | | - .shift = 16, |
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270 | | - .width = 2, |
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271 | 275 | }, |
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272 | 276 | .frac = { |
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273 | 277 | .reg_off = HHI_HIFI_PLL_CNTL5, |
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.. | .. |
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284 | 288 | .shift = 29, |
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285 | 289 | .width = 1, |
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286 | 290 | }, |
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287 | | - .table = axg_gp0_pll_rate_table, |
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| 291 | + .table = axg_gp0_pll_params_table, |
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288 | 292 | .init_regs = axg_hifi_init_regs, |
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289 | 293 | .init_count = ARRAY_SIZE(axg_hifi_init_regs), |
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290 | 294 | .flags = CLK_MESON_PLL_ROUND_CLOSEST, |
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291 | 295 | }, |
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292 | 296 | .hw.init = &(struct clk_init_data){ |
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293 | | - .name = "hifi_pll", |
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| 297 | + .name = "hifi_pll_dco", |
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294 | 298 | .ops = &meson_clk_pll_ops, |
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295 | | - .parent_names = (const char *[]){ "xtal" }, |
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| 299 | + .parent_data = &(const struct clk_parent_data) { |
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| 300 | + .fw_name = "xtal", |
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| 301 | + }, |
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296 | 302 | .num_parents = 1, |
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| 303 | + }, |
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| 304 | +}; |
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| 305 | + |
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| 306 | +static struct clk_regmap axg_hifi_pll = { |
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| 307 | + .data = &(struct clk_regmap_div_data){ |
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| 308 | + .offset = HHI_HIFI_PLL_CNTL, |
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| 309 | + .shift = 16, |
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| 310 | + .width = 2, |
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| 311 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
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| 312 | + }, |
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| 313 | + .hw.init = &(struct clk_init_data){ |
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| 314 | + .name = "hifi_pll", |
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| 315 | + .ops = &clk_regmap_divider_ops, |
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| 316 | + .parent_hws = (const struct clk_hw *[]) { |
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| 317 | + &axg_hifi_pll_dco.hw |
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| 318 | + }, |
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| 319 | + .num_parents = 1, |
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| 320 | + .flags = CLK_SET_RATE_PARENT, |
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297 | 321 | }, |
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298 | 322 | }; |
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299 | 323 | |
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.. | .. |
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303 | 327 | .hw.init = &(struct clk_init_data){ |
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304 | 328 | .name = "fclk_div2_div", |
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305 | 329 | .ops = &clk_fixed_factor_ops, |
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306 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
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| 330 | + .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, |
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307 | 331 | .num_parents = 1, |
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308 | 332 | }, |
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309 | 333 | }; |
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.. | .. |
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316 | 340 | .hw.init = &(struct clk_init_data){ |
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317 | 341 | .name = "fclk_div2", |
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318 | 342 | .ops = &clk_regmap_gate_ops, |
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319 | | - .parent_names = (const char *[]){ "fclk_div2_div" }, |
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| 343 | + .parent_hws = (const struct clk_hw *[]) { |
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| 344 | + &axg_fclk_div2_div.hw |
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| 345 | + }, |
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320 | 346 | .num_parents = 1, |
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321 | 347 | .flags = CLK_IS_CRITICAL, |
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322 | 348 | }, |
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.. | .. |
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328 | 354 | .hw.init = &(struct clk_init_data){ |
---|
329 | 355 | .name = "fclk_div3_div", |
---|
330 | 356 | .ops = &clk_fixed_factor_ops, |
---|
331 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
---|
| 357 | + .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, |
---|
332 | 358 | .num_parents = 1, |
---|
333 | 359 | }, |
---|
334 | 360 | }; |
---|
.. | .. |
---|
341 | 367 | .hw.init = &(struct clk_init_data){ |
---|
342 | 368 | .name = "fclk_div3", |
---|
343 | 369 | .ops = &clk_regmap_gate_ops, |
---|
344 | | - .parent_names = (const char *[]){ "fclk_div3_div" }, |
---|
| 370 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 371 | + &axg_fclk_div3_div.hw |
---|
| 372 | + }, |
---|
345 | 373 | .num_parents = 1, |
---|
346 | 374 | /* |
---|
347 | 375 | * FIXME: |
---|
.. | .. |
---|
364 | 392 | .hw.init = &(struct clk_init_data){ |
---|
365 | 393 | .name = "fclk_div4_div", |
---|
366 | 394 | .ops = &clk_fixed_factor_ops, |
---|
367 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
---|
| 395 | + .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, |
---|
368 | 396 | .num_parents = 1, |
---|
369 | 397 | }, |
---|
370 | 398 | }; |
---|
.. | .. |
---|
377 | 405 | .hw.init = &(struct clk_init_data){ |
---|
378 | 406 | .name = "fclk_div4", |
---|
379 | 407 | .ops = &clk_regmap_gate_ops, |
---|
380 | | - .parent_names = (const char *[]){ "fclk_div4_div" }, |
---|
| 408 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 409 | + &axg_fclk_div4_div.hw |
---|
| 410 | + }, |
---|
381 | 411 | .num_parents = 1, |
---|
382 | 412 | }, |
---|
383 | 413 | }; |
---|
.. | .. |
---|
388 | 418 | .hw.init = &(struct clk_init_data){ |
---|
389 | 419 | .name = "fclk_div5_div", |
---|
390 | 420 | .ops = &clk_fixed_factor_ops, |
---|
391 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
---|
| 421 | + .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, |
---|
392 | 422 | .num_parents = 1, |
---|
393 | 423 | }, |
---|
394 | 424 | }; |
---|
.. | .. |
---|
401 | 431 | .hw.init = &(struct clk_init_data){ |
---|
402 | 432 | .name = "fclk_div5", |
---|
403 | 433 | .ops = &clk_regmap_gate_ops, |
---|
404 | | - .parent_names = (const char *[]){ "fclk_div5_div" }, |
---|
| 434 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 435 | + &axg_fclk_div5_div.hw |
---|
| 436 | + }, |
---|
405 | 437 | .num_parents = 1, |
---|
406 | 438 | }, |
---|
407 | 439 | }; |
---|
.. | .. |
---|
412 | 444 | .hw.init = &(struct clk_init_data){ |
---|
413 | 445 | .name = "fclk_div7_div", |
---|
414 | 446 | .ops = &clk_fixed_factor_ops, |
---|
415 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
---|
| 447 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 448 | + &axg_fixed_pll.hw |
---|
| 449 | + }, |
---|
416 | 450 | .num_parents = 1, |
---|
417 | 451 | }, |
---|
418 | 452 | }; |
---|
.. | .. |
---|
425 | 459 | .hw.init = &(struct clk_init_data){ |
---|
426 | 460 | .name = "fclk_div7", |
---|
427 | 461 | .ops = &clk_regmap_gate_ops, |
---|
428 | | - .parent_names = (const char *[]){ "fclk_div7_div" }, |
---|
| 462 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 463 | + &axg_fclk_div7_div.hw |
---|
| 464 | + }, |
---|
429 | 465 | .num_parents = 1, |
---|
430 | 466 | }, |
---|
431 | 467 | }; |
---|
.. | .. |
---|
439 | 475 | .hw.init = &(struct clk_init_data){ |
---|
440 | 476 | .name = "mpll_prediv", |
---|
441 | 477 | .ops = &clk_regmap_divider_ro_ops, |
---|
442 | | - .parent_names = (const char *[]){ "fixed_pll" }, |
---|
| 478 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 479 | + &axg_fixed_pll.hw |
---|
| 480 | + }, |
---|
443 | 481 | .num_parents = 1, |
---|
444 | 482 | }, |
---|
445 | 483 | }; |
---|
.. | .. |
---|
472 | 510 | .hw.init = &(struct clk_init_data){ |
---|
473 | 511 | .name = "mpll0_div", |
---|
474 | 512 | .ops = &meson_clk_mpll_ops, |
---|
475 | | - .parent_names = (const char *[]){ "mpll_prediv" }, |
---|
| 513 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 514 | + &axg_mpll_prediv.hw |
---|
| 515 | + }, |
---|
476 | 516 | .num_parents = 1, |
---|
477 | 517 | }, |
---|
478 | 518 | }; |
---|
.. | .. |
---|
485 | 525 | .hw.init = &(struct clk_init_data){ |
---|
486 | 526 | .name = "mpll0", |
---|
487 | 527 | .ops = &clk_regmap_gate_ops, |
---|
488 | | - .parent_names = (const char *[]){ "mpll0_div" }, |
---|
| 528 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 529 | + &axg_mpll0_div.hw |
---|
| 530 | + }, |
---|
489 | 531 | .num_parents = 1, |
---|
490 | 532 | .flags = CLK_SET_RATE_PARENT, |
---|
491 | 533 | }, |
---|
.. | .. |
---|
519 | 561 | .hw.init = &(struct clk_init_data){ |
---|
520 | 562 | .name = "mpll1_div", |
---|
521 | 563 | .ops = &meson_clk_mpll_ops, |
---|
522 | | - .parent_names = (const char *[]){ "mpll_prediv" }, |
---|
| 564 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 565 | + &axg_mpll_prediv.hw |
---|
| 566 | + }, |
---|
523 | 567 | .num_parents = 1, |
---|
524 | 568 | }, |
---|
525 | 569 | }; |
---|
.. | .. |
---|
532 | 576 | .hw.init = &(struct clk_init_data){ |
---|
533 | 577 | .name = "mpll1", |
---|
534 | 578 | .ops = &clk_regmap_gate_ops, |
---|
535 | | - .parent_names = (const char *[]){ "mpll1_div" }, |
---|
| 579 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 580 | + &axg_mpll1_div.hw |
---|
| 581 | + }, |
---|
536 | 582 | .num_parents = 1, |
---|
537 | 583 | .flags = CLK_SET_RATE_PARENT, |
---|
538 | 584 | }, |
---|
.. | .. |
---|
571 | 617 | .hw.init = &(struct clk_init_data){ |
---|
572 | 618 | .name = "mpll2_div", |
---|
573 | 619 | .ops = &meson_clk_mpll_ops, |
---|
574 | | - .parent_names = (const char *[]){ "mpll_prediv" }, |
---|
| 620 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 621 | + &axg_mpll_prediv.hw |
---|
| 622 | + }, |
---|
575 | 623 | .num_parents = 1, |
---|
576 | 624 | }, |
---|
577 | 625 | }; |
---|
.. | .. |
---|
584 | 632 | .hw.init = &(struct clk_init_data){ |
---|
585 | 633 | .name = "mpll2", |
---|
586 | 634 | .ops = &clk_regmap_gate_ops, |
---|
587 | | - .parent_names = (const char *[]){ "mpll2_div" }, |
---|
| 635 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 636 | + &axg_mpll2_div.hw |
---|
| 637 | + }, |
---|
588 | 638 | .num_parents = 1, |
---|
589 | 639 | .flags = CLK_SET_RATE_PARENT, |
---|
590 | 640 | }, |
---|
.. | .. |
---|
618 | 668 | .hw.init = &(struct clk_init_data){ |
---|
619 | 669 | .name = "mpll3_div", |
---|
620 | 670 | .ops = &meson_clk_mpll_ops, |
---|
621 | | - .parent_names = (const char *[]){ "mpll_prediv" }, |
---|
| 671 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 672 | + &axg_mpll_prediv.hw |
---|
| 673 | + }, |
---|
622 | 674 | .num_parents = 1, |
---|
623 | 675 | }, |
---|
624 | 676 | }; |
---|
.. | .. |
---|
631 | 683 | .hw.init = &(struct clk_init_data){ |
---|
632 | 684 | .name = "mpll3", |
---|
633 | 685 | .ops = &clk_regmap_gate_ops, |
---|
634 | | - .parent_names = (const char *[]){ "mpll3_div" }, |
---|
| 686 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 687 | + &axg_mpll3_div.hw |
---|
| 688 | + }, |
---|
635 | 689 | .num_parents = 1, |
---|
636 | 690 | .flags = CLK_SET_RATE_PARENT, |
---|
637 | 691 | }, |
---|
638 | 692 | }; |
---|
639 | 693 | |
---|
640 | | -static const struct pll_rate_table axg_pcie_pll_rate_table[] = { |
---|
| 694 | +static const struct pll_params_table axg_pcie_pll_params_table[] = { |
---|
641 | 695 | { |
---|
642 | | - .rate = 100000000, |
---|
643 | | - .m = 200, |
---|
644 | | - .n = 3, |
---|
645 | | - .od = 1, |
---|
646 | | - .od2 = 3, |
---|
| 696 | + .m = 200, |
---|
| 697 | + .n = 3, |
---|
647 | 698 | }, |
---|
648 | 699 | { /* sentinel */ }, |
---|
649 | 700 | }; |
---|
650 | 701 | |
---|
651 | 702 | static const struct reg_sequence axg_pcie_init_regs[] = { |
---|
652 | | - { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, |
---|
653 | 703 | { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, |
---|
654 | 704 | { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, |
---|
655 | 705 | { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, |
---|
656 | 706 | { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, |
---|
657 | 707 | { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, |
---|
658 | 708 | { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, |
---|
| 709 | + { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, |
---|
659 | 710 | }; |
---|
660 | 711 | |
---|
661 | | -static struct clk_regmap axg_pcie_pll = { |
---|
| 712 | +static struct clk_regmap axg_pcie_pll_dco = { |
---|
662 | 713 | .data = &(struct meson_clk_pll_data){ |
---|
| 714 | + .en = { |
---|
| 715 | + .reg_off = HHI_PCIE_PLL_CNTL, |
---|
| 716 | + .shift = 30, |
---|
| 717 | + .width = 1, |
---|
| 718 | + }, |
---|
663 | 719 | .m = { |
---|
664 | 720 | .reg_off = HHI_PCIE_PLL_CNTL, |
---|
665 | 721 | .shift = 0, |
---|
.. | .. |
---|
669 | 725 | .reg_off = HHI_PCIE_PLL_CNTL, |
---|
670 | 726 | .shift = 9, |
---|
671 | 727 | .width = 5, |
---|
672 | | - }, |
---|
673 | | - .od = { |
---|
674 | | - .reg_off = HHI_PCIE_PLL_CNTL, |
---|
675 | | - .shift = 16, |
---|
676 | | - .width = 2, |
---|
677 | | - }, |
---|
678 | | - .od2 = { |
---|
679 | | - .reg_off = HHI_PCIE_PLL_CNTL6, |
---|
680 | | - .shift = 6, |
---|
681 | | - .width = 2, |
---|
682 | 728 | }, |
---|
683 | 729 | .frac = { |
---|
684 | 730 | .reg_off = HHI_PCIE_PLL_CNTL1, |
---|
.. | .. |
---|
695 | 741 | .shift = 29, |
---|
696 | 742 | .width = 1, |
---|
697 | 743 | }, |
---|
698 | | - .table = axg_pcie_pll_rate_table, |
---|
| 744 | + .table = axg_pcie_pll_params_table, |
---|
699 | 745 | .init_regs = axg_pcie_init_regs, |
---|
700 | 746 | .init_count = ARRAY_SIZE(axg_pcie_init_regs), |
---|
701 | 747 | }, |
---|
702 | 748 | .hw.init = &(struct clk_init_data){ |
---|
703 | | - .name = "pcie_pll", |
---|
| 749 | + .name = "pcie_pll_dco", |
---|
704 | 750 | .ops = &meson_clk_pll_ops, |
---|
705 | | - .parent_names = (const char *[]){ "xtal" }, |
---|
| 751 | + .parent_data = &(const struct clk_parent_data) { |
---|
| 752 | + .fw_name = "xtal", |
---|
| 753 | + }, |
---|
706 | 754 | .num_parents = 1, |
---|
| 755 | + }, |
---|
| 756 | +}; |
---|
| 757 | + |
---|
| 758 | +static struct clk_regmap axg_pcie_pll_od = { |
---|
| 759 | + .data = &(struct clk_regmap_div_data){ |
---|
| 760 | + .offset = HHI_PCIE_PLL_CNTL, |
---|
| 761 | + .shift = 16, |
---|
| 762 | + .width = 2, |
---|
| 763 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
---|
| 764 | + }, |
---|
| 765 | + .hw.init = &(struct clk_init_data){ |
---|
| 766 | + .name = "pcie_pll_od", |
---|
| 767 | + .ops = &clk_regmap_divider_ops, |
---|
| 768 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 769 | + &axg_pcie_pll_dco.hw |
---|
| 770 | + }, |
---|
| 771 | + .num_parents = 1, |
---|
| 772 | + .flags = CLK_SET_RATE_PARENT, |
---|
| 773 | + }, |
---|
| 774 | +}; |
---|
| 775 | + |
---|
| 776 | +static struct clk_regmap axg_pcie_pll = { |
---|
| 777 | + .data = &(struct clk_regmap_div_data){ |
---|
| 778 | + .offset = HHI_PCIE_PLL_CNTL6, |
---|
| 779 | + .shift = 6, |
---|
| 780 | + .width = 2, |
---|
| 781 | + .flags = CLK_DIVIDER_POWER_OF_TWO, |
---|
| 782 | + }, |
---|
| 783 | + .hw.init = &(struct clk_init_data){ |
---|
| 784 | + .name = "pcie_pll", |
---|
| 785 | + .ops = &clk_regmap_divider_ops, |
---|
| 786 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 787 | + &axg_pcie_pll_od.hw |
---|
| 788 | + }, |
---|
| 789 | + .num_parents = 1, |
---|
| 790 | + .flags = CLK_SET_RATE_PARENT, |
---|
707 | 791 | }, |
---|
708 | 792 | }; |
---|
709 | 793 | |
---|
.. | .. |
---|
718 | 802 | .hw.init = &(struct clk_init_data){ |
---|
719 | 803 | .name = "pcie_mux", |
---|
720 | 804 | .ops = &clk_regmap_mux_ops, |
---|
721 | | - .parent_names = (const char *[]){ "pcie_pll" }, |
---|
| 805 | + .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, |
---|
722 | 806 | .num_parents = 1, |
---|
723 | 807 | .flags = CLK_SET_RATE_PARENT, |
---|
724 | 808 | }, |
---|
.. | .. |
---|
735 | 819 | .hw.init = &(struct clk_init_data){ |
---|
736 | 820 | .name = "pcie_ref", |
---|
737 | 821 | .ops = &clk_regmap_mux_ops, |
---|
738 | | - .parent_names = (const char *[]){ "pcie_mux" }, |
---|
| 822 | + .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, |
---|
739 | 823 | .num_parents = 1, |
---|
740 | 824 | .flags = CLK_SET_RATE_PARENT, |
---|
741 | 825 | }, |
---|
.. | .. |
---|
749 | 833 | .hw.init = &(struct clk_init_data) { |
---|
750 | 834 | .name = "pcie_cml_en0", |
---|
751 | 835 | .ops = &clk_regmap_gate_ops, |
---|
752 | | - .parent_names = (const char *[]){ "pcie_ref" }, |
---|
| 836 | + .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, |
---|
753 | 837 | .num_parents = 1, |
---|
754 | 838 | .flags = CLK_SET_RATE_PARENT, |
---|
755 | 839 | |
---|
.. | .. |
---|
764 | 848 | .hw.init = &(struct clk_init_data) { |
---|
765 | 849 | .name = "pcie_cml_en1", |
---|
766 | 850 | .ops = &clk_regmap_gate_ops, |
---|
767 | | - .parent_names = (const char *[]){ "pcie_ref" }, |
---|
| 851 | + .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, |
---|
768 | 852 | .num_parents = 1, |
---|
769 | 853 | .flags = CLK_SET_RATE_PARENT, |
---|
770 | 854 | }, |
---|
771 | 855 | }; |
---|
772 | 856 | |
---|
773 | 857 | static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; |
---|
774 | | -static const char * const clk81_parent_names[] = { |
---|
775 | | - "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", |
---|
776 | | - "fclk_div3", "fclk_div5" |
---|
| 858 | +static const struct clk_parent_data clk81_parent_data[] = { |
---|
| 859 | + { .fw_name = "xtal", }, |
---|
| 860 | + { .hw = &axg_fclk_div7.hw }, |
---|
| 861 | + { .hw = &axg_mpll1.hw }, |
---|
| 862 | + { .hw = &axg_mpll2.hw }, |
---|
| 863 | + { .hw = &axg_fclk_div4.hw }, |
---|
| 864 | + { .hw = &axg_fclk_div3.hw }, |
---|
| 865 | + { .hw = &axg_fclk_div5.hw }, |
---|
777 | 866 | }; |
---|
778 | 867 | |
---|
779 | 868 | static struct clk_regmap axg_mpeg_clk_sel = { |
---|
.. | .. |
---|
786 | 875 | .hw.init = &(struct clk_init_data){ |
---|
787 | 876 | .name = "mpeg_clk_sel", |
---|
788 | 877 | .ops = &clk_regmap_mux_ro_ops, |
---|
789 | | - .parent_names = clk81_parent_names, |
---|
790 | | - .num_parents = ARRAY_SIZE(clk81_parent_names), |
---|
| 878 | + .parent_data = clk81_parent_data, |
---|
| 879 | + .num_parents = ARRAY_SIZE(clk81_parent_data), |
---|
791 | 880 | }, |
---|
792 | 881 | }; |
---|
793 | 882 | |
---|
.. | .. |
---|
800 | 889 | .hw.init = &(struct clk_init_data){ |
---|
801 | 890 | .name = "mpeg_clk_div", |
---|
802 | 891 | .ops = &clk_regmap_divider_ops, |
---|
803 | | - .parent_names = (const char *[]){ "mpeg_clk_sel" }, |
---|
| 892 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 893 | + &axg_mpeg_clk_sel.hw |
---|
| 894 | + }, |
---|
804 | 895 | .num_parents = 1, |
---|
805 | 896 | .flags = CLK_SET_RATE_PARENT, |
---|
806 | 897 | }, |
---|
.. | .. |
---|
814 | 905 | .hw.init = &(struct clk_init_data){ |
---|
815 | 906 | .name = "clk81", |
---|
816 | 907 | .ops = &clk_regmap_gate_ops, |
---|
817 | | - .parent_names = (const char *[]){ "mpeg_clk_div" }, |
---|
| 908 | + .parent_hws = (const struct clk_hw *[]) { |
---|
| 909 | + &axg_mpeg_clk_div.hw |
---|
| 910 | + }, |
---|
818 | 911 | .num_parents = 1, |
---|
819 | 912 | .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), |
---|
820 | 913 | }, |
---|
821 | 914 | }; |
---|
822 | 915 | |
---|
823 | | -static const char * const axg_sd_emmc_clk0_parent_names[] = { |
---|
824 | | - "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", |
---|
825 | | - |
---|
| 916 | +static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = { |
---|
| 917 | + { .fw_name = "xtal", }, |
---|
| 918 | + { .hw = &axg_fclk_div2.hw }, |
---|
| 919 | + { .hw = &axg_fclk_div3.hw }, |
---|
| 920 | + { .hw = &axg_fclk_div5.hw }, |
---|
| 921 | + { .hw = &axg_fclk_div7.hw }, |
---|
826 | 922 | /* |
---|
827 | 923 | * Following these parent clocks, we should also have had mpll2, mpll3 |
---|
828 | 924 | * and gp0_pll but these clocks are too precious to be used here. All |
---|
.. | .. |
---|
841 | 937 | .hw.init = &(struct clk_init_data) { |
---|
842 | 938 | .name = "sd_emmc_b_clk0_sel", |
---|
843 | 939 | .ops = &clk_regmap_mux_ops, |
---|
844 | | - .parent_names = axg_sd_emmc_clk0_parent_names, |
---|
845 | | - .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), |
---|
| 940 | + .parent_data = axg_sd_emmc_clk0_parent_data, |
---|
| 941 | + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), |
---|
846 | 942 | .flags = CLK_SET_RATE_PARENT, |
---|
847 | 943 | }, |
---|
848 | 944 | }; |
---|
.. | .. |
---|
857 | 953 | .hw.init = &(struct clk_init_data) { |
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858 | 954 | .name = "sd_emmc_b_clk0_div", |
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859 | 955 | .ops = &clk_regmap_divider_ops, |
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860 | | - .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, |
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| 956 | + .parent_hws = (const struct clk_hw *[]) { |
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| 957 | + &axg_sd_emmc_b_clk0_sel.hw |
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| 958 | + }, |
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861 | 959 | .num_parents = 1, |
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862 | 960 | .flags = CLK_SET_RATE_PARENT, |
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863 | 961 | }, |
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.. | .. |
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871 | 969 | .hw.init = &(struct clk_init_data){ |
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872 | 970 | .name = "sd_emmc_b_clk0", |
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873 | 971 | .ops = &clk_regmap_gate_ops, |
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874 | | - .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, |
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| 972 | + .parent_hws = (const struct clk_hw *[]) { |
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| 973 | + &axg_sd_emmc_b_clk0_div.hw |
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| 974 | + }, |
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875 | 975 | .num_parents = 1, |
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876 | 976 | .flags = CLK_SET_RATE_PARENT, |
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877 | 977 | }, |
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.. | .. |
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887 | 987 | .hw.init = &(struct clk_init_data) { |
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888 | 988 | .name = "sd_emmc_c_clk0_sel", |
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889 | 989 | .ops = &clk_regmap_mux_ops, |
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890 | | - .parent_names = axg_sd_emmc_clk0_parent_names, |
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891 | | - .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), |
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| 990 | + .parent_data = axg_sd_emmc_clk0_parent_data, |
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| 991 | + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data), |
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892 | 992 | .flags = CLK_SET_RATE_PARENT, |
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893 | 993 | }, |
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894 | 994 | }; |
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.. | .. |
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903 | 1003 | .hw.init = &(struct clk_init_data) { |
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904 | 1004 | .name = "sd_emmc_c_clk0_div", |
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905 | 1005 | .ops = &clk_regmap_divider_ops, |
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906 | | - .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, |
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| 1006 | + .parent_hws = (const struct clk_hw *[]) { |
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| 1007 | + &axg_sd_emmc_c_clk0_sel.hw |
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| 1008 | + }, |
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907 | 1009 | .num_parents = 1, |
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908 | 1010 | .flags = CLK_SET_RATE_PARENT, |
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909 | 1011 | }, |
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.. | .. |
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917 | 1019 | .hw.init = &(struct clk_init_data){ |
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918 | 1020 | .name = "sd_emmc_c_clk0", |
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919 | 1021 | .ops = &clk_regmap_gate_ops, |
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920 | | - .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, |
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| 1022 | + .parent_hws = (const struct clk_hw *[]) { |
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| 1023 | + &axg_sd_emmc_c_clk0_div.hw |
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| 1024 | + }, |
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921 | 1025 | .num_parents = 1, |
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922 | 1026 | .flags = CLK_SET_RATE_PARENT, |
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923 | 1027 | }, |
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.. | .. |
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925 | 1029 | |
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926 | 1030 | static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, |
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927 | 1031 | 9, 10, 11, 13, 14, }; |
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928 | | -static const char * const gen_clk_parent_names[] = { |
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929 | | - "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3", |
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930 | | - "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", |
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| 1032 | +static const struct clk_parent_data gen_clk_parent_data[] = { |
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| 1033 | + { .fw_name = "xtal", }, |
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| 1034 | + { .hw = &axg_hifi_pll.hw }, |
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| 1035 | + { .hw = &axg_mpll0.hw }, |
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| 1036 | + { .hw = &axg_mpll1.hw }, |
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| 1037 | + { .hw = &axg_mpll2.hw }, |
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| 1038 | + { .hw = &axg_mpll3.hw }, |
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| 1039 | + { .hw = &axg_fclk_div4.hw }, |
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| 1040 | + { .hw = &axg_fclk_div3.hw }, |
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| 1041 | + { .hw = &axg_fclk_div5.hw }, |
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| 1042 | + { .hw = &axg_fclk_div7.hw }, |
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| 1043 | + { .hw = &axg_gp0_pll.hw }, |
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931 | 1044 | }; |
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932 | 1045 | |
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933 | 1046 | static struct clk_regmap axg_gen_clk_sel = { |
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.. | .. |
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946 | 1059 | * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, |
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947 | 1060 | * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll |
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948 | 1061 | */ |
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949 | | - .parent_names = gen_clk_parent_names, |
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950 | | - .num_parents = ARRAY_SIZE(gen_clk_parent_names), |
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| 1062 | + .parent_data = gen_clk_parent_data, |
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| 1063 | + .num_parents = ARRAY_SIZE(gen_clk_parent_data), |
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951 | 1064 | }, |
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952 | 1065 | }; |
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953 | 1066 | |
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.. | .. |
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960 | 1073 | .hw.init = &(struct clk_init_data){ |
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961 | 1074 | .name = "gen_clk_div", |
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962 | 1075 | .ops = &clk_regmap_divider_ops, |
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963 | | - .parent_names = (const char *[]){ "gen_clk_sel" }, |
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| 1076 | + .parent_hws = (const struct clk_hw *[]) { |
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| 1077 | + &axg_gen_clk_sel.hw |
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| 1078 | + }, |
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964 | 1079 | .num_parents = 1, |
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965 | 1080 | .flags = CLK_SET_RATE_PARENT, |
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966 | 1081 | }, |
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.. | .. |
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974 | 1089 | .hw.init = &(struct clk_init_data){ |
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975 | 1090 | .name = "gen_clk", |
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976 | 1091 | .ops = &clk_regmap_gate_ops, |
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977 | | - .parent_names = (const char *[]){ "gen_clk_div" }, |
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| 1092 | + .parent_hws = (const struct clk_hw *[]) { |
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| 1093 | + &axg_gen_clk_div.hw |
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| 1094 | + }, |
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978 | 1095 | .num_parents = 1, |
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979 | 1096 | .flags = CLK_SET_RATE_PARENT, |
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980 | 1097 | }, |
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981 | 1098 | }; |
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| 1099 | + |
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| 1100 | +#define MESON_GATE(_name, _reg, _bit) \ |
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| 1101 | + MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) |
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982 | 1102 | |
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983 | 1103 | /* Everything Else (EE) domain gates */ |
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984 | 1104 | static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); |
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.. | .. |
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1121 | 1241 | [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, |
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1122 | 1242 | [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, |
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1123 | 1243 | [CLKID_GEN_CLK] = &axg_gen_clk.hw, |
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| 1244 | + [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, |
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| 1245 | + [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, |
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| 1246 | + [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, |
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| 1247 | + [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, |
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| 1248 | + [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, |
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| 1249 | + [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, |
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1124 | 1250 | [NR_CLKS] = NULL, |
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1125 | 1251 | }, |
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1126 | 1252 | .num = NR_CLKS, |
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.. | .. |
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1199 | 1325 | &axg_fclk_div4, |
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1200 | 1326 | &axg_fclk_div5, |
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1201 | 1327 | &axg_fclk_div7, |
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| 1328 | + &axg_pcie_pll_dco, |
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| 1329 | + &axg_pcie_pll_od, |
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1202 | 1330 | &axg_pcie_pll, |
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1203 | 1331 | &axg_pcie_mux, |
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1204 | 1332 | &axg_pcie_ref, |
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.. | .. |
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1208 | 1336 | &axg_gen_clk_sel, |
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1209 | 1337 | &axg_gen_clk_div, |
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1210 | 1338 | &axg_gen_clk, |
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| 1339 | + &axg_fixed_pll_dco, |
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| 1340 | + &axg_sys_pll_dco, |
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| 1341 | + &axg_gp0_pll_dco, |
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| 1342 | + &axg_hifi_pll_dco, |
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| 1343 | + &axg_pcie_pll_dco, |
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| 1344 | + &axg_pcie_pll_od, |
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1211 | 1345 | }; |
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| 1346 | + |
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| 1347 | +static const struct meson_eeclkc_data axg_clkc_data = { |
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| 1348 | + .regmap_clks = axg_clk_regmaps, |
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| 1349 | + .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), |
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| 1350 | + .hw_onecell_data = &axg_hw_onecell_data, |
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| 1351 | +}; |
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| 1352 | + |
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1212 | 1353 | |
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1213 | 1354 | static const struct of_device_id clkc_match_table[] = { |
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1214 | | - { .compatible = "amlogic,axg-clkc" }, |
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| 1355 | + { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, |
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1215 | 1356 | {} |
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1216 | 1357 | }; |
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1217 | | - |
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1218 | | -static int axg_clkc_probe(struct platform_device *pdev) |
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1219 | | -{ |
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1220 | | - struct device *dev = &pdev->dev; |
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1221 | | - struct regmap *map; |
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1222 | | - int ret, i; |
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1223 | | - |
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1224 | | - /* Get the hhi system controller node if available */ |
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1225 | | - map = syscon_node_to_regmap(of_get_parent(dev->of_node)); |
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1226 | | - if (IS_ERR(map)) { |
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1227 | | - dev_err(dev, "failed to get HHI regmap\n"); |
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1228 | | - return PTR_ERR(map); |
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1229 | | - } |
---|
1230 | | - |
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1231 | | - /* Populate regmap for the regmap backed clocks */ |
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1232 | | - for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) |
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1233 | | - axg_clk_regmaps[i]->map = map; |
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1234 | | - |
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1235 | | - for (i = 0; i < axg_hw_onecell_data.num; i++) { |
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1236 | | - /* array might be sparse */ |
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1237 | | - if (!axg_hw_onecell_data.hws[i]) |
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1238 | | - continue; |
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1239 | | - |
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1240 | | - ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]); |
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1241 | | - if (ret) { |
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1242 | | - dev_err(dev, "Clock registration failed\n"); |
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1243 | | - return ret; |
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1244 | | - } |
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1245 | | - } |
---|
1246 | | - |
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1247 | | - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, |
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1248 | | - &axg_hw_onecell_data); |
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1249 | | -} |
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| 1358 | +MODULE_DEVICE_TABLE(of, clkc_match_table); |
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1250 | 1359 | |
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1251 | 1360 | static struct platform_driver axg_driver = { |
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1252 | | - .probe = axg_clkc_probe, |
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| 1361 | + .probe = meson_eeclkc_probe, |
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1253 | 1362 | .driver = { |
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1254 | 1363 | .name = "axg-clkc", |
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1255 | 1364 | .of_match_table = clkc_match_table, |
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1256 | 1365 | }, |
---|
1257 | 1366 | }; |
---|
1258 | 1367 | |
---|
1259 | | -builtin_platform_driver(axg_driver); |
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| 1368 | +module_platform_driver(axg_driver); |
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| 1369 | +MODULE_LICENSE("GPL v2"); |
---|