add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/drivers/clk/ingenic/cgu.h
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@@ -1,30 +1,23 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Ingenic SoC CGU driver
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  *
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  * Copyright (c) 2013-2015 Imagination Technologies
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  * Author: Paul Burton <paul.burton@mips.com>
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__
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 #define __DRIVERS_CLK_INGENIC_CGU_H__
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 #include <linux/bitops.h>
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+#include <linux/clk-provider.h>
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 #include <linux/of.h>
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 #include <linux/spinlock.h>
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 /**
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  * struct ingenic_cgu_pll_info - information about a PLL
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  * @reg: the offset of the PLL's control register within the CGU
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+ * @rate_multiplier: the multiplier needed by pll rate calculation
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  * @m_shift: the number of bits to shift the multiplier value by (ie. the
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  *           index of the lowest bit of the multiplier value in the PLL's
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  *           control register)
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@@ -45,6 +38,7 @@
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  * @od_encoding: a pointer to an array mapping post-VCO divider values to
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  *               their encoded values in the PLL control register, or -1 for
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  *               unsupported values
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+ * @bypass_reg: the offset of the bypass control register within the CGU
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  * @bypass_bit: the index of the bypass bit in the PLL control register
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  * @enable_bit: the index of the enable bit in the PLL control register
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  * @stable_bit: the index of the stable bit in the PLL control register
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  */
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 struct ingenic_cgu_pll_info {
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 	unsigned reg;
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+	unsigned rate_multiplier;
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 	const s8 *od_encoding;
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 	u8 m_shift, m_bits, m_offset;
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 	u8 n_shift, n_bits, n_offset;
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 	u8 od_shift, od_bits, od_max;
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+	unsigned bypass_reg;
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 	u8 bypass_bit;
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 	u8 enable_bit;
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 	u8 stable_bit;
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@@ -88,6 +84,8 @@
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  *          isn't one
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  * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
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  * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
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+ * @div_table: optional table to map the value read from the register to the
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+ *             actual divider value
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  */
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 struct ingenic_cgu_div_info {
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 	unsigned reg;
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@@ -97,6 +95,7 @@
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 	s8 ce_bit;
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 	s8 busy_bit;
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 	s8 stop_bit;
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+	const u8 *div_table;
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 };
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 /**