forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2 
 kernel/arch/arm64/include/asm/cputype.h
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2012 ARM Ltd.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 #ifndef __ASM_CPUTYPE_H
176 #define __ASM_CPUTYPE_H
....@@ -52,7 +41,7 @@
5241 	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
5342 
5443 #define MIDR_CPU_MODEL(imp, partnum) \
55
-	(((imp)			<< MIDR_IMPLEMENTOR_SHIFT) | \
44
+	((_AT(u32, imp)		<< MIDR_IMPLEMENTOR_SHIFT) | \
5645 	(0xf			<< MIDR_ARCHITECTURE_SHIFT) | \
5746 	((partnum)		<< MIDR_PARTNUM_SHIFT))
5847 
....@@ -68,7 +57,10 @@
6857 #define ARM_CPU_IMP_BRCM		0x42
6958 #define ARM_CPU_IMP_QCOM		0x51
7059 #define ARM_CPU_IMP_NVIDIA		0x4E
60
+#define ARM_CPU_IMP_FUJITSU		0x46
7161 #define ARM_CPU_IMP_HISI		0x48
62
+#define ARM_CPU_IMP_APPLE		0x61
63
+#define ARM_CPU_IMP_AMPERE		0xC0
7264 
7365 #define ARM_CPU_PART_AEM_V8		0xD0F
7466 #define ARM_CPU_PART_FOUNDATION		0xD00
....@@ -81,6 +73,17 @@
8173 #define ARM_CPU_PART_CORTEX_A55		0xD05
8274 #define ARM_CPU_PART_CORTEX_A76		0xD0B
8375 #define ARM_CPU_PART_NEOVERSE_N1	0xD0C
76
+#define ARM_CPU_PART_CORTEX_A77		0xD0D
77
+#define ARM_CPU_PART_NEOVERSE_V1	0xD40
78
+#define ARM_CPU_PART_CORTEX_A78		0xD41
79
+#define ARM_CPU_PART_CORTEX_A78AE	0xD42
80
+#define ARM_CPU_PART_CORTEX_X1		0xD44
81
+#define ARM_CPU_PART_CORTEX_A510	0xD46
82
+#define ARM_CPU_PART_CORTEX_A520	0xD80
83
+#define ARM_CPU_PART_CORTEX_A710	0xD47
84
+#define ARM_CPU_PART_CORTEX_X2		0xD48
85
+#define ARM_CPU_PART_NEOVERSE_N2	0xD49
86
+#define ARM_CPU_PART_CORTEX_A78C	0xD4B
8487 
8588 #define APM_CPU_PART_POTENZA		0x000
8689 
....@@ -89,16 +92,29 @@
8992 #define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3
9093 #define CAVIUM_CPU_PART_THUNDERX2	0x0AF
9194 
95
+#define BRCM_CPU_PART_BRAHMA_B53	0x100
9296 #define BRCM_CPU_PART_VULCAN		0x516
9397 
9498 #define QCOM_CPU_PART_FALKOR_V1		0x800
9599 #define QCOM_CPU_PART_FALKOR		0xC00
96100 #define QCOM_CPU_PART_KRYO		0x200
101
+#define QCOM_CPU_PART_KRYO_2XX_GOLD	0x800
102
+#define QCOM_CPU_PART_KRYO_2XX_SILVER	0x801
103
+#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803
104
+#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804
105
+#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805
97106 
98107 #define NVIDIA_CPU_PART_DENVER		0x003
99108 #define NVIDIA_CPU_PART_CARMEL		0x004
100109 
110
+#define FUJITSU_CPU_PART_A64FX		0x001
111
+
101112 #define HISI_CPU_PART_TSV110		0xD01
113
+
114
+#define APPLE_CPU_PART_M1_ICESTORM	0x022
115
+#define APPLE_CPU_PART_M1_FIRESTORM	0x023
116
+
117
+#define AMPERE_CPU_PART_AMPERE1		0xAC3
102118 
103119 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
104120 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
....@@ -107,19 +123,45 @@
107123 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
108124 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
109125 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
110
-#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
126
+#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
111127 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
128
+#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
129
+#define MIDR_NEOVERSE_V1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
130
+#define MIDR_CORTEX_A78	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
131
+#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
132
+#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
133
+#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
134
+#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
135
+#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
136
+#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
137
+#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
138
+#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
112139 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
113140 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
114141 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
115142 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
143
+#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
116144 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
117145 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
118146 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
119147 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
148
+#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
149
+#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
150
+#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
151
+#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
152
+#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
120153 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
121154 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
155
+#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
122156 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
157
+#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
158
+#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
159
+#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
160
+
161
+/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
162
+#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
163
+#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))
164
+#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)
123165 
124166 #ifndef __ASSEMBLY__
125167 
....@@ -149,6 +191,8 @@
149191 		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\
150192 	}
151193 
194
+#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
195
+#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
152196 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
153197 
154198 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,