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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2014 ARM Ltd. |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License version 2 as |
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6 | | - * published by the Free Software Foundation. |
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7 | | - * |
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8 | | - * This program is distributed in the hope that it will be useful, |
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9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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11 | | - * GNU General Public License for more details. |
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12 | | - * |
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13 | | - * You should have received a copy of the GNU General Public License |
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14 | | - * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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15 | 4 | */ |
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16 | 5 | #ifndef __ASM_CPU_H |
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17 | 6 | #define __ASM_CPU_H |
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.. | .. |
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23 | 12 | /* |
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24 | 13 | * Records attributes of an individual CPU. |
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25 | 14 | */ |
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| 15 | +struct cpuinfo_32bit { |
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| 16 | + u32 reg_id_dfr0; |
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| 17 | + u32 reg_id_dfr1; |
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| 18 | + u32 reg_id_isar0; |
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| 19 | + u32 reg_id_isar1; |
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| 20 | + u32 reg_id_isar2; |
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| 21 | + u32 reg_id_isar3; |
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| 22 | + u32 reg_id_isar4; |
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| 23 | + u32 reg_id_isar5; |
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| 24 | + u32 reg_id_isar6; |
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| 25 | + u32 reg_id_mmfr0; |
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| 26 | + u32 reg_id_mmfr1; |
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| 27 | + u32 reg_id_mmfr2; |
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| 28 | + u32 reg_id_mmfr3; |
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| 29 | + u32 reg_id_mmfr4; |
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| 30 | + u32 reg_id_mmfr5; |
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| 31 | + u32 reg_id_pfr0; |
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| 32 | + u32 reg_id_pfr1; |
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| 33 | + u32 reg_id_pfr2; |
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| 34 | + |
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| 35 | + u32 reg_mvfr0; |
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| 36 | + u32 reg_mvfr1; |
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| 37 | + u32 reg_mvfr2; |
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| 38 | +}; |
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| 39 | + |
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26 | 40 | struct cpuinfo_arm64 { |
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27 | 41 | struct cpu cpu; |
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28 | 42 | struct kobject kobj; |
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.. | .. |
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36 | 50 | u64 reg_id_aa64dfr1; |
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37 | 51 | u64 reg_id_aa64isar0; |
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38 | 52 | u64 reg_id_aa64isar1; |
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| 53 | + u64 reg_id_aa64isar2; |
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39 | 54 | u64 reg_id_aa64mmfr0; |
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40 | 55 | u64 reg_id_aa64mmfr1; |
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41 | 56 | u64 reg_id_aa64mmfr2; |
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.. | .. |
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43 | 58 | u64 reg_id_aa64pfr1; |
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44 | 59 | u64 reg_id_aa64zfr0; |
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45 | 60 | |
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46 | | - u32 reg_id_dfr0; |
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47 | | - u32 reg_id_isar0; |
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48 | | - u32 reg_id_isar1; |
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49 | | - u32 reg_id_isar2; |
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50 | | - u32 reg_id_isar3; |
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51 | | - u32 reg_id_isar4; |
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52 | | - u32 reg_id_isar5; |
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53 | | - u32 reg_id_mmfr0; |
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54 | | - u32 reg_id_mmfr1; |
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55 | | - u32 reg_id_mmfr2; |
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56 | | - u32 reg_id_mmfr3; |
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57 | | - u32 reg_id_pfr0; |
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58 | | - u32 reg_id_pfr1; |
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59 | | - |
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60 | | - u32 reg_mvfr0; |
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61 | | - u32 reg_mvfr1; |
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62 | | - u32 reg_mvfr2; |
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| 61 | + struct cpuinfo_32bit aarch32; |
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63 | 62 | |
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64 | 63 | /* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */ |
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65 | 64 | u64 reg_zcr; |
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