add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
..
..
@@ -7,8 +7,7 @@
7
7
 
8
8
 #include <dt-bindings/gpio/gpio.h>
9
9
 #include <dt-bindings/gpio/uniphier-gpio.h>
10
-
11
-/memreserve/ 0x80000000 0x02000000;
10
+#include <dt-bindings/thermal/thermal.h>
12
11
 
13
12
 / {
14
13
 	compatible = "socionext,uniphier-pxs3";
..
..
@@ -39,38 +38,42 @@
39
38
 
40
39
 		cpu0: cpu@0 {
41
40
 			device_type = "cpu";
42
-			compatible = "arm,cortex-a53", "arm,armv8";
41
+			compatible = "arm,cortex-a53";
43
42
 			reg = <0 0x000>;
44
43
 			clocks = <&sys_clk 33>;
45
44
 			enable-method = "psci";
46
45
 			operating-points-v2 = <&cluster0_opp>;
46
+			#cooling-cells = <2>;
47
47
 		};
48
48
 
49
49
 		cpu1: cpu@1 {
50
50
 			device_type = "cpu";
51
-			compatible = "arm,cortex-a53", "arm,armv8";
51
+			compatible = "arm,cortex-a53";
52
52
 			reg = <0 0x001>;
53
53
 			clocks = <&sys_clk 33>;
54
54
 			enable-method = "psci";
55
55
 			operating-points-v2 = <&cluster0_opp>;
56
+			#cooling-cells = <2>;
56
57
 		};
57
58
 
58
59
 		cpu2: cpu@2 {
59
60
 			device_type = "cpu";
60
-			compatible = "arm,cortex-a53", "arm,armv8";
61
+			compatible = "arm,cortex-a53";
61
62
 			reg = <0 0x002>;
62
63
 			clocks = <&sys_clk 33>;
63
64
 			enable-method = "psci";
64
65
 			operating-points-v2 = <&cluster0_opp>;
66
+			#cooling-cells = <2>;
65
67
 		};
66
68
 
67
69
 		cpu3: cpu@3 {
68
70
 			device_type = "cpu";
69
-			compatible = "arm,cortex-a53", "arm,armv8";
71
+			compatible = "arm,cortex-a53";
70
72
 			reg = <0 0x003>;
71
73
 			clocks = <&sys_clk 33>;
72
74
 			enable-method = "psci";
73
75
 			operating-points-v2 = <&cluster0_opp>;
76
+			#cooling-cells = <2>;
74
77
 		};
75
78
 	};
76
79
 
..
..
@@ -138,11 +141,79 @@
138
141
 			     <1 10 4>;
139
142
 	};
140
143
 
144
+	thermal-zones {
145
+		cpu-thermal {
146
+			polling-delay-passive = <250>;	/* 250ms */
147
+			polling-delay = <1000>;		/* 1000ms */
148
+			thermal-sensors = <&pvtctl>;
149
+
150
+			trips {
151
+				cpu_crit: cpu-crit {
152
+					temperature = <110000>;	/* 110C */
153
+					hysteresis = <2000>;
154
+					type = "critical";
155
+				};
156
+				cpu_alert: cpu-alert {
157
+					temperature = <100000>;	/* 100C */
158
+					hysteresis = <2000>;
159
+					type = "passive";
160
+				};
161
+			};
162
+
163
+			cooling-maps {
164
+				map0 {
165
+					trip = <&cpu_alert>;
166
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
167
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
168
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
169
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
170
+				};
171
+			};
172
+		};
173
+	};
174
+
175
+	reserved-memory {
176
+		#address-cells = <2>;
177
+		#size-cells = <2>;
178
+		ranges;
179
+
180
+		secure-memory@81000000 {
181
+			reg = <0x0 0x81000000 0x0 0x01000000>;
182
+			no-map;
183
+		};
184
+	};
185
+
141
186
 	soc@0 {
142
187
 		compatible = "simple-bus";
143
188
 		#address-cells = <1>;
144
189
 		#size-cells = <1>;
145
190
 		ranges = <0 0 0 0xffffffff>;
191
+
192
+		spi0: spi@54006000 {
193
+			compatible = "socionext,uniphier-scssi";
194
+			status = "disabled";
195
+			reg = <0x54006000 0x100>;
196
+			#address-cells = <1>;
197
+			#size-cells = <0>;
198
+			interrupts = <0 39 4>;
199
+			pinctrl-names = "default";
200
+			pinctrl-0 = <&pinctrl_spi0>;
201
+			clocks = <&peri_clk 11>;
202
+			resets = <&peri_rst 11>;
203
+		};
204
+
205
+		spi1: spi@54006100 {
206
+			compatible = "socionext,uniphier-scssi";
207
+			status = "disabled";
208
+			reg = <0x54006100 0x100>;
209
+			#address-cells = <1>;
210
+			#size-cells = <0>;
211
+			interrupts = <0 216 4>;
212
+			pinctrl-names = "default";
213
+			pinctrl-0 = <&pinctrl_spi1>;
214
+			clocks = <&peri_clk 12>;
215
+			resets = <&peri_rst 12>;
216
+		};
146
217
 
147
218
 		serial0: serial@54006800 {
148
219
 			compatible = "socionext,uniphier-uart";
..
..
@@ -322,7 +393,7 @@
322
393
 			};
323
394
 		};
324
395
 
325
-		emmc: sdhc@5a000000 {
396
+		emmc: mmc@5a000000 {
326
397
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
327
398
 			reg = <0x5a000000 0x400>;
328
399
 			interrupts = <0 78 4>;
..
..
@@ -339,6 +410,24 @@
339
410
 			cdns,phy-input-delay-mmc-ddr = <3>;
340
411
 			cdns,phy-dll-delay-sdclk = <21>;
341
412
 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
413
+		};
414
+
415
+		sd: mmc@5a400000 {
416
+			compatible = "socionext,uniphier-sd-v3.1.1";
417
+			status = "disabled";
418
+			reg = <0x5a400000 0x800>;
419
+			interrupts = <0 76 4>;
420
+			pinctrl-names = "default", "uhs";
421
+			pinctrl-0 = <&pinctrl_sd>;
422
+			pinctrl-1 = <&pinctrl_sd_uhs>;
423
+			clocks = <&sd_clk 0>;
424
+			reset-names = "host";
425
+			resets = <&sd_rst 0>;
426
+			bus-width = <4>;
427
+			cap-sd-highspeed;
428
+			sd-uhs-sdr12;
429
+			sd-uhs-sdr25;
430
+			sd-uhs-sdr50;
342
431
 		};
343
432
 
344
433
 		soc_glue: soc-glue@5f800000 {
..
..
@@ -366,10 +455,62 @@
366
455
 			efuse@200 {
367
456
 				compatible = "socionext,uniphier-efuse";
368
457
 				reg = <0x200 0x68>;
458
+				#address-cells = <1>;
459
+				#size-cells = <1>;
460
+
461
+				/* USB cells */
462
+				usb_rterm0: trim@54,4 {
463
+					reg = <0x54 1>;
464
+					bits = <4 2>;
465
+				};
466
+				usb_rterm1: trim@55,4 {
467
+					reg = <0x55 1>;
468
+					bits = <4 2>;
469
+				};
470
+				usb_rterm2: trim@58,4 {
471
+					reg = <0x58 1>;
472
+					bits = <4 2>;
473
+				};
474
+				usb_rterm3: trim@59,4 {
475
+					reg = <0x59 1>;
476
+					bits = <4 2>;
477
+				};
478
+				usb_sel_t0: trim@54,0 {
479
+					reg = <0x54 1>;
480
+					bits = <0 4>;
481
+				};
482
+				usb_sel_t1: trim@55,0 {
483
+					reg = <0x55 1>;
484
+					bits = <0 4>;
485
+				};
486
+				usb_sel_t2: trim@58,0 {
487
+					reg = <0x58 1>;
488
+					bits = <0 4>;
489
+				};
490
+				usb_sel_t3: trim@59,0 {
491
+					reg = <0x59 1>;
492
+					bits = <0 4>;
493
+				};
494
+				usb_hs_i0: trim@56,0 {
495
+					reg = <0x56 1>;
496
+					bits = <0 4>;
497
+				};
498
+				usb_hs_i2: trim@5a,0 {
499
+					reg = <0x5a 1>;
500
+					bits = <0 4>;
501
+				};
369
502
 			};
370
503
 		};
371
504
 
372
-		aidet: aidet@5fc20000 {
505
+		xdmac: dma-controller@5fc10000 {
506
+			compatible = "socionext,uniphier-xdmac";
507
+			reg = <0x5fc10000 0x5300>;
508
+			interrupts = <0 188 4>;
509
+			dma-channels = <16>;
510
+			#dma-cells = <2>;
511
+		};
512
+
513
+		aidet: interrupt-controller@5fc20000 {
373
514
 			compatible = "socionext,uniphier-pxs3-aidet";
374
515
 			reg = <0x5fc20000 0x200>;
375
516
 			interrupt-controller;
..
..
@@ -402,6 +543,13 @@
402
543
 
403
544
 			watchdog {
404
545
 				compatible = "socionext,uniphier-wdt";
546
+			};
547
+
548
+			pvtctl: pvtctl {
549
+				compatible = "socionext,uniphier-pxs3-thermal";
550
+				interrupts = <0 3 4>;
551
+				#thermal-sensor-cells = <0>;
552
+				socionext,tmod-calibration = <0x0f22 0x68ee>;
405
553
 			};
406
554
 		};
407
555
 
..
..
@@ -447,16 +595,265 @@
447
595
 			};
448
596
 		};
449
597
 
450
-		nand: nand@68000000 {
598
+		usb0: usb@65a00000 {
599
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
600
+			status = "disabled";
601
+			reg = <0x65a00000 0xcd00>;
602
+			interrupt-names = "dwc_usb3";
603
+			interrupts = <0 134 4>;
604
+			pinctrl-names = "default";
605
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
606
+			clock-names = "ref", "bus_early", "suspend";
607
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
608
+			resets = <&usb0_rst 15>;
609
+			phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
610
+			       <&usb0_ssphy0>, <&usb0_ssphy1>;
611
+			dr_mode = "host";
612
+		};
613
+
614
+		usb-glue@65b00000 {
615
+			compatible = "socionext,uniphier-pxs3-dwc3-glue",
616
+				     "simple-mfd";
617
+			#address-cells = <1>;
618
+			#size-cells = <1>;
619
+			ranges = <0 0x65b00000 0x400>;
620
+
621
+			usb0_rst: reset@0 {
622
+				compatible = "socionext,uniphier-pxs3-usb3-reset";
623
+				reg = <0x0 0x4>;
624
+				#reset-cells = <1>;
625
+				clock-names = "link";
626
+				clocks = <&sys_clk 12>;
627
+				reset-names = "link";
628
+				resets = <&sys_rst 12>;
629
+			};
630
+
631
+			usb0_vbus0: regulator@100 {
632
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
633
+				reg = <0x100 0x10>;
634
+				clock-names = "link";
635
+				clocks = <&sys_clk 12>;
636
+				reset-names = "link";
637
+				resets = <&sys_rst 12>;
638
+			};
639
+
640
+			usb0_vbus1: regulator@110 {
641
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
642
+				reg = <0x110 0x10>;
643
+				clock-names = "link";
644
+				clocks = <&sys_clk 12>;
645
+				reset-names = "link";
646
+				resets = <&sys_rst 12>;
647
+			};
648
+
649
+			usb0_hsphy0: hs-phy@200 {
650
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
651
+				reg = <0x200 0x10>;
652
+				#phy-cells = <0>;
653
+				clock-names = "link", "phy";
654
+				clocks = <&sys_clk 12>, <&sys_clk 16>;
655
+				reset-names = "link", "phy";
656
+				resets = <&sys_rst 12>, <&sys_rst 16>;
657
+				vbus-supply = <&usb0_vbus0>;
658
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
659
+				nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
660
+					      <&usb_hs_i0>;
661
+			};
662
+
663
+			usb0_hsphy1: hs-phy@210 {
664
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
665
+				reg = <0x210 0x10>;
666
+				#phy-cells = <0>;
667
+				clock-names = "link", "phy";
668
+				clocks = <&sys_clk 12>, <&sys_clk 16>;
669
+				reset-names = "link", "phy";
670
+				resets = <&sys_rst 12>, <&sys_rst 16>;
671
+				vbus-supply = <&usb0_vbus1>;
672
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
673
+				nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
674
+					      <&usb_hs_i0>;
675
+			};
676
+
677
+			usb0_ssphy0: ss-phy@300 {
678
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
679
+				reg = <0x300 0x10>;
680
+				#phy-cells = <0>;
681
+				clock-names = "link", "phy";
682
+				clocks = <&sys_clk 12>, <&sys_clk 17>;
683
+				reset-names = "link", "phy";
684
+				resets = <&sys_rst 12>, <&sys_rst 17>;
685
+				vbus-supply = <&usb0_vbus0>;
686
+			};
687
+
688
+			usb0_ssphy1: ss-phy@310 {
689
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
690
+				reg = <0x310 0x10>;
691
+				#phy-cells = <0>;
692
+				clock-names = "link", "phy";
693
+				clocks = <&sys_clk 12>, <&sys_clk 18>;
694
+				reset-names = "link", "phy";
695
+				resets = <&sys_rst 12>, <&sys_rst 18>;
696
+				vbus-supply = <&usb0_vbus1>;
697
+			};
698
+		};
699
+
700
+		usb1: usb@65c00000 {
701
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
702
+			status = "disabled";
703
+			reg = <0x65c00000 0xcd00>;
704
+			interrupt-names = "dwc_usb3";
705
+			interrupts = <0 137 4>;
706
+			pinctrl-names = "default";
707
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
708
+			clock-names = "ref", "bus_early", "suspend";
709
+			clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
710
+			resets = <&usb1_rst 15>;
711
+			phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
712
+			       <&usb1_ssphy0>;
713
+			dr_mode = "host";
714
+		};
715
+
716
+		usb-glue@65d00000 {
717
+			compatible = "socionext,uniphier-pxs3-dwc3-glue",
718
+				     "simple-mfd";
719
+			#address-cells = <1>;
720
+			#size-cells = <1>;
721
+			ranges = <0 0x65d00000 0x400>;
722
+
723
+			usb1_rst: reset@0 {
724
+				compatible = "socionext,uniphier-pxs3-usb3-reset";
725
+				reg = <0x0 0x4>;
726
+				#reset-cells = <1>;
727
+				clock-names = "link";
728
+				clocks = <&sys_clk 13>;
729
+				reset-names = "link";
730
+				resets = <&sys_rst 13>;
731
+			};
732
+
733
+			usb1_vbus0: regulator@100 {
734
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
735
+				reg = <0x100 0x10>;
736
+				clock-names = "link";
737
+				clocks = <&sys_clk 13>;
738
+				reset-names = "link";
739
+				resets = <&sys_rst 13>;
740
+			};
741
+
742
+			usb1_vbus1: regulator@110 {
743
+				compatible = "socionext,uniphier-pxs3-usb3-regulator";
744
+				reg = <0x110 0x10>;
745
+				clock-names = "link";
746
+				clocks = <&sys_clk 13>;
747
+				reset-names = "link";
748
+				resets = <&sys_rst 13>;
749
+			};
750
+
751
+			usb1_hsphy0: hs-phy@200 {
752
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
753
+				reg = <0x200 0x10>;
754
+				#phy-cells = <0>;
755
+				clock-names = "link", "phy", "phy-ext";
756
+				clocks = <&sys_clk 13>, <&sys_clk 20>,
757
+					 <&sys_clk 14>;
758
+				reset-names = "link", "phy";
759
+				resets = <&sys_rst 13>, <&sys_rst 20>;
760
+				vbus-supply = <&usb1_vbus0>;
761
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
762
+				nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
763
+					      <&usb_hs_i2>;
764
+			};
765
+
766
+			usb1_hsphy1: hs-phy@210 {
767
+				compatible = "socionext,uniphier-pxs3-usb3-hsphy";
768
+				reg = <0x210 0x10>;
769
+				#phy-cells = <0>;
770
+				clock-names = "link", "phy", "phy-ext";
771
+				clocks = <&sys_clk 13>, <&sys_clk 20>,
772
+					 <&sys_clk 14>;
773
+				reset-names = "link", "phy";
774
+				resets = <&sys_rst 13>, <&sys_rst 20>;
775
+				vbus-supply = <&usb1_vbus1>;
776
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
777
+				nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
778
+					      <&usb_hs_i2>;
779
+			};
780
+
781
+			usb1_ssphy0: ss-phy@300 {
782
+				compatible = "socionext,uniphier-pxs3-usb3-ssphy";
783
+				reg = <0x300 0x10>;
784
+				#phy-cells = <0>;
785
+				clock-names = "link", "phy", "phy-ext";
786
+				clocks = <&sys_clk 13>, <&sys_clk 21>,
787
+					 <&sys_clk 14>;
788
+				reset-names = "link", "phy";
789
+				resets = <&sys_rst 13>, <&sys_rst 21>;
790
+				vbus-supply = <&usb1_vbus0>;
791
+			};
792
+		};
793
+
794
+		pcie: pcie@66000000 {
795
+			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
796
+			status = "disabled";
797
+			reg-names = "dbi", "link", "config";
798
+			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
799
+			      <0x2fff0000 0x10000>;
800
+			#address-cells = <3>;
801
+			#size-cells = <2>;
802
+			clocks = <&sys_clk 24>;
803
+			resets = <&sys_rst 24>;
804
+			num-lanes = <1>;
805
+			num-viewport = <1>;
806
+			bus-range = <0x0 0xff>;
807
+			device_type = "pci";
808
+			ranges =
809
+			/* downstream I/O */
810
+				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
811
+			/* non-prefetchable memory */
812
+				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
813
+			#interrupt-cells = <1>;
814
+			interrupt-names = "dma", "msi";
815
+			interrupts = <0 224 4>, <0 225 4>;
816
+			interrupt-map-mask = <0 0 0 7>;
817
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */
818
+					<0 0 0 2 &pcie_intc 1>,	/* INTB */
819
+					<0 0 0 3 &pcie_intc 2>,	/* INTC */
820
+					<0 0 0 4 &pcie_intc 3>;	/* INTD */
821
+			phy-names = "pcie-phy";
822
+			phys = <&pcie_phy>;
823
+
824
+			pcie_intc: legacy-interrupt-controller {
825
+				interrupt-controller;
826
+				#interrupt-cells = <1>;
827
+				interrupt-parent = <&gic>;
828
+				interrupts = <0 226 4>;
829
+			};
830
+		};
831
+
832
+		pcie_phy: phy@66038000 {
833
+			compatible = "socionext,uniphier-pxs3-pcie-phy";
834
+			reg = <0x66038000 0x4000>;
835
+			#phy-cells = <0>;
836
+			clock-names = "link";
837
+			clocks = <&sys_clk 24>;
838
+			reset-names = "link";
839
+			resets = <&sys_rst 24>;
840
+			socionext,syscon = <&soc_glue>;
841
+		};
842
+
843
+		nand: nand-controller@68000000 {
451
844
 			compatible = "socionext,uniphier-denali-nand-v5b";
452
845
 			status = "disabled";
453
846
 			reg-names = "nand_data", "denali_reg";
454
847
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
848
+			#address-cells = <1>;
849
+			#size-cells = <0>;
455
850
 			interrupts = <0 65 4>;
456
851
 			pinctrl-names = "default";
457
852
 			pinctrl-0 = <&pinctrl_nand>;
458
-			clocks = <&sys_clk 2>;
459
-			resets = <&sys_rst 2>;
853
+			clock-names = "nand", "nand_x", "ecc";
854
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
855
+			reset-names = "nand", "reg";
856
+			resets = <&sys_rst 2>, <&sys_rst 2>;
460
857
 		};
461
858
 	};
462
859
 };