~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8
9	9	#include <dt-bindings/gpio/gpio.h>
10	10	#include <dt-bindings/pinctrl/rockchip.h>
	11	+#include <dt-bindings/display/media-bus-format.h>
11	12	#include "rk3568.dtsi"
12	13	#include "rk3568-evb.dtsi"
13	14
..	..	@@ -17,7 +18,8 @@
17	18
18	19	rk_headset: rk-headset {
19	20	compatible = "rockchip_headset";
20		- headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
	21	+ headset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
	22	+ spk_ctl_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;//AMP_SD_GPIO4_C2_3V3
21	23	pinctrl-names = "default";
22	24	pinctrl-0 = <&hp_det>;
23	25	};
..	..	@@ -32,15 +34,6 @@
32	34	vin-supply = <&vcc3v3_sys>;
33	35	};
34	36
35		- vcc3v3_vga: vcc3v3-vga {
36		- compatible = "regulator-fixed";
37		- regulator-name = "vcc3v3_vga";
38		- regulator-always-on;
39		- regulator-boot-on;
40		- gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
41		- enable-active-high;
42		- vin-supply = <&vcc3v3_sys>;
43		- };
44	37
45	38	pcie30_avdd0v9: pcie30-avdd0v9 {
46	39	compatible = "regulator-fixed";
..	..	@@ -67,7 +60,9 @@
67	60	regulator-name = "vcc3v3_pcie";
68	61	regulator-min-microvolt = <3300000>;
69	62	regulator-max-microvolt = <3300000>;
	63	+ regulator-always-on;
70	64	enable-active-high;
	65	+ regulator-boot-on;
71	66	gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
72	67	startup-delay-us = <5000>;
73	68	vin-supply = <&dc_12v>;
..	..	@@ -82,7 +77,7 @@
82	77	regulator-max-microvolt = <3300000>;
83	78	vin-supply = <&vcc5v0_sys>;
84	79	};
85		-
	80	+#if 0
86	81	vcc_camera: vcc-camera-regulator {
87	82	compatible = "regulator-fixed";
88	83	gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
..	..	@@ -92,43 +87,191 @@
92	87	enable-active-high;
93	88	regulator-always-on;
94	89	regulator-boot-on;
95		-
96	90	};
	91	+#endif
97	92
	93	+ leds: leds {
	94	+ compatible = "gpio-leds";
	95	+ sig_led: sig_led {
	96	+ gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
	97	+ default-state = "on";
	98	+ };
	99	+ };
	100	+
	101	+ leds: leds {
	102	+ compatible = "gpio-leds";
	103	+ err_led: err_led {
	104	+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
	105	+ default-state = "on";
	106	+ };
	107	+ };
	108	+
	109	+
	110	+ ndj_io_init {
	111	+ compatible = "nk_io_control";
	112	+ pinctrl-names = "default";
	113	+ pinctrl-0 = <&nk_io_gpio>;
	114	+
	115	+ //gpio_op0 = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
	116	+
	117	+ vcc_5v {
	118	+ gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	119	+ gpio_function = <0>;
	120	+ };
	121	+
	122	+ vcc_12v {
	123	+ gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
	124	+ gpio_function = <0>;
	125	+ };
	126	+
	127	+ vcc_3.3v {
	128	+ gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
	129	+ gpio_function = <0>;
	130	+ };
	131	+
	132	+ hub_host2_rst {
	133	+ gpio_num = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
	134	+ gpio_function = <3>;
	135	+ };
	136	+
	137	+ hub_host3 {
	138	+ gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
	139	+ gpio_function = <0>;
	140	+ };
	141	+
	142	+ wake_4g {
	143	+ gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; //4G_WAKEUP_GPIO01_B1_3V3
	144	+ gpio_function = <0>;
	145	+ };
	146	+
	147	+ air_mode_4g {
	148	+ gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; //4G_AIR_MODE_GPIO01_B0_3V3
	149	+ gpio_function = <0>;
	150	+ };
	151	+
	152	+ reset_4g {
	153	+ gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; //4G_RST_GPIO01_B2_3V3
	154	+ gpio_function = <3>;
	155	+ };
	156	+
	157	+ en_4g {
	158	+ gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
	159	+ gpio_function = <0>;
	160	+ };
	161	+
	162	+ //gpio99 {
	163	+ // gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;//HP_EN_GPIO3_A6_3V3
	164	+ // gpio_function = <1>;
	165	+ //};
	166	+
	167	+ wifi_power_en {
	168	+ gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	169	+ gpio_function = <0>;
	170	+ };
	171	+ #if 0
	172	+ do1 {
	173	+ gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
	174	+ gpio_function = <0>;
	175	+ };
	176	+
	177	+ do2 {
	178	+ gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
	179	+ gpio_function = <0>;
	180	+ };
	181	+
	182	+ do3 {
	183	+ gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
	184	+ gpio_function = <0>;
	185	+ };
	186	+
	187	+ do4 {
	188	+ gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
	189	+ gpio_function = <0>;
	190	+ };
	191	+
	192	+ do5 {
	193	+ gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
	194	+ gpio_function = <0>;
	195	+ };
	196	+
	197	+ do6 {
	198	+ gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
	199	+ gpio_function = <0>;
	200	+ };
	201	+
	202	+ do7 {
	203	+ gpio_num = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
	204	+ gpio_function = <0>;
	205	+ };
	206	+
	207	+ di1 {
	208	+ gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
	209	+ gpio_function = <1>;
	210	+ };
	211	+ #endif
	212	+ };
	213	+#if 0
98	214	nk_io_init {
99	215	compatible = "nk_io_control";
100		- hub_host2_5v_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; //USB_HOST_PWREN_H_GPIO0_A6
101		- usb_en_oc_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; //USB_EN_OC_GPIO0_A5
102		- lcd_bk_en_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
103		- lcd_pwblk_gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
104		- vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
	216	+// vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
105	217	hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
106	218	hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
107		-// hub_host3_5V_rest_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
108	219	vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
109	220	vcc_12v_io = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
110	221	en_4g_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
111	222	reset_4g_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; //4G_RST_GPIO01_B2_3V3
112	223	air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
113	224	wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
114		-
115		- edp_enable_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
116		- edp_gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; //7511_GPIO0-GPIO3_D2
117		- edp_gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; //7511_GPIO1-GPIO3_D3
118		- edp_gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //7511_GPIO2-GPIO3_D4
119		- edp_gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; //7511_GPIO3-GPIO3_D5
120		- edp_reset = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
121		-// tp_reset = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
122		-// vddio_mipi = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
123		-
124		- wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
125		-
126		- // pinctrl-names = "default";
127		-// pinctrl-0 = <&nk_io_gpio>;
128		- nodka_lvds = <9>;
	225	+ hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
	226	+// spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
	227	+ wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	228	+// pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4
	229	+ pinctrl-names = "default";
	230	+ pinctrl-0 = <&nk_io_gpio>;
129	231	};
	232	+#endif
	233	+ panel: panel {
	234	+ compatible = "simple-panel";
	235	+ backlight = <&backlight>;
	236	+ power-supply = <&vcc3v3_lcd0_n>;
	237	+ enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; //LCD0_VDD_H_GPIO2_D4
	238	+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
	239	+ edp-bl-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	240	+ edp-bl-en = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	241	+ bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
	242	+ bpc = <8>;
	243	+ prepare-delay-ms = <200>;
	244	+ enable-delay-ms = <20>;
	245	+ lvds-gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2
	246	+ lvds-gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3
	247	+ lvds-gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4
	248	+ lvds-gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
	249	+ nodka-lvds = <15>;
130	250
131		-
	251	+ display-timings {
	252	+ native-mode = <&timing>;
	253	+ timing: timing {
	254	+ clock-frequency = <72500000>;
	255	+ hactive = <1280>;
	256	+ vactive = <800>;
	257	+ hfront-porch = <70>;
	258	+ hsync-len = <2>;
	259	+ hback-porch = <88>;
	260	+ vfront-porch = <7>;
	261	+ vsync-len = <4>;
	262	+ vback-porch = <17>;
	263	+ hsync-active = <21>;
	264	+ vsync-active = <0>;
	265	+ de-active = <0>;
	266	+ pixelclk-active = <0>;
	267	+ };
	268	+ };
	269	+ ports {
	270	+ panel_in_lvds: endpoint {
	271	+ remote-endpoint = <&lvds_out>;
	272	+ };
	273	+ };
	274	+ };
132	275	};
133	276
134	277	&combphy0_us {
..	..	@@ -144,11 +287,11 @@
144	287	};
145	288
146	289	&csi2_dphy_hw {
147		- status = "okay";
	290	+ status = "disabled";
148	291	};
149	292
150	293	&csi2_dphy0 {
151		- status = "okay";
	294	+ status = "disabled";
152	295
153	296	ports {
154	297	#address-cells = <1>;
..	..	@@ -191,8 +334,12 @@
191	334	* video_phy0 needs to be enabled
192	335	* when dsi0 is enabled
193	336	*/
	337	+&video_phy0 {
	338	+ status = "disabled";
	339	+};
	340	+
194	341	&dsi0 {
195		- status = "okay";
	342	+ status = "disabled";
196	343	};
197	344
198	345	&dsi0_in_vp0 {
..	..	@@ -200,7 +347,7 @@
200	347	};
201	348
202	349	&dsi0_in_vp1 {
203		- status = "okay";
	350	+ status = "disabled";
204	351	};
205	352
206	353	&dsi0_panel {
..	..	@@ -211,6 +358,10 @@
211	358	* video_phy1 needs to be enabled
212	359	* when dsi1 is enabled
213	360	*/
	361	+
	362	+&video_phy1 {
	363	+ status = "disabled";
	364	+};
214	365	&dsi1 {
215	366	status = "disabled";
216	367	};
..	..	@@ -224,31 +375,117 @@
224	375	};
225	376
226	377	&dsi1_panel {
227		- power-supply = <&vcc3v3_lcd1_n>;
	378	+// power-supply = <&vcc3v3_lcd1_n>; //MIPI_3V3EN_GPIO3_A3_d_3V3
	379	+ vddio-mipi = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; //MIPI_EN_1V8_GPIO3_A4_d_3V3
	380	+ reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; //MIPI_RST_L_GPIO3_C7
	381	+ vcc-5v-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	382	+ pinctrl-names = "default";
	383	+ pinctrl-0 = <&lcd1_rst_gpio>;
228	384	};
229	385
	386	+&route_dsi1 {
	387	+ status = "disabled";
	388	+ connect = <&vp1_out_dsi1>;
	389	+};
	390	+
	391	+
	392	+/*
	393	+* edp_start
	394	+*/
	395	+
230	396	&edp {
231		- hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
232		- status = "okay";
	397	+ force-hpd;
	398	+ status = "disabled";
233	399	};
234	400
235	401	&edp_phy {
236		- status = "okay";
	402	+ status = "disabled";
237	403	};
238	404
239	405	&edp_in_vp0 {
240		- status = "okay";
	406	+ status = "disabled";
241	407	};
242	408
243	409	&edp_in_vp1 {
	410	+ status = "disabled";
	411	+
	412	+};
	413	+
	414	+&route_edp {
	415	+ status = "disabled";
	416	+ connect = <&vp1_out_edp>;
	417	+};
	418	+
	419	+&route_edp {
244	420	status = "disabled";
245	421	};
	422	+
	423	+&lvds {
	424	+ status = "disabled";
	425	+ ports {
	426	+ port@1 {
	427	+ reg = <1>;
	428	+ lvds_out:endpoint {
	429	+ remote-endpoint = <&panel_in_lvds>;
	430	+ };
	431	+ };
	432	+ };
	433	+};
	434	+
	435	+&route_lvds{
	436	+ status = "okay";
	437	+ connect = <&vp1_out_lvds>;
	438	+};
	439	+
	440	+&lvds_in_vp1 {
	441	+ status = "disabled";
	442	+};
	443	+
	444	+/*
	445	+* edp_end
	446	+*/
	447	+
	448	+/*
	449	+* Hdmi_start
	450	+*/
	451	+
	452	+&hdmi {
	453	+ status = "okay";
	454	+ rockchip,phy-table =
	455	+ <92812500 0x8009 0x0000 0x0270>,
	456	+ <165000000 0x800b 0x0000 0x026d>,
	457	+ <185625000 0x800b 0x0000 0x01ed>,
	458	+ <297000000 0x800b 0x0000 0x01ad>,
	459	+ <594000000 0x8029 0x0000 0x0088>,
	460	+ <000000000 0x0000 0x0000 0x0000>;
	461	+};
	462	+
	463	+&route_hdmi {
	464	+ status = "okay";
	465	+ connect = <&vp0_out_hdmi>;
	466	+};
	467	+
	468	+&hdmi_in_vp0 {
	469	+ status = "okay";
	470	+};
	471	+
	472	+&hdmi_in_vp1 {
	473	+ status = "disabled";
	474	+};
	475	+
	476	+&hdmi_sound {
	477	+ status = "okay";
	478	+};
	479	+
	480	+/*
	481	+ * Hdmi_END
	482	+*/
246	483
247	484	&gmac0 {
248	485	phy-mode = "rgmii";
249	486	clock_in_out = "output";
250	487
251		- snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	488	+ snps,reset-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
252	489	snps,reset-active-low;
253	490	/* Reset time is 20ms, 100ms for rtl8211f */
254	491	snps,reset-delays-us = <0 20000 100000>;
..	..	@@ -268,7 +505,9 @@
268	505	rx_delay = <0x2f>;
269	506
270	507	phy-handle = <&rgmii_phy0>;
	508	+
271	509	status = "disabled";
	510	+
272	511	};
273	512
274	513	&gmac1 {
..	..	@@ -302,9 +541,7 @@
302	541	* power-supply should switche to vcc3v3_lcd1_n
303	542	* when mipi panel is connected to dsi1.
304	543	*/
305		-&gt1x {
306		- power-supply = <&vcc3v3_lcd0_n>;
307		-};
	544	+
308	545
309	546	&i2c3 {
310	547	status = "okay";
..	..	@@ -320,13 +557,10 @@
320	557	compatible = "nk_mcu";
321	558	reg = <0x15>;
322	559	};
323		-
324		-
325		-
326	560	};
327	561
328	562	&i2c4 {
329		- status = "okay";
	563	+ status = "disabled";
330	564	gc8034: gc8034@37 {
331	565	compatible = "galaxycore,gc8034";
332	566	status = "okay";
..	..	@@ -338,7 +572,6 @@
338	572	reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
339	573	pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
340	574	rockchip,grf = <&grf>;
341		- power-domains = <&power RK3568_PD_VI>;
342	575	rockchip,camera-module-index = <0>;
343	576	rockchip,camera-module-facing = "back";
344	577	rockchip,camera-module-name = "RK-CMK-8M-2-v1";
..	..	@@ -372,7 +605,7 @@
372	605	};
373	606	};
374	607	ov5695: ov5695@36 {
375		- status = "okay";
	608	+ status = "disabled";
376	609	compatible = "ovti,ov5695";
377	610	reg = <0x36>;
378	611	clocks = <&cru CLK_CIF_OUT>;
..	..	@@ -395,6 +628,19 @@
395	628	};
396	629	};
397	630
	631	+&i2c5 {
	632	+ status = "okay";
	633	+
	634	+ hym8563: hym8563@51 {
	635	+ compatible = "haoyu,hym8563";
	636	+ reg = <0x51>;
	637	+ #clock-cells = <0>;
	638	+ clock-frequency = <32768>;
	639	+ clock-output-names = "xin32k";
	640	+ /* rtc_int is not connected */
	641	+ };
	642	+};
	643	+
398	644	&mdio0 {
399	645	rgmii_phy0: phy@0 {
400	646	compatible = "ethernet-phy-ieee802.3-c22";
..	..	@@ -409,73 +655,98 @@
409	655	};
410	656	};
411	657
412		-&video_phy0 {
413		- status = "okay";
414		-};
415	658
416		-&video_phy1 {
	659	+
	660	+&pcie30phy {
417	661	status = "disabled";
418	662	};
419	663
420		-&pcie30phy {
421		- status = "okay";
422		-};
423		-
424		-&pcie3x2 {
425		- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	664	+&pcie2x1 {
	665	+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
426	666	vpcie3v3-supply = <&vcc3v3_pcie>;
427	667	status = "okay";
428	668	};
429	669
430	670	&pinctrl {
431		- cam {
432		- camera_pwr: camera-pwr {
433		- rockchip,pins =
434		- /* camera power en */
435		- <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
436		- };
437		- };
	671	+// cam {
	672	+// camera_pwr: camera-pwr {
	673	+// rockchip,pins =
	674	+// /* camera power en */
	675	+// <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
	676	+// };
	677	+// };
438	678	headphone {
439	679	hp_det: hp-det {
440		- rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
	680	+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>,
	681	+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
441	682	};
442	683	};
443	684
444	685	wireless-wlan {
445	686	wifi_host_wake_irq: wifi-host-wake-irq {
446		- rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
	687	+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
447	688	};
448	689	};
449	690
450	691	wireless-bluetooth {
451		- uart8_gpios: uart8-gpios {
452		- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	692	+ uart1_gpios: uart1-gpios {
	693	+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
453	694	};
454	695	};
455		-
456		- nk_io_gpio: nk_io_gpio_col{
457		- rockchip,pins =
458		- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
459		- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
460		- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
461		- <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
462		- <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>,
463		- <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
464		- <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
465		- <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
	696	+
	697	+ lcd1 {
	698	+ lcd1_rst_gpio: lcd1-rst-gpio {
	699	+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
	700	+ };
	701	+ };
	702	+
	703	+ nk_io_init{
	704	+ nk_io_gpio: nk-io-gpio{
	705	+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	706	+ <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
	707	+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
	708	+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	709	+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	710	+ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
	711	+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
	712	+ <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	713	+ <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	714	+ <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
	715	+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
	716	+ <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	717	+ <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
	718	+ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,
	719	+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
	720	+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
	721	+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
	722	+ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
	723	+ <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
	724	+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B0_u_3V3 DO1
	725	+ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B3_u_3V3 DO2
	726	+ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B4_u_3V3 DO3
	727	+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B5_u_3V3 DO4
	728	+ <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B6_u_3V3 DO5
	729	+
	730	+ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C0_d_3V3 DI1_1
	731	+ <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C1_d_3V3 DI2_1
	732	+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C2_d_3V3 DI3_1
	733	+ <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C3_d_3V3 DI4_1
	734	+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C5_d_3V3 DI5_1
	735	+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	736	+ };
466	737	};
467	738	};
468	739
469	740	&rkisp {
470		- status = "okay";
	741	+ status = "disabled";
471	742	};
472	743
473	744	&rkisp_mmu {
474		- status = "okay";
	745	+ status = "disabled";
475	746	};
476	747
477	748	&rkisp_vir0 {
478		- status = "okay";
	749	+ status = "disabled";
479	750
480	751	port {
481	752	#address-cells = <1>;
..	..	@@ -488,34 +759,30 @@
488	759	};
489	760	};
490	761
491		-&route_dsi0 {
492		- status = "okay";
493		- connect = <&vp1_out_dsi0>;
494		-};
495	762
496		-&route_edp {
497		- status = "okay";
498		- connect = <&vp0_out_edp>;
499		-};
500	763
501	764	&sata2 {
502	765	status = "okay";
503	766	};
504	767
505	768	&sdmmc2 {
506		- max-frequency = <150000000>;
507		- supports-sdio;
508		- bus-width = <4>;
509		- disable-wp;
510		- cap-sd-highspeed;
511		- cap-sdio-irq;
512		- keep-power-in-suspend;
513		- mmc-pwrseq = <&sdio_pwrseq>;
514		- non-removable;
515		- pinctrl-names = "default";
516		- pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
517		- sd-uhs-sdr104;
518		- status = "okay";
	769	+ status = "disabled";
	770	+};
	771	+
	772	+&sdmmc1 {
	773	+ max-frequency = <150000000>;
	774	+ supports-sdio;
	775	+ bus-width = <4>;
	776	+ disable-wp;
	777	+ cap-sd-highspeed;
	778	+ cap-sdio-irq;
	779	+ keep-power-in-suspend;
	780	+ mmc-pwrseq = <&sdio_pwrseq>;
	781	+ non-removable;
	782	+ pinctrl-names = "default";
	783	+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
	784	+ sd-uhs-sdr104;
	785	+ status = "okay";
519	786	};
520	787
521	788	&spdif_8ch {
..	..	@@ -530,15 +797,6 @@
530	797	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
531	798	};
532	799
533		-&vcc3v3_lcd0_n {
534		- gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
535		- enable-active-high;
536		-};
537		-
538		-&vcc3v3_lcd1_n {
539		- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
540		- enable-active-high;
541		-};
542	800
543	801	&wireless_wlan {
544	802	pinctrl-names = "default";
..	..	@@ -551,12 +809,53 @@
551	809	clocks = <&rk809 1>;
552	810	clock-names = "ext_clock";
553	811	//wifi-bt-power-toggle;
554		- uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
	812	+ uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
555	813	pinctrl-names = "default", "rts_gpio";
556		- pinctrl-0 = <&uart8m0_rtsn>;
557		- pinctrl-1 = <&uart8_gpios>;
558		- BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
559		- BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
560		- BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
	814	+ pinctrl-0 = <&uart1m0_rtsn>;
	815	+ pinctrl-1 = <&uart1_gpios>;
	816	+ BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
	817	+ BT,wake_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
	818	+ BT,wake_host_irq = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
	819	+ status = "disabled";
	820	+};
	821	+
	822	+&uart0 {
	823	+ status = "disabled";
	824	+};
	825	+
	826	+&uart1 {
	827	+ pinctrl-names = "default";
	828	+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
	829	+ status = "disabled";
	830	+};
	831	+
	832	+&uart3 {
561	833	status = "okay";
	834	+ pinctrl-0 = <&uart3m1_xfer>;
	835	+};
	836	+
	837	+&uart4 {
	838	+ status = "disabled";
	839	+ pinctrl-0 = <&uart4m1_xfer>;
	840	+};
	841	+
	842	+&uart5 {
	843	+ status = "okay";
	844	+ pinctrl-0 = <&uart5m1_xfer>;
	845	+};
	846	+
	847	+
	848	+&uart7 {
	849	+ status = "okay";
	850	+ pinctrl-0 = <&uart7m1_xfer>;
	851	+};
	852	+
	853	+&uart8 {
	854	+ status = "disabled";
	855	+ pinctrl-0 = <&uart8m1_xfer>;
	856	+};
	857	+
	858	+&uart9 {
	859	+ status = "disabled";
	860	+ pinctrl-0 = <&uart9m1_xfer>;
562	861	};