forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2
kernel/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
....@@ -15,17 +15,47 @@
1515 #address-cells = <1>;
1616 #size-cells = <0>;
1717
18
- cpu@0 {
18
+ cpu0: cpu@0 {
1919 device_type = "cpu";
20
- compatible = "arm,cortex-a72", "arm,armv8";
20
+ compatible = "arm,cortex-a72";
2121 reg = <0x000>;
2222 enable-method = "psci";
23
+ #cooling-cells = <2>;
24
+ clocks = <&cpu_clk 0>;
25
+ i-cache-size = <0xc000>;
26
+ i-cache-line-size = <64>;
27
+ i-cache-sets = <256>;
28
+ d-cache-size = <0x8000>;
29
+ d-cache-line-size = <64>;
30
+ d-cache-sets = <256>;
31
+ next-level-cache = <&l2>;
2332 };
24
- cpu@1 {
33
+ cpu1: cpu@1 {
2534 device_type = "cpu";
26
- compatible = "arm,cortex-a72", "arm,armv8";
35
+ compatible = "arm,cortex-a72";
2736 reg = <0x001>;
2837 enable-method = "psci";
38
+ #cooling-cells = <2>;
39
+ clocks = <&cpu_clk 0>;
40
+ i-cache-size = <0xc000>;
41
+ i-cache-line-size = <64>;
42
+ i-cache-sets = <256>;
43
+ d-cache-size = <0x8000>;
44
+ d-cache-line-size = <64>;
45
+ d-cache-sets = <256>;
46
+ next-level-cache = <&l2>;
2947 };
48
+
49
+ l2: l2-cache {
50
+ compatible = "cache";
51
+ cache-size = <0x80000>;
52
+ cache-line-size = <64>;
53
+ cache-sets = <512>;
54
+ };
55
+ };
56
+
57
+ thermal-zones {
58
+ /delete-node/ ap-thermal-cpu2;
59
+ /delete-node/ ap-thermal-cpu3;
3060 };
3161 };