add ax88772C AX88772C_eeprom_tools

hc

2024-05-10 61598093bbdd283a7edc367d900f223070ead8d2

 kernel/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
..
..
@@ -19,44 +19,44 @@
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 /*
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  * Instantiate the master CP110
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  */
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-#define CP110_NAME		cp0
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-#define CP110_BASE		f2000000
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-#define CP110_PCIE_IO_BASE	0xf9000000
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-#define CP110_PCIE_MEM_BASE	0xf6000000
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-#define CP110_PCIE0_BASE	f2600000
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-#define CP110_PCIE1_BASE	f2620000
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-#define CP110_PCIE2_BASE	f2640000
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+#define CP11X_NAME		cp0
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+#define CP11X_BASE		f2000000
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+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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+#define CP11X_PCIE0_BASE	f2600000
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+#define CP11X_PCIE1_BASE	f2620000
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+#define CP11X_PCIE2_BASE	f2640000
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 #include "armada-cp110.dtsi"
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-#undef CP110_NAME
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-#undef CP110_BASE
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-#undef CP110_PCIE_IO_BASE
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-#undef CP110_PCIE_MEM_BASE
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-#undef CP110_PCIE0_BASE
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-#undef CP110_PCIE1_BASE
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-#undef CP110_PCIE2_BASE
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+#undef CP11X_NAME
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+#undef CP11X_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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+#undef CP11X_PCIE0_BASE
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+#undef CP11X_PCIE1_BASE
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+#undef CP11X_PCIE2_BASE
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 /*
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  * Instantiate the slave CP110
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  */
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-#define CP110_NAME		cp1
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-#define CP110_BASE		f4000000
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-#define CP110_PCIE_IO_BASE	0xfd000000
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-#define CP110_PCIE_MEM_BASE	0xfa000000
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-#define CP110_PCIE0_BASE	f4600000
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-#define CP110_PCIE1_BASE	f4620000
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-#define CP110_PCIE2_BASE	f4640000
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+#define CP11X_NAME		cp1
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+#define CP11X_BASE		f4000000
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+#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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+#define CP11X_PCIE0_BASE	f4600000
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+#define CP11X_PCIE1_BASE	f4620000
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+#define CP11X_PCIE2_BASE	f4640000
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 #include "armada-cp110.dtsi"
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-#undef CP110_NAME
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-#undef CP110_BASE
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-#undef CP110_PCIE_IO_BASE
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-#undef CP110_PCIE_MEM_BASE
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-#undef CP110_PCIE0_BASE
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-#undef CP110_PCIE1_BASE
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-#undef CP110_PCIE2_BASE
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+#undef CP11X_NAME
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+#undef CP11X_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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+#undef CP11X_PCIE0_BASE
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+#undef CP11X_PCIE1_BASE
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+#undef CP11X_PCIE2_BASE
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 /* The 80x0 has two CP blocks, but uses only one block from each. */
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 &cp1_gpio1 {