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| 25 | 25 | ADI registers will make ADI controller registers chaos to lead incorrect results. |
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| 26 | 26 | Then we need one hardware spinlock to synchronize between the multiple subsystems. |
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| 27 | 27 | |
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| 28 | +The new version ADI controller supplies multiple master channels for different |
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| 29 | +subsystem accessing, that means no need to add hardware spinlock to synchronize, |
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| 30 | +thus change the hardware spinlock support to be optional to keep backward |
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| 31 | +compatibility. |
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| 32 | + |
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| 28 | 33 | Required properties: |
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| 29 | 34 | - compatible: Should be "sprd,sc9860-adi". |
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| 30 | 35 | - reg: Offset and length of ADI-SPI controller register space. |
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| 31 | | -- hwlocks: Reference to a phandle of a hwlock provider node. |
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| 32 | | -- hwlock-names: Reference to hwlock name strings defined in the same order |
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| 33 | | - as the hwlocks, should be "adi". |
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| 34 | 36 | - #address-cells: Number of cells required to define a chip select address |
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| 35 | 37 | on the ADI-SPI bus. Should be set to 1. |
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| 36 | 38 | - #size-cells: Size of cells required to define a chip select address size |
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| 37 | 39 | on the ADI-SPI bus. Should be set to 0. |
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| 38 | 40 | |
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| 39 | 41 | Optional properties: |
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| 42 | +- hwlocks: Reference to a phandle of a hwlock provider node. |
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| 43 | +- hwlock-names: Reference to hwlock name strings defined in the same order |
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| 44 | + as the hwlocks, should be "adi". |
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| 40 | 45 | - sprd,hw-channels: This is an array of channel values up to 49 channels. |
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| 41 | 46 | The first value specifies the hardware channel id which is used to |
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| 42 | 47 | transfer data triggered by hardware automatically, and the second |
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