| .. | .. |
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| 1 | | -* Mediatek Universal Asynchronous Receiver/Transmitter (UART) |
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| 1 | +* MediaTek Universal Asynchronous Receiver/Transmitter (UART) |
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| 2 | 2 | |
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| 3 | 3 | Required properties: |
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| 4 | 4 | - compatible should contain: |
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| .. | .. |
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| 9 | 9 | * "mediatek,mt6589-uart" for MT6589 compatible UARTS |
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| 10 | 10 | * "mediatek,mt6755-uart" for MT6755 compatible UARTS |
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| 11 | 11 | * "mediatek,mt6765-uart" for MT6765 compatible UARTS |
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| 12 | + * "mediatek,mt6779-uart" for MT6779 compatible UARTS |
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| 12 | 13 | * "mediatek,mt6795-uart" for MT6795 compatible UARTS |
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| 13 | 14 | * "mediatek,mt6797-uart" for MT6797 compatible UARTS |
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| 14 | 15 | * "mediatek,mt7622-uart" for MT7622 compatible UARTS |
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| 15 | 16 | * "mediatek,mt7623-uart" for MT7623 compatible UARTS |
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| 17 | + * "mediatek,mt7629-uart" for MT7629 compatible UARTS |
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| 16 | 18 | * "mediatek,mt8127-uart" for MT8127 compatible UARTS |
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| 17 | 19 | * "mediatek,mt8135-uart" for MT8135 compatible UARTS |
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| 18 | 20 | * "mediatek,mt8173-uart" for MT8173 compatible UARTS |
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| 21 | + * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS |
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| 22 | + * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS |
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| 23 | + * "mediatek,mt8516-uart" for MT8516 compatible UARTS |
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| 19 | 24 | * "mediatek,mt6577-uart" for MT6577 and all of the above |
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| 20 | 25 | |
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| 21 | 26 | - reg: The base address of the UART register bank. |
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| 22 | 27 | |
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| 23 | | -- interrupts: A single interrupt specifier. |
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| 28 | +- interrupts: |
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| 29 | + index 0: an interrupt specifier for the UART controller itself |
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| 30 | + index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to |
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| 31 | + support Rx in-band wake up. If one would like to use this feature, |
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| 32 | + one must create an addtional pinctrl to reconfigure Rx pin to normal |
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| 33 | + GPIO before suspend. |
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| 24 | 34 | |
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| 25 | 35 | - clocks : Must contain an entry for each entry in clock-names. |
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| 26 | 36 | See ../clocks/clock-bindings.txt for details. |
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| .. | .. |
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| 36 | 46 | uart0: serial@11006000 { |
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| 37 | 47 | compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; |
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| 38 | 48 | reg = <0x11006000 0x400>; |
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| 39 | | - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; |
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| 49 | + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, |
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| 50 | + <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>; |
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| 40 | 51 | clocks = <&uart_clk>, <&bus_clk>; |
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| 41 | 52 | clock-names = "baud", "bus"; |
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| 53 | + pinctrl-names = "default", "sleep"; |
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| 54 | + pinctrl-0 = <&uart_pin>; |
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| 55 | + pinctrl-1 = <&uart_pin_sleep>; |
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| 42 | 56 | }; |
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