| .. | .. |
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| 156 | 156 | break; |
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| 157 | 157 | } |
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| 158 | 158 | |
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| 159 | + /* For Coverity check */ |
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| 160 | + if (idx == DW_WDT_NUM_TOPS) |
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| 161 | + idx = 0; |
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| 162 | + |
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| 159 | 163 | return dw_wdt->timeouts[idx].sec; |
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| 160 | 164 | } |
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| 161 | 165 | |
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| .. | .. |
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| 178 | 182 | if (dw_wdt->timeouts[idx].top_val == top_val) |
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| 179 | 183 | break; |
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| 180 | 184 | } |
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| 185 | + |
|---|
| 186 | + if (idx == DW_WDT_NUM_TOPS) |
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| 187 | + idx = 0; |
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| 181 | 188 | |
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| 182 | 189 | /* |
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| 183 | 190 | * In IRQ mode due to the two stages counter, the actual timeout is |
|---|
| .. | .. |
|---|
| 638 | 645 | |
|---|
| 639 | 646 | ret = dw_wdt_init_timeouts(dw_wdt, dev); |
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| 640 | 647 | if (ret) |
|---|
| 641 | | - goto out_disable_clk; |
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| 648 | + goto out_assert_rst; |
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| 642 | 649 | |
|---|
| 643 | 650 | wdd = &dw_wdt->wdd; |
|---|
| 644 | 651 | wdd->ops = &dw_wdt_ops; |
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| .. | .. |
|---|
| 669 | 676 | |
|---|
| 670 | 677 | ret = watchdog_register_device(wdd); |
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| 671 | 678 | if (ret) |
|---|
| 672 | | - goto out_disable_pclk; |
|---|
| 679 | + goto out_assert_rst; |
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| 673 | 680 | |
|---|
| 674 | 681 | dw_wdt_dbgfs_init(dw_wdt); |
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| 675 | 682 | |
|---|
| 676 | 683 | return 0; |
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| 677 | 684 | |
|---|
| 685 | +out_assert_rst: |
|---|
| 686 | + reset_control_assert(dw_wdt->rst); |
|---|
| 687 | + |
|---|
| 678 | 688 | out_disable_pclk: |
|---|
| 679 | 689 | clk_disable_unprepare(dw_wdt->pclk); |
|---|
| 680 | 690 | |
|---|