修改GPIO导出默认初始值

hc

2024-10-16 50a212ec906f7524620675f0c57357691c26c81f

 kernel/drivers/mtd/nand/raw/brcmnand/brcmnand.h
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@@ -11,12 +11,25 @@
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 struct platform_device;
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 struct dev_pm_ops;
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+struct brcmnand_io_ops;
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+
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+/* Special register offset constant to intercept a non-MMIO access
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+ * to the flash cache register space. This is intentionally large
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+ * not to overlap with an existing offset.
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+ */
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+#define BRCMNAND_NON_MMIO_FC_ADDR	0xffffffff
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 struct brcmnand_soc {
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 	bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
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 	void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
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 	void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
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 				 bool is_param);
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+	const struct brcmnand_io_ops *ops;
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+};
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+
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+struct brcmnand_io_ops {
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+	u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset);
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+	void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset);
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 };
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 static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
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@@ -58,6 +71,22 @@
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 		writel_relaxed(val, addr);
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 }
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+static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc)
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+{
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+	return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
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+}
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+
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+static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset)
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+{
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+	return soc->ops->read_reg(soc, offset);
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+}
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+
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+static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,
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+				      u32 offset)
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+{
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+	soc->ops->write_reg(soc, val, offset);
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+}
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+
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 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
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 int brcmnand_remove(struct platform_device *pdev);
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