forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-16 50a212ec906f7524620675f0c57357691c26c81f 
 kernel/drivers/mtd/nand/raw/brcmnand/brcmnand.c
....@@ -25,6 +25,7 @@
2525 #include <linux/of.h>
2626 #include <linux/of_platform.h>
2727 #include <linux/slab.h>
28
+#include <linux/static_key.h>
2829 #include <linux/list.h>
2930 #include <linux/log2.h>
3031 
....@@ -207,6 +208,8 @@
207208 
208209 struct brcmnand_host;
209210 
211
+static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);
212
+
210213 struct brcmnand_controller {
211214 	struct device		*dev;
212215 	struct nand_controller	controller;
....@@ -265,6 +268,7 @@
265268 	const unsigned int	*page_sizes;
266269 	unsigned int		page_size_shift;
267270 	unsigned int		max_oob;
271
+	u32			ecc_level_shift;
268272 	u32			features;
269273 
270274 	/* for low-power standby/resume only */
....@@ -589,15 +593,53 @@
589593 	INTFC_CTLR_READY		= BIT(31),
590594 };
591595 
596
+/***********************************************************************
597
+ * NAND ACC CONTROL bitfield
598
+ *
599
+ * Some bits have remained constant throughout hardware revision, while
600
+ * others have shifted around.
601
+ ***********************************************************************/
602
+
603
+/* Constant for all versions (where supported) */
604
+enum {
605
+	/* See BRCMNAND_HAS_CACHE_MODE */
606
+	ACC_CONTROL_CACHE_MODE				= BIT(22),
607
+
608
+	/* See BRCMNAND_HAS_PREFETCH */
609
+	ACC_CONTROL_PREFETCH				= BIT(23),
610
+
611
+	ACC_CONTROL_PAGE_HIT				= BIT(24),
612
+	ACC_CONTROL_WR_PREEMPT				= BIT(25),
613
+	ACC_CONTROL_PARTIAL_PAGE			= BIT(26),
614
+	ACC_CONTROL_RD_ERASED				= BIT(27),
615
+	ACC_CONTROL_FAST_PGM_RDIN			= BIT(28),
616
+	ACC_CONTROL_WR_ECC				= BIT(30),
617
+	ACC_CONTROL_RD_ECC				= BIT(31),
618
+};
619
+
620
+#define	ACC_CONTROL_ECC_SHIFT			16
621
+/* Only for v7.2 */
622
+#define	ACC_CONTROL_ECC_EXT_SHIFT		13
623
+
624
+static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
625
+{
626
+	return static_branch_unlikely(&brcmnand_soc_has_ops_key);
627
+}
628
+
592629 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
593630 {
631
+	if (brcmnand_non_mmio_ops(ctrl))
632
+		return brcmnand_soc_read(ctrl->soc, offs);
594633 	return brcmnand_readl(ctrl->nand_base + offs);
595634 }
596635 
597636 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
598637 				 u32 val)
599638 {
600
-	brcmnand_writel(val, ctrl->nand_base + offs);
639
+	if (brcmnand_non_mmio_ops(ctrl))
640
+		brcmnand_soc_write(ctrl->soc, val, offs);
641
+	else
642
+		brcmnand_writel(val, ctrl->nand_base + offs);
601643 }
602644 
603645 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
....@@ -716,6 +758,12 @@
716758 	else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
717759 		ctrl->features |= BRCMNAND_HAS_WP;
718760 
761
+	/* v7.2 has different ecc level shift in the acc register */
762
+	if (ctrl->nand_version == 0x0702)
763
+		ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;
764
+	else
765
+		ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;
766
+
719767 	return 0;
720768 }
721769 
....@@ -763,13 +811,18 @@
763811 
764812 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
765813 {
814
+	if (brcmnand_non_mmio_ops(ctrl))
815
+		return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);
766816 	return __raw_readl(ctrl->nand_fc + word * 4);
767817 }
768818 
769819 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
770820 				     int word, u32 val)
771821 {
772
-	__raw_writel(val, ctrl->nand_fc + word * 4);
822
+	if (brcmnand_non_mmio_ops(ctrl))
823
+		brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);
824
+	else
825
+		__raw_writel(val, ctrl->nand_fc + word * 4);
773826 }
774827 
775828 static inline void edu_writel(struct brcmnand_controller *ctrl,
....@@ -899,30 +952,6 @@
899952 	return 0;
900953 }
901954 
902
-/***********************************************************************
903
- * NAND ACC CONTROL bitfield
904
- *
905
- * Some bits have remained constant throughout hardware revision, while
906
- * others have shifted around.
907
- ***********************************************************************/
908
-
909
-/* Constant for all versions (where supported) */
910
-enum {
911
-	/* See BRCMNAND_HAS_CACHE_MODE */
912
-	ACC_CONTROL_CACHE_MODE				= BIT(22),
913
-
914
-	/* See BRCMNAND_HAS_PREFETCH */
915
-	ACC_CONTROL_PREFETCH				= BIT(23),
916
-
917
-	ACC_CONTROL_PAGE_HIT				= BIT(24),
918
-	ACC_CONTROL_WR_PREEMPT				= BIT(25),
919
-	ACC_CONTROL_PARTIAL_PAGE			= BIT(26),
920
-	ACC_CONTROL_RD_ERASED				= BIT(27),
921
-	ACC_CONTROL_FAST_PGM_RDIN			= BIT(28),
922
-	ACC_CONTROL_WR_ECC				= BIT(30),
923
-	ACC_CONTROL_RD_ECC				= BIT(31),
924
-};
925
-
926955 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
927956 {
928957 	if (ctrl->nand_version == 0x0702)
....@@ -935,18 +964,15 @@
935964 		return GENMASK(4, 0);
936965 }
937966 
938
-#define NAND_ACC_CONTROL_ECC_SHIFT	16
939
-#define NAND_ACC_CONTROL_ECC_EXT_SHIFT	13
940
-
941967 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
942968 {
943969 	u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
944970 
945
-	mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
971
+	mask <<= ACC_CONTROL_ECC_SHIFT;
946972 
947973 	/* v7.2 includes additional ECC levels */
948
-	if (ctrl->nand_version >= 0x0702)
949
-		mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
974
+	if (ctrl->nand_version == 0x0702)
975
+		mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT;
950976 
951977 	return mask;
952978 }
....@@ -960,8 +986,8 @@
960986 
961987 	if (en) {
962988 		acc_control |= ecc_flags; /* enable RD/WR ECC */
963
-		acc_control |= host->hwcfg.ecc_level
964
-			       << NAND_ACC_CONTROL_ECC_SHIFT;
989
+		acc_control &= ~brcmnand_ecc_level_mask(ctrl);
990
+		acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift;
965991 	} else {
966992 		acc_control &= ~ecc_flags; /* disable RD/WR ECC */
967993 		acc_control &= ~brcmnand_ecc_level_mask(ctrl);
....@@ -1039,6 +1065,14 @@
10391065 
10401066 		cpu_relax();
10411067 	} while (time_after(limit, jiffies));
1068
+
1069
+	/*
1070
+	 * do a final check after time out in case the CPU was busy and the driver
1071
+	 * did not get enough time to perform the polling to avoid false alarms
1072
+	 */
1073
+	val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1074
+	if ((val & mask) == expected_val)
1075
+		return 0;
10421076 
10431077 	dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
10441078 		 expected_val, val & mask);
....@@ -1429,19 +1463,33 @@
14291463 			     const u8 *oob, int sas, int sector_1k)
14301464 {
14311465 	int tbytes = sas << sector_1k;
1432
-	int j;
1466
+	int j, k = 0;
1467
+	u32 last = 0xffffffff;
1468
+	u8 *plast = (u8 *)&last;
14331469 
14341470 	/* Adjust OOB values for 1K sector size */
14351471 	if (sector_1k && (i & 0x01))
14361472 		tbytes = max(0, tbytes - (int)ctrl->max_oob);
14371473 	tbytes = min_t(int, tbytes, ctrl->max_oob);
14381474 
1439
-	for (j = 0; j < tbytes; j += 4)
1475
+	/*
1476
+	 * tbytes may not be multiple of words. Make sure we don't read out of
1477
+	 * the boundary and stop at last word.
1478
+	 */
1479
+	for (j = 0; (j + 3) < tbytes; j += 4)
14401480 		oob_reg_write(ctrl, j,
14411481 				(oob[j + 0] << 24) |
14421482 				(oob[j + 1] << 16) |
14431483 				(oob[j + 2] <<  8) |
14441484 				(oob[j + 3] <<  0));
1485
+
1486
+	/* handle the remaing bytes */
1487
+	while (j < tbytes)
1488
+		plast[k++] = oob[j++];
1489
+
1490
+	if (tbytes & 0x3)
1491
+		oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last));
1492
+
14451493 	return tbytes;
14461494 }
14471495 
....@@ -1543,7 +1591,17 @@
15431591 
15441592 	dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);
15451593 
1546
-	BUG_ON(ctrl->cmd_pending != 0);
1594
+	/*
1595
+	 * If we came here through _panic_write and there is a pending
1596
+	 * command, try to wait for it. If it times out, rather than
1597
+	 * hitting BUG_ON, just return so we don't crash while crashing.
1598
+	 */
1599
+	if (oops_in_progress) {
1600
+		if (ctrl->cmd_pending &&
1601
+			bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))
1602
+			return;
1603
+	} else
1604
+		BUG_ON(ctrl->cmd_pending != 0);
15471605 	ctrl->cmd_pending = cmd;
15481606 
15491607 	ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
....@@ -2483,7 +2541,7 @@
24832541 	tmp &= ~brcmnand_ecc_level_mask(ctrl);
24842542 	tmp &= ~brcmnand_spare_area_mask(ctrl);
24852543 	if (ctrl->nand_version >= 0x0302) {
2486
-		tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2544
+		tmp |= cfg->ecc_level << ctrl->ecc_level_shift;
24872545 		tmp |= cfg->spare_area_size;
24882546 	}
24892547 	nand_writereg(ctrl, acc_control_offs, tmp);
....@@ -2534,6 +2592,8 @@
25342592 	struct nand_chip *chip = &host->chip;
25352593 	const struct nand_ecc_props *requirements =
25362594 		nanddev_get_ecc_requirements(&chip->base);
2595
+	struct nand_memory_organization *memorg =
2596
+		nanddev_get_memorg(&chip->base);
25372597 	struct brcmnand_controller *ctrl = host->ctrl;
25382598 	struct brcmnand_cfg *cfg = &host->hwcfg;
25392599 	char msg[128];
....@@ -2555,10 +2615,11 @@
25552615 	if (cfg->spare_area_size > ctrl->max_oob)
25562616 		cfg->spare_area_size = ctrl->max_oob;
25572617 	/*
2558
-	 * Set oobsize to be consistent with controller's spare_area_size, as
2559
-	 * the rest is inaccessible.
2618
+	 * Set mtd and memorg oobsize to be consistent with controller's
2619
+	 * spare_area_size, as the rest is inaccessible.
25602620 	 */
25612621 	mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2622
+	memorg->oobsize = mtd->oobsize;
25622623 
25632624 	cfg->device_size = mtd->size;
25642625 	cfg->block_size = mtd->erasesize;
....@@ -2950,6 +3011,12 @@
29503011 	dev_set_drvdata(dev, ctrl);
29513012 	ctrl->dev = dev;
29523013 
3014
+	/* Enable the static key if the soc provides I/O operations indicating
3015
+	 * that a non-memory mapped IO access path must be used
3016
+	 */
3017
+	if (brcmnand_soc_has_ops(ctrl->soc))
3018
+		static_branch_enable(&brcmnand_soc_has_ops_key);
3019
+
29533020 	init_completion(&ctrl->done);
29543021 	init_completion(&ctrl->dma_done);
29553022 	init_completion(&ctrl->edu_done);