| .. | .. |
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| 82 | 82 | }; |
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| 83 | 83 | |
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| 84 | 84 | struct bcm6345_l1_cpu { |
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| 85 | + struct bcm6345_l1_chip *intc; |
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| 85 | 86 | void __iomem *map_base; |
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| 86 | 87 | unsigned int parent_irq; |
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| 87 | 88 | u32 enable_cache[]; |
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| .. | .. |
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| 115 | 116 | |
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| 116 | 117 | static void bcm6345_l1_irq_handle(struct irq_desc *desc) |
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| 117 | 118 | { |
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| 118 | | - struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); |
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| 119 | | - struct bcm6345_l1_cpu *cpu; |
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| 119 | + struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc); |
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| 120 | + struct bcm6345_l1_chip *intc = cpu->intc; |
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| 120 | 121 | struct irq_chip *chip = irq_desc_get_chip(desc); |
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| 121 | 122 | unsigned int idx; |
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| 122 | | - |
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| 123 | | -#ifdef CONFIG_SMP |
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| 124 | | - cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; |
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| 125 | | -#else |
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| 126 | | - cpu = intc->cpus[0]; |
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| 127 | | -#endif |
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| 128 | 123 | |
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| 129 | 124 | chained_irq_enter(chip, desc); |
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| 130 | 125 | |
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| .. | .. |
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| 257 | 252 | if (!cpu) |
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| 258 | 253 | return -ENOMEM; |
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| 259 | 254 | |
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| 255 | + cpu->intc = intc; |
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| 260 | 256 | cpu->map_base = ioremap(res.start, sz); |
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| 261 | 257 | if (!cpu->map_base) |
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| 262 | 258 | return -ENOMEM; |
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| .. | .. |
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| 272 | 268 | return -EINVAL; |
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| 273 | 269 | } |
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| 274 | 270 | irq_set_chained_handler_and_data(cpu->parent_irq, |
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| 275 | | - bcm6345_l1_irq_handle, intc); |
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| 271 | + bcm6345_l1_irq_handle, cpu); |
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| 276 | 272 | |
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| 277 | 273 | return 0; |
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| 278 | 274 | } |
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