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2024-10-16 50a212ec906f7524620675f0c57357691c26c81f 
 kernel/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
....@@ -55,41 +55,50 @@
5555 	do {								\
5656 		memset(&(req), 0, sizeof((req)));			\
5757 		(req).opcode = CMDQ_BASE_OPCODE_##CMD;			\
58
-		(req).cmd_size = (sizeof((req)) +			\
59
-				BNXT_QPLIB_CMDQE_UNITS - 1) /		\
60
-				BNXT_QPLIB_CMDQE_UNITS;			\
58
+		(req).cmd_size = sizeof((req));				\
6159 		(req).flags = cpu_to_le16(cmd_flags);			\
6260 	} while (0)
6361 
6462 #define RCFW_CMD_WAIT_TIME_MS		20000 /* 20 Seconds timeout */
65
-
66
-/* CMDQ elements */
67
-#define BNXT_QPLIB_CMDQE_MAX_CNT	256
68
-#define BNXT_QPLIB_CMDQE_UNITS		sizeof(struct bnxt_qplib_cmdqe)
69
-#define BNXT_QPLIB_CMDQE_CNT_PER_PG	(PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
70
-
71
-#define MAX_CMDQ_IDX			(BNXT_QPLIB_CMDQE_MAX_CNT - 1)
72
-#define MAX_CMDQ_IDX_PER_PG		(BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
73
-
74
-#define RCFW_MAX_OUTSTANDING_CMD	BNXT_QPLIB_CMDQE_MAX_CNT
75
-#define RCFW_MAX_COOKIE_VALUE		0x7FFF
76
-#define RCFW_CMD_IS_BLOCKING		0x8000
77
-#define RCFW_BLOCKED_CMD_WAIT_COUNT	0x4E20
7863 
7964 /* Cmdq contains a fix number of a 16-Byte slots */
8065 struct bnxt_qplib_cmdqe {
8166 	u8		data[16];
8267 };
8368 
84
-static inline u32 get_cmdq_pg(u32 val)
69
+/* CMDQ elements */
70
+#define BNXT_QPLIB_CMDQE_MAX_CNT_256	256
71
+#define BNXT_QPLIB_CMDQE_MAX_CNT_8192	8192
72
+#define BNXT_QPLIB_CMDQE_UNITS		sizeof(struct bnxt_qplib_cmdqe)
73
+#define BNXT_QPLIB_CMDQE_BYTES(depth)	((depth) * BNXT_QPLIB_CMDQE_UNITS)
74
+
75
+static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
8576 {
86
-	return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
77
+	u32 npages;
78
+
79
+	npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
80
+	if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
81
+		npages++;
82
+	return npages;
8783 }
8884 
89
-static inline u32 get_cmdq_idx(u32 val)
85
+static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
9086 {
91
-	return val & MAX_CMDQ_IDX_PER_PG;
87
+	return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
9288 }
89
+
90
+/* Set the cmd_size to a factor of CMDQE unit */
91
+static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
92
+{
93
+	req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
94
+			 BNXT_QPLIB_CMDQE_UNITS;
95
+}
96
+
97
+#define RCFW_MAX_COOKIE_VALUE		0x7FFF
98
+#define RCFW_CMD_IS_BLOCKING		0x8000
99
+#define RCFW_BLOCKED_CMD_WAIT_COUNT	0x4E20
100
+
101
+#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
93102 
94103 /* Crsq buf is 1024-Byte */
95104 struct bnxt_qplib_crsbe {
....@@ -100,45 +109,15 @@
100109 /* Allocate 1 per QP for async error notification for now */
101110 #define BNXT_QPLIB_CREQE_MAX_CNT	(64 * 1024)
102111 #define BNXT_QPLIB_CREQE_UNITS		16	/* 16-Bytes per prod unit */
103
-#define BNXT_QPLIB_CREQE_CNT_PER_PG	(PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
104
-
105
-#define MAX_CREQ_IDX			(BNXT_QPLIB_CREQE_MAX_CNT - 1)
106
-#define MAX_CREQ_IDX_PER_PG		(BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
107
-
108
-static inline u32 get_creq_pg(u32 val)
109
-{
110
-	return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
111
-}
112
-
113
-static inline u32 get_creq_idx(u32 val)
114
-{
115
-	return val & MAX_CREQ_IDX_PER_PG;
116
-}
117
-
118
-#define BNXT_QPLIB_CREQE_PER_PG	(PAGE_SIZE / sizeof(struct creq_base))
119
-
120112 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)			\
121113 	(!!((hdr)->v & CREQ_BASE_V) ==				\
122114 	   !((raw_cons) & (cp_bit)))
123
-
124
-#define CREQ_DB_KEY_CP			(0x2 << CMPL_DOORBELL_KEY_SFT)
125
-#define CREQ_DB_IDX_VALID		CMPL_DOORBELL_IDX_VALID
126
-#define CREQ_DB_IRQ_DIS			CMPL_DOORBELL_MASK
127
-#define CREQ_DB_CP_FLAGS_REARM		(CREQ_DB_KEY_CP |	\
128
-					 CREQ_DB_IDX_VALID)
129
-#define CREQ_DB_CP_FLAGS		(CREQ_DB_KEY_CP |	\
130
-					 CREQ_DB_IDX_VALID |	\
131
-					 CREQ_DB_IRQ_DIS)
132
-#define CREQ_DB_REARM(db, raw_cons, cp_bit)			\
133
-	writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
134
-#define CREQ_DB(db, raw_cons, cp_bit)				\
135
-	writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
136
-
137115 #define CREQ_ENTRY_POLL_BUDGET		0x100
138116 
139117 /* HWQ */
118
+typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *);
140119 
141
-struct bnxt_qplib_crsq {
120
+struct bnxt_qplib_crsqe {
142121 	struct creq_qp_event	*resp;
143122 	u32			req_size;
144123 };
....@@ -154,57 +133,75 @@
154133 	void *qp_handle;        /* ptr to qplib_qp */
155134 };
156135 
136
+#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
137
+
138
+#define FIRMWARE_INITIALIZED_FLAG	(0)
139
+#define FIRMWARE_FIRST_FLAG		(31)
140
+#define FIRMWARE_TIMED_OUT		(3)
141
+struct bnxt_qplib_cmdq_mbox {
142
+	struct bnxt_qplib_reg_desc	reg;
143
+	void __iomem			*prod;
144
+	void __iomem			*db;
145
+};
146
+
147
+struct bnxt_qplib_cmdq_ctx {
148
+	struct bnxt_qplib_hwq		hwq;
149
+	struct bnxt_qplib_cmdq_mbox	cmdq_mbox;
150
+	wait_queue_head_t		waitq;
151
+	unsigned long			flags;
152
+	unsigned long			*cmdq_bitmap;
153
+	u32				seq_num;
154
+};
155
+
156
+struct bnxt_qplib_creq_db {
157
+	struct bnxt_qplib_reg_desc	reg;
158
+	struct bnxt_qplib_db_info	dbinfo;
159
+};
160
+
161
+struct bnxt_qplib_creq_stat {
162
+	u64	creq_qp_event_processed;
163
+	u64	creq_func_event_processed;
164
+};
165
+
166
+struct bnxt_qplib_creq_ctx {
167
+	struct bnxt_qplib_hwq		hwq;
168
+	struct bnxt_qplib_creq_db	creq_db;
169
+	struct bnxt_qplib_creq_stat	stats;
170
+	struct tasklet_struct		creq_tasklet;
171
+	aeq_handler_t			aeq_handler;
172
+	u16				ring_id;
173
+	int				msix_vec;
174
+	bool				requested; /*irq handler installed */
175
+	char				*irq_name;
176
+};
177
+
157178 /* RCFW Communication Channels */
158179 struct bnxt_qplib_rcfw {
159180 	struct pci_dev		*pdev;
160
-	int			vector;
161
-	struct tasklet_struct	worker;
162
-	bool			requested;
163
-	unsigned long		*cmdq_bitmap;
164
-	u32			bmap_size;
165
-	unsigned long		flags;
166
-#define FIRMWARE_INITIALIZED_FLAG	0
167
-#define FIRMWARE_FIRST_FLAG		31
168
-#define FIRMWARE_TIMED_OUT		3
169
-	wait_queue_head_t	waitq;
170
-	int			(*aeq_handler)(struct bnxt_qplib_rcfw *,
171
-					       void *, void *);
172
-	u32			seq_num;
173
-
174
-	/* Bar region info */
175
-	void __iomem		*cmdq_bar_reg_iomem;
176
-	u16			cmdq_bar_reg;
177
-	u16			cmdq_bar_reg_prod_off;
178
-	u16			cmdq_bar_reg_trig_off;
179
-	u16			creq_ring_id;
180
-	u16			creq_bar_reg;
181
-	void __iomem		*creq_bar_reg_iomem;
182
-
183
-	/* Cmd-Resp and Async Event notification queue */
184
-	struct bnxt_qplib_hwq	creq;
185
-	u64			creq_qp_event_processed;
186
-	u64			creq_func_event_processed;
187
-
188
-	/* Actual Cmd and Resp Queues */
189
-	struct bnxt_qplib_hwq	cmdq;
190
-	struct bnxt_qplib_crsq	*crsqe_tbl;
181
+	struct bnxt_qplib_res	*res;
182
+	struct bnxt_qplib_cmdq_ctx	cmdq;
183
+	struct bnxt_qplib_creq_ctx	creq;
184
+	struct bnxt_qplib_crsqe		*crsqe_tbl;
191185 	int qp_tbl_size;
192186 	struct bnxt_qplib_qp_node *qp_tbl;
187
+	u64 oos_prev;
188
+	u32 init_oos_stats;
189
+	u32 cmdq_depth;
193190 };
194191 
195192 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
196
-int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
197
-				  struct bnxt_qplib_rcfw *rcfw, int qp_tbl_sz);
193
+int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
194
+				  struct bnxt_qplib_rcfw *rcfw,
195
+				  struct bnxt_qplib_ctx *ctx,
196
+				  int qp_tbl_sz);
198197 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
199198 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
200199 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
201200 			      bool need_init);
202
-int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
203
-				   struct bnxt_qplib_rcfw *rcfw,
201
+int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
204202 				   int msix_vector,
205203 				   int cp_bar_reg_off, int virt_fn,
206
-				   int (*aeq_handler)(struct bnxt_qplib_rcfw *,
207
-						      void *aeqe, void *obj));
204
+				   aeq_handler_t aeq_handler);
208205 
209206 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
210207 				struct bnxt_qplib_rcfw *rcfw,
....@@ -219,4 +216,9 @@
219216 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
220217 			 struct bnxt_qplib_ctx *ctx, int is_virtfn);
221218 void bnxt_qplib_mark_qp_error(void *qp_handle);
219
+static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw)
220
+{
221
+	/* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/
222
+	return (qid == 1) ? rcfw->qp_tbl_size - 1 : qid % rcfw->qp_tbl_size - 2;
223
+}
222224 #endif /* __BNXT_QPLIB_RCFW_H__ */