.. | .. |
---|
45 | 45 | #define cpu_has_ic_fills_f_dc 0 |
---|
46 | 46 | #define cpu_has_64bits 1 |
---|
47 | 47 | #define cpu_has_octeon_cache 1 |
---|
48 | | -#define cpu_has_saa octeon_has_saa() |
---|
49 | 48 | #define cpu_has_mips32r1 1 |
---|
50 | 49 | #define cpu_has_mips32r2 1 |
---|
51 | 50 | #define cpu_has_mips64r1 1 |
---|
.. | .. |
---|
60 | 59 | |
---|
61 | 60 | #define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) |
---|
62 | 61 | |
---|
63 | | -#define ARCH_HAS_IRQ_PER_CPU 1 |
---|
64 | 62 | #define ARCH_HAS_SPINLOCK_PREFETCH 1 |
---|
65 | 63 | #define spin_lock_prefetch(x) prefetch(x) |
---|
66 | 64 | #define PREFETCH_STRIDE 128 |
---|
.. | .. |
---|
72 | 70 | */ |
---|
73 | 71 | #define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1 |
---|
74 | 72 | #endif |
---|
75 | | - |
---|
76 | | -static inline int octeon_has_saa(void) |
---|
77 | | -{ |
---|
78 | | - int id; |
---|
79 | | - asm volatile ("mfc0 %0, $15,0" : "=r" (id)); |
---|
80 | | - return id >= 0x000d0300; |
---|
81 | | -} |
---|
82 | 73 | |
---|
83 | 74 | /* |
---|
84 | 75 | * The last 256MB are reserved for device to device mappings and the |
---|