forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-16 50a212ec906f7524620675f0c57357691c26c81f 
 kernel/arch/arm/mach-davinci/da850.c
....@@ -1,7 +1,7 @@
11 /*
22  * TI DA850/OMAP-L138 chip specific setup
33  *
4
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
4
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
55  *
66  * Derived from: arch/arm/mach-davinci/da830.c
77  * Original Copyrights follow:
....@@ -18,9 +18,12 @@
1818 #include <linux/cpufreq.h>
1919 #include <linux/gpio.h>
2020 #include <linux/init.h>
21
+#include <linux/io.h>
22
+#include <linux/irqchip/irq-davinci-cp-intc.h>
2123 #include <linux/mfd/da8xx-cfgchip.h>
2224 #include <linux/platform_data/clk-da8xx-cfgchip.h>
2325 #include <linux/platform_data/clk-davinci-pll.h>
26
+#include <linux/platform_data/davinci-cpufreq.h>
2427 #include <linux/platform_data/gpio-davinci.h>
2528 #include <linux/platform_device.h>
2629 #include <linux/regmap.h>
....@@ -29,13 +32,13 @@
2932 #include <asm/mach/map.h>
3033 
3134 #include <mach/common.h>
32
-#include <mach/cpufreq.h>
3335 #include <mach/cputype.h>
3436 #include <mach/da8xx.h>
35
-#include <mach/irqs.h>
3637 #include <mach/pm.h>
37
-#include <mach/time.h>
3838 
39
+#include <clocksource/timer-davinci.h>
40
+
41
+#include "irqs.h"
3942 #include "mux.h"
4043 
4144 #define DA850_PLL1_BASE		0x01e1a000
....@@ -298,111 +301,6 @@
298301 	-1
299302 };
300303 
301
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
302
-static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
303
-	[IRQ_DA8XX_COMMTX]		= 7,
304
-	[IRQ_DA8XX_COMMRX]		= 7,
305
-	[IRQ_DA8XX_NINT]		= 7,
306
-	[IRQ_DA8XX_EVTOUT0]		= 7,
307
-	[IRQ_DA8XX_EVTOUT1]		= 7,
308
-	[IRQ_DA8XX_EVTOUT2]		= 7,
309
-	[IRQ_DA8XX_EVTOUT3]		= 7,
310
-	[IRQ_DA8XX_EVTOUT4]		= 7,
311
-	[IRQ_DA8XX_EVTOUT5]		= 7,
312
-	[IRQ_DA8XX_EVTOUT6]		= 7,
313
-	[IRQ_DA8XX_EVTOUT7]		= 7,
314
-	[IRQ_DA8XX_CCINT0]		= 7,
315
-	[IRQ_DA8XX_CCERRINT]		= 7,
316
-	[IRQ_DA8XX_TCERRINT0]		= 7,
317
-	[IRQ_DA8XX_AEMIFINT]		= 7,
318
-	[IRQ_DA8XX_I2CINT0]		= 7,
319
-	[IRQ_DA8XX_MMCSDINT0]		= 7,
320
-	[IRQ_DA8XX_MMCSDINT1]		= 7,
321
-	[IRQ_DA8XX_ALLINT0]		= 7,
322
-	[IRQ_DA8XX_RTC]			= 7,
323
-	[IRQ_DA8XX_SPINT0]		= 7,
324
-	[IRQ_DA8XX_TINT12_0]		= 7,
325
-	[IRQ_DA8XX_TINT34_0]		= 7,
326
-	[IRQ_DA8XX_TINT12_1]		= 7,
327
-	[IRQ_DA8XX_TINT34_1]		= 7,
328
-	[IRQ_DA8XX_UARTINT0]		= 7,
329
-	[IRQ_DA8XX_KEYMGRINT]		= 7,
330
-	[IRQ_DA850_MPUADDRERR0]		= 7,
331
-	[IRQ_DA8XX_CHIPINT0]		= 7,
332
-	[IRQ_DA8XX_CHIPINT1]		= 7,
333
-	[IRQ_DA8XX_CHIPINT2]		= 7,
334
-	[IRQ_DA8XX_CHIPINT3]		= 7,
335
-	[IRQ_DA8XX_TCERRINT1]		= 7,
336
-	[IRQ_DA8XX_C0_RX_THRESH_PULSE]	= 7,
337
-	[IRQ_DA8XX_C0_RX_PULSE]		= 7,
338
-	[IRQ_DA8XX_C0_TX_PULSE]		= 7,
339
-	[IRQ_DA8XX_C0_MISC_PULSE]	= 7,
340
-	[IRQ_DA8XX_C1_RX_THRESH_PULSE]	= 7,
341
-	[IRQ_DA8XX_C1_RX_PULSE]		= 7,
342
-	[IRQ_DA8XX_C1_TX_PULSE]		= 7,
343
-	[IRQ_DA8XX_C1_MISC_PULSE]	= 7,
344
-	[IRQ_DA8XX_MEMERR]		= 7,
345
-	[IRQ_DA8XX_GPIO0]		= 7,
346
-	[IRQ_DA8XX_GPIO1]		= 7,
347
-	[IRQ_DA8XX_GPIO2]		= 7,
348
-	[IRQ_DA8XX_GPIO3]		= 7,
349
-	[IRQ_DA8XX_GPIO4]		= 7,
350
-	[IRQ_DA8XX_GPIO5]		= 7,
351
-	[IRQ_DA8XX_GPIO6]		= 7,
352
-	[IRQ_DA8XX_GPIO7]		= 7,
353
-	[IRQ_DA8XX_GPIO8]		= 7,
354
-	[IRQ_DA8XX_I2CINT1]		= 7,
355
-	[IRQ_DA8XX_LCDINT]		= 7,
356
-	[IRQ_DA8XX_UARTINT1]		= 7,
357
-	[IRQ_DA8XX_MCASPINT]		= 7,
358
-	[IRQ_DA8XX_ALLINT1]		= 7,
359
-	[IRQ_DA8XX_SPINT1]		= 7,
360
-	[IRQ_DA8XX_UHPI_INT1]		= 7,
361
-	[IRQ_DA8XX_USB_INT]		= 7,
362
-	[IRQ_DA8XX_IRQN]		= 7,
363
-	[IRQ_DA8XX_RWAKEUP]		= 7,
364
-	[IRQ_DA8XX_UARTINT2]		= 7,
365
-	[IRQ_DA8XX_DFTSSINT]		= 7,
366
-	[IRQ_DA8XX_EHRPWM0]		= 7,
367
-	[IRQ_DA8XX_EHRPWM0TZ]		= 7,
368
-	[IRQ_DA8XX_EHRPWM1]		= 7,
369
-	[IRQ_DA8XX_EHRPWM1TZ]		= 7,
370
-	[IRQ_DA850_SATAINT]		= 7,
371
-	[IRQ_DA850_TINTALL_2]		= 7,
372
-	[IRQ_DA8XX_ECAP0]		= 7,
373
-	[IRQ_DA8XX_ECAP1]		= 7,
374
-	[IRQ_DA8XX_ECAP2]		= 7,
375
-	[IRQ_DA850_MMCSDINT0_1]		= 7,
376
-	[IRQ_DA850_MMCSDINT1_1]		= 7,
377
-	[IRQ_DA850_T12CMPINT0_2]	= 7,
378
-	[IRQ_DA850_T12CMPINT1_2]	= 7,
379
-	[IRQ_DA850_T12CMPINT2_2]	= 7,
380
-	[IRQ_DA850_T12CMPINT3_2]	= 7,
381
-	[IRQ_DA850_T12CMPINT4_2]	= 7,
382
-	[IRQ_DA850_T12CMPINT5_2]	= 7,
383
-	[IRQ_DA850_T12CMPINT6_2]	= 7,
384
-	[IRQ_DA850_T12CMPINT7_2]	= 7,
385
-	[IRQ_DA850_T12CMPINT0_3]	= 7,
386
-	[IRQ_DA850_T12CMPINT1_3]	= 7,
387
-	[IRQ_DA850_T12CMPINT2_3]	= 7,
388
-	[IRQ_DA850_T12CMPINT3_3]	= 7,
389
-	[IRQ_DA850_T12CMPINT4_3]	= 7,
390
-	[IRQ_DA850_T12CMPINT5_3]	= 7,
391
-	[IRQ_DA850_T12CMPINT6_3]	= 7,
392
-	[IRQ_DA850_T12CMPINT7_3]	= 7,
393
-	[IRQ_DA850_RPIINT]		= 7,
394
-	[IRQ_DA850_VPIFINT]		= 7,
395
-	[IRQ_DA850_CCINT1]		= 7,
396
-	[IRQ_DA850_CCERRINT1]		= 7,
397
-	[IRQ_DA850_TCERRINT2]		= 7,
398
-	[IRQ_DA850_TINTALL_3]		= 7,
399
-	[IRQ_DA850_MCBSP0RINT]		= 7,
400
-	[IRQ_DA850_MCBSP0XINT]		= 7,
401
-	[IRQ_DA850_MCBSP1RINT]		= 7,
402
-	[IRQ_DA850_MCBSP1XINT]		= 7,
403
-	[IRQ_DA8XX_ARMCLKSTOPREQ]	= 7,
404
-};
405
-
406304 static struct map_desc da850_io_desc[] = {
407305 	{
408306 		.virtual	= IO_VIRT,
....@@ -436,38 +334,16 @@
436334 	},
437335 };
438336 
439
-static struct davinci_timer_instance da850_timer_instance[4] = {
440
-	{
441
-		.base		= DA8XX_TIMER64P0_BASE,
442
-		.bottom_irq	= IRQ_DA8XX_TINT12_0,
443
-		.top_irq	= IRQ_DA8XX_TINT34_0,
444
-	},
445
-	{
446
-		.base		= DA8XX_TIMER64P1_BASE,
447
-		.bottom_irq	= IRQ_DA8XX_TINT12_1,
448
-		.top_irq	= IRQ_DA8XX_TINT34_1,
449
-	},
450
-	{
451
-		.base		= DA850_TIMER64P2_BASE,
452
-		.bottom_irq	= IRQ_DA850_TINT12_2,
453
-		.top_irq	= IRQ_DA850_TINT34_2,
454
-	},
455
-	{
456
-		.base		= DA850_TIMER64P3_BASE,
457
-		.bottom_irq	= IRQ_DA850_TINT12_3,
458
-		.top_irq	= IRQ_DA850_TINT34_3,
459
-	},
460
-};
461
-
462337 /*
463
- * T0_BOT: Timer 0, bottom		: Used for clock_event
464
- * T0_TOP: Timer 0, top			: Used for clocksource
465
- * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
338
+ * Bottom half of timer 0 is used for clock_event, top half for
339
+ * clocksource.
466340  */
467
-static struct davinci_timer_info da850_timer_info = {
468
-	.timers		= da850_timer_instance,
469
-	.clockevent_id	= T0_BOT,
470
-	.clocksource_id	= T0_TOP,
341
+static const struct davinci_timer_cfg da850_timer_cfg = {
342
+	.reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
343
+	.irq = {
344
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
345
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
346
+	},
471347 };
472348 
473349 #ifdef CONFIG_CPU_FREQ
....@@ -658,8 +534,8 @@
658534 
659535 static struct resource da850_vpif_display_resource[] = {
660536 	{
661
-		.start = IRQ_DA850_VPIFINT,
662
-		.end   = IRQ_DA850_VPIFINT,
537
+		.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
538
+		.end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
663539 		.flags = IORESOURCE_IRQ,
664540 	},
665541 };
....@@ -677,13 +553,13 @@
677553 
678554 static struct resource da850_vpif_capture_resource[] = {
679555 	{
680
-		.start = IRQ_DA850_VPIFINT,
681
-		.end   = IRQ_DA850_VPIFINT,
556
+		.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
557
+		.end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
682558 		.flags = IORESOURCE_IRQ,
683559 	},
684560 	{
685
-		.start = IRQ_DA850_VPIFINT,
686
-		.end   = IRQ_DA850_VPIFINT,
561
+		.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
562
+		.end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
687563 		.flags = IORESOURCE_IRQ,
688564 	},
689565 };
....@@ -719,7 +595,9 @@
719595 }
720596 
721597 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
722
-	.ngpio = 144,
598
+	.no_auto_base	= true,
599
+	.base		= 0,
600
+	.ngpio		= 144,
723601 };
724602 
725603 int __init da850_register_gpio(void)
....@@ -736,11 +614,6 @@
736614 	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
737615 	.pinmux_pins		= da850_pins,
738616 	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
739
-	.intc_base		= DA8XX_CP_INTC_BASE,
740
-	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
741
-	.intc_irq_prios		= da850_default_priorities,
742
-	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
743
-	.timer_info		= &da850_timer_info,
744617 	.emac_pdata		= &da8xx_emac_pdata,
745618 	.sram_dma		= DA8XX_SHARED_RAM_BASE,
746619 	.sram_len		= SZ_128K,
....@@ -758,11 +631,26 @@
758631 	WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
759632 }
760633 
634
+static const struct davinci_cp_intc_config da850_cp_intc_config = {
635
+	.reg = {
636
+		.start		= DA8XX_CP_INTC_BASE,
637
+		.end		= DA8XX_CP_INTC_BASE + SZ_8K - 1,
638
+		.flags		= IORESOURCE_MEM,
639
+	},
640
+	.num_irqs		= DA850_N_CP_INTC_IRQ,
641
+};
642
+
643
+void __init da850_init_irq(void)
644
+{
645
+	davinci_cp_intc_init(&da850_cp_intc_config);
646
+}
647
+
761648 void __init da850_init_time(void)
762649 {
763650 	void __iomem *pll0;
764651 	struct regmap *cfgchip;
765652 	struct clk *clk;
653
+	int rv;
766654 
767655 	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
768656 
....@@ -772,8 +660,13 @@
772660 	da850_pll0_init(NULL, pll0, cfgchip);
773661 
774662 	clk = clk_get(NULL, "timer0");
663
+	if (WARN_ON(IS_ERR(clk))) {
664
+		pr_err("Unable to get the timer clock\n");
665
+		return;
666
+	}
775667 
776
-	davinci_timer_init(clk);
668
+	rv = davinci_timer_register(clk, &da850_timer_cfg);
669
+	WARN(rv, "Unable to register the timer: %d\n", rv);
777670 }
778671 
779672 static struct resource da850_pll1_resources[] = {