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2024-10-16 50a212ec906f7524620675f0c57357691c26c81f 
 kernel/arch/arm/boot/dts/qcom-ipq4019.dtsi
....@@ -1,24 +1,18 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 /dts-v1/;
157 
16
-#include "skeleton.dtsi"
178 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
189 #include <dt-bindings/interrupt-controller/arm-gic.h>
1910 #include <dt-bindings/interrupt-controller/irq.h>
2011 
2112 / {
13
+	#address-cells = <1>;
14
+	#size-cells = <1>;
15
+
2216 	model = "Qualcomm Technologies, Inc. IPQ4019";
2317 	compatible = "qcom,ipq4019";
2418 	interrupt-parent = <&intc>;
....@@ -52,78 +46,91 @@
5246 		cpu@0 {
5347 			device_type = "cpu";
5448 			compatible = "arm,cortex-a7";
55
-			enable-method = "qcom,kpss-acc-v1";
49
+			enable-method = "qcom,kpss-acc-v2";
50
+			next-level-cache = <&L2>;
5651 			qcom,acc = <&acc0>;
5752 			qcom,saw = <&saw0>;
5853 			reg = <0x0>;
5954 			clocks = <&gcc GCC_APPS_CLK_SRC>;
6055 			clock-frequency = <0>;
61
-			operating-points = <
62
-				/* kHz	uV (fixed) */
63
-				48000	1100000
64
-				200000	1100000
65
-				500000	1100000
66
-				716000  1100000
67
-			>;
6856 			clock-latency = <256000>;
57
+			operating-points-v2 = <&cpu0_opp_table>;
6958 		};
7059 
7160 		cpu@1 {
7261 			device_type = "cpu";
7362 			compatible = "arm,cortex-a7";
74
-			enable-method = "qcom,kpss-acc-v1";
63
+			enable-method = "qcom,kpss-acc-v2";
64
+			next-level-cache = <&L2>;
7565 			qcom,acc = <&acc1>;
7666 			qcom,saw = <&saw1>;
7767 			reg = <0x1>;
7868 			clocks = <&gcc GCC_APPS_CLK_SRC>;
7969 			clock-frequency = <0>;
80
-			operating-points = <
81
-				/* kHz	uV (fixed) */
82
-				48000	1100000
83
-				200000	1100000
84
-				500000	1100000
85
-				666000	1100000
86
-			>;
8770 			clock-latency = <256000>;
71
+			operating-points-v2 = <&cpu0_opp_table>;
8872 		};
8973 
9074 		cpu@2 {
9175 			device_type = "cpu";
9276 			compatible = "arm,cortex-a7";
93
-			enable-method = "qcom,kpss-acc-v1";
77
+			enable-method = "qcom,kpss-acc-v2";
78
+			next-level-cache = <&L2>;
9479 			qcom,acc = <&acc2>;
9580 			qcom,saw = <&saw2>;
9681 			reg = <0x2>;
9782 			clocks = <&gcc GCC_APPS_CLK_SRC>;
9883 			clock-frequency = <0>;
99
-			operating-points = <
100
-				/* kHz	uV (fixed) */
101
-				48000	1100000
102
-				200000	1100000
103
-				500000	1100000
104
-				666000	1100000
105
-			>;
10684 			clock-latency = <256000>;
85
+			operating-points-v2 = <&cpu0_opp_table>;
10786 		};
10887 
10988 		cpu@3 {
11089 			device_type = "cpu";
11190 			compatible = "arm,cortex-a7";
112
-			enable-method = "qcom,kpss-acc-v1";
91
+			enable-method = "qcom,kpss-acc-v2";
92
+			next-level-cache = <&L2>;
11393 			qcom,acc = <&acc3>;
11494 			qcom,saw = <&saw3>;
11595 			reg = <0x3>;
11696 			clocks = <&gcc GCC_APPS_CLK_SRC>;
11797 			clock-frequency = <0>;
118
-			operating-points = <
119
-				/* kHz	uV (fixed) */
120
-				48000	1100000
121
-				200000	1100000
122
-				500000	1100000
123
-				666000	1100000
124
-			>;
12598 			clock-latency = <256000>;
99
+			operating-points-v2 = <&cpu0_opp_table>;
126100 		};
101
+
102
+		L2: l2-cache {
103
+			compatible = "cache";
104
+			cache-level = <2>;
105
+			qcom,saw = <&saw_l2>;
106
+		};
107
+	};
108
+
109
+	cpu0_opp_table: opp_table0 {
110
+		compatible = "operating-points-v2";
111
+		opp-shared;
112
+
113
+		opp-48000000 {
114
+			opp-hz = /bits/ 64 <48000000>;
115
+			clock-latency-ns = <256000>;
116
+		};
117
+		opp-200000000 {
118
+			opp-hz = /bits/ 64 <200000000>;
119
+			clock-latency-ns = <256000>;
120
+		};
121
+		opp-500000000 {
122
+			opp-hz = /bits/ 64 <500000000>;
123
+			clock-latency-ns = <256000>;
124
+		};
125
+		opp-716000000 {
126
+			opp-hz = /bits/ 64 <716000000>;
127
+			clock-latency-ns = <256000>;
128
+ 		};
129
+	};
130
+
131
+	memory {
132
+		device_type = "memory";
133
+		reg = <0x0 0x0>;
127134 	};
128135 
129136 	pmu {
....@@ -135,7 +142,8 @@
135142 	clocks {
136143 		sleep_clk: sleep_clk {
137144 			compatible = "fixed-clock";
138
-			clock-frequency = <32768>;
145
+			clock-frequency = <32000>;
146
+			clock-output-names = "gcc_sleep_clk_src";
139147 			#clock-cells = <0>;
140148 		};
141149 
....@@ -159,6 +167,7 @@
159167 			     <1 4 0xf08>,
160168 			     <1 1 0xf08>;
161169 		clock-frequency = <48000000>;
170
+		always-on;
162171 	};
163172 
164173 	soc {
....@@ -194,10 +203,23 @@
194203 			compatible = "qcom,ipq4019-pinctrl";
195204 			reg = <0x01000000 0x300000>;
196205 			gpio-controller;
206
+			gpio-ranges = <&tlmm 0 0 100>;
197207 			#gpio-cells = <2>;
198208 			interrupt-controller;
199209 			#interrupt-cells = <2>;
200210 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
211
+		};
212
+
213
+		sdhci: sdhci@7824900 {
214
+			compatible = "qcom,sdhci-msm-v4";
215
+			reg = <0x7824900 0x11c>, <0x7824000 0x800>;
216
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
217
+			interrupt-names = "hc_irq", "pwr_irq";
218
+			bus-width = <8>;
219
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
220
+				 <&gcc GCC_DCD_XO_CLK>;
221
+			clock-names = "core", "iface", "xo";
222
+			status = "disabled";
201223 		};
202224 
203225 		blsp_dma: dma@7884000 {
....@@ -291,49 +313,55 @@
291313 			status = "disabled";
292314 		};
293315 
294
-                acc0: clock-controller@b088000 {
295
-                        compatible = "qcom,kpss-acc-v1";
296
-                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
297
-                };
316
+		acc0: clock-controller@b088000 {
317
+			compatible = "qcom,kpss-acc-v2";
318
+			reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
319
+		};
298320 
299
-                acc1: clock-controller@b098000 {
300
-                        compatible = "qcom,kpss-acc-v1";
301
-                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
302
-                };
321
+		acc1: clock-controller@b098000 {
322
+			compatible = "qcom,kpss-acc-v2";
323
+			reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
324
+		};
303325 
304
-                acc2: clock-controller@b0a8000 {
305
-                        compatible = "qcom,kpss-acc-v1";
306
-                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
307
-                };
326
+		acc2: clock-controller@b0a8000 {
327
+			compatible = "qcom,kpss-acc-v2";
328
+			reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
329
+		};
308330 
309
-                acc3: clock-controller@b0b8000 {
310
-                        compatible = "qcom,kpss-acc-v1";
311
-                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
312
-                };
331
+		acc3: clock-controller@b0b8000 {
332
+			compatible = "qcom,kpss-acc-v2";
333
+			reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
334
+		};
313335 
314
-                saw0: regulator@b089000 {
315
-                        compatible = "qcom,saw2";
336
+		saw0: regulator@b089000 {
337
+			compatible = "qcom,saw2";
316338 			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
317339                         regulator;
318
-                };
340
+		};
319341 
320
-                saw1: regulator@b099000 {
321
-                        compatible = "qcom,saw2";
322
-                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
323
-                        regulator;
324
-                };
342
+		saw1: regulator@b099000 {
343
+			compatible = "qcom,saw2";
344
+			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
345
+			regulator;
346
+		};
325347 
326
-                saw2: regulator@b0a9000 {
327
-                        compatible = "qcom,saw2";
328
-                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
329
-                        regulator;
330
-                };
348
+		saw2: regulator@b0a9000 {
349
+			compatible = "qcom,saw2";
350
+			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
351
+			regulator;
352
+		};
331353 
332
-                saw3: regulator@b0b9000 {
333
-                        compatible = "qcom,saw2";
334
-                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
335
-                        regulator;
336
-                };
354
+		saw3: regulator@b0b9000 {
355
+			compatible = "qcom,saw2";
356
+			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
357
+			regulator;
358
+		};
359
+
360
+		saw_l2: regulator@b012000 {
361
+			compatible = "qcom,saw2";
362
+			reg = <0xb012000 0x1000>;
363
+			regulator;
364
+		};
337365 
338366 		blsp1_uart1: serial@78af000 {
339367 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
....@@ -386,8 +414,8 @@
386414 			#address-cells = <3>;
387415 			#size-cells = <2>;
388416 
389
-			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
390
-				 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
417
+			ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
418
+				 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
391419 
392420 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
393421 			interrupt-names = "msi";
....@@ -550,5 +578,33 @@
550578 					  "legacy";
551579 			status = "disabled";
552580 		};
581
+
582
+		mdio: mdio@90000 {
583
+			#address-cells = <1>;
584
+			#size-cells = <0>;
585
+			compatible = "qcom,ipq4019-mdio";
586
+			reg = <0x90000 0x64>;
587
+			status = "disabled";
588
+
589
+			ethphy0: ethernet-phy@0 {
590
+				reg = <0>;
591
+			};
592
+
593
+			ethphy1: ethernet-phy@1 {
594
+				reg = <1>;
595
+			};
596
+
597
+			ethphy2: ethernet-phy@2 {
598
+				reg = <2>;
599
+			};
600
+
601
+			ethphy3: ethernet-phy@3 {
602
+				reg = <3>;
603
+			};
604
+
605
+			ethphy4: ethernet-phy@4 {
606
+				reg = <4>;
607
+			};
608
+		};
553609 	};
554610 };