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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2012 Marvell Technology Group Ltd. |
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| 3 | 4 | * Author: Haojian Zhuang <haojian.zhuang@marvell.com> |
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| 4 | | - * |
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| 5 | | - * This program is free software; you can redistribute it and/or modify |
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| 6 | | - * it under the terms of the GNU General Public License version 2 as |
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| 7 | | - * publishhed by the Free Software Foundation. |
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| 8 | 5 | */ |
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| 9 | 6 | |
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| 10 | | -#include "skeleton.dtsi" |
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| 11 | 7 | #include <dt-bindings/clock/marvell,pxa910.h> |
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| 12 | 8 | |
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| 13 | 9 | / { |
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| 10 | + #address-cells = <1>; |
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| 11 | + #size-cells = <1>; |
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| 12 | + |
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| 14 | 13 | aliases { |
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| 15 | 14 | serial0 = &uart1; |
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| 16 | 15 | serial1 = &uart2; |
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| .. | .. |
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| 68 | 67 | status = "disabled"; |
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| 69 | 68 | }; |
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| 70 | 69 | |
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| 71 | | - uart1: uart@d4017000 { |
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| 72 | | - compatible = "mrvl,mmp-uart"; |
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| 70 | + uart1: serial@d4017000 { |
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| 71 | + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
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| 73 | 72 | reg = <0xd4017000 0x1000>; |
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| 73 | + reg-shift = <2>; |
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| 74 | 74 | interrupts = <27>; |
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| 75 | 75 | clocks = <&soc_clocks PXA910_CLK_UART0>; |
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| 76 | 76 | resets = <&soc_clocks PXA910_CLK_UART0>; |
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| 77 | 77 | status = "disabled"; |
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| 78 | 78 | }; |
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| 79 | 79 | |
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| 80 | | - uart2: uart@d4018000 { |
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| 81 | | - compatible = "mrvl,mmp-uart"; |
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| 80 | + uart2: serial@d4018000 { |
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| 81 | + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
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| 82 | 82 | reg = <0xd4018000 0x1000>; |
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| 83 | + reg-shift = <2>; |
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| 83 | 84 | interrupts = <28>; |
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| 84 | 85 | clocks = <&soc_clocks PXA910_CLK_UART1>; |
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| 85 | 86 | resets = <&soc_clocks PXA910_CLK_UART1>; |
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| 86 | 87 | status = "disabled"; |
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| 87 | 88 | }; |
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| 88 | 89 | |
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| 89 | | - uart3: uart@d4036000 { |
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| 90 | | - compatible = "mrvl,mmp-uart"; |
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| 90 | + uart3: serial@d4036000 { |
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| 91 | + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; |
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| 91 | 92 | reg = <0xd4036000 0x1000>; |
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| 93 | + reg-shift = <2>; |
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| 92 | 94 | interrupts = <59>; |
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| 93 | 95 | clocks = <&soc_clocks PXA910_CLK_UART2>; |
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| 94 | 96 | resets = <&soc_clocks PXA910_CLK_UART2>; |
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| .. | .. |
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| 107 | 109 | clocks = <&soc_clocks PXA910_CLK_GPIO>; |
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| 108 | 110 | resets = <&soc_clocks PXA910_CLK_GPIO>; |
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| 109 | 111 | interrupt-controller; |
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| 110 | | - #interrupt-cells = <1>; |
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| 112 | + #interrupt-cells = <2>; |
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| 111 | 113 | ranges; |
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| 112 | 114 | |
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| 113 | 115 | gcb0: gpio@d4019000 { |
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| .. | .. |
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| 153 | 155 | rtc: rtc@d4010000 { |
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| 154 | 156 | compatible = "mrvl,mmp-rtc"; |
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| 155 | 157 | reg = <0xd4010000 0x1000>; |
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| 156 | | - interrupts = <5 6>; |
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| 158 | + interrupts = <5>, <6>; |
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| 157 | 159 | interrupt-names = "rtc 1Hz", "rtc alarm"; |
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| 158 | 160 | clocks = <&soc_clocks PXA910_CLK_RTC>; |
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| 159 | 161 | resets = <&soc_clocks PXA910_CLK_RTC>; |
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