| .. | .. |
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| 4 | 4 | // Copyright 2011 Linaro Ltd. |
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| 5 | 5 | |
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| 6 | 6 | #include <dt-bindings/clock/imx6qdl-clock.h> |
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| 7 | +#include <dt-bindings/input/input.h> |
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| 7 | 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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| 8 | 9 | |
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| 9 | 10 | / { |
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| .. | .. |
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| 13 | 14 | * The decompressor and also some bootloaders rely on a |
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| 14 | 15 | * pre-existing /chosen node to be available to insert the |
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| 15 | 16 | * command line and merge other ATAGS info. |
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| 16 | | - * Also for U-Boot there must be a pre-existing /memory node. |
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| 17 | 17 | */ |
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| 18 | 18 | chosen {}; |
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| 19 | | - memory { device_type = "memory"; }; |
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| 20 | 19 | |
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| 21 | 20 | aliases { |
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| 22 | 21 | ethernet0 = &fec; |
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| .. | .. |
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| 46 | 45 | spi1 = &ecspi2; |
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| 47 | 46 | spi2 = &ecspi3; |
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| 48 | 47 | spi3 = &ecspi4; |
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| 48 | + usb0 = &usbotg; |
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| 49 | + usb1 = &usbh1; |
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| 50 | + usb2 = &usbh2; |
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| 51 | + usb3 = &usbh3; |
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| 49 | 52 | usbphy0 = &usbphy1; |
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| 50 | 53 | usbphy1 = &usbphy2; |
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| 51 | 54 | }; |
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| .. | .. |
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| 68 | 71 | #clock-cells = <0>; |
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| 69 | 72 | clock-frequency = <24000000>; |
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| 70 | 73 | }; |
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| 71 | | - }; |
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| 72 | | - |
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| 73 | | - tempmon: tempmon { |
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| 74 | | - compatible = "fsl,imx6q-tempmon"; |
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| 75 | | - interrupt-parent = <&gpc>; |
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| 76 | | - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
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| 77 | | - fsl,tempmon = <&anatop>; |
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| 78 | | - fsl,tempmon-data = <&ocotp>; |
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| 79 | | - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
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| 80 | 74 | }; |
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| 81 | 75 | |
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| 82 | 76 | ldb: ldb { |
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| .. | .. |
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| 139 | 133 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
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| 140 | 134 | }; |
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| 141 | 135 | |
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| 136 | + usbphynop1: usbphynop1 { |
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| 137 | + compatible = "usb-nop-xceiv"; |
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| 138 | + #phy-cells = <0>; |
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| 139 | + }; |
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| 140 | + |
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| 141 | + usbphynop2: usbphynop2 { |
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| 142 | + compatible = "usb-nop-xceiv"; |
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| 143 | + #phy-cells = <0>; |
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| 144 | + }; |
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| 145 | + |
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| 142 | 146 | soc { |
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| 143 | 147 | #address-cells = <1>; |
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| 144 | 148 | #size-cells = <1>; |
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| .. | .. |
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| 146 | 150 | interrupt-parent = <&gpc>; |
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| 147 | 151 | ranges; |
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| 148 | 152 | |
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| 149 | | - dma_apbh: dma-apbh@110000 { |
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| 153 | + dma_apbh: dma-controller@110000 { |
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| 150 | 154 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
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| 151 | 155 | reg = <0x00110000 0x2000>; |
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| 152 | 156 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
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| .. | .. |
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| 159 | 163 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
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| 160 | 164 | }; |
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| 161 | 165 | |
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| 162 | | - gpmi: gpmi-nand@112000 { |
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| 166 | + gpmi: nand-controller@112000 { |
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| 163 | 167 | compatible = "fsl,imx6q-gpmi-nand"; |
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| 164 | | - #address-cells = <1>; |
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| 165 | | - #size-cells = <1>; |
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| 166 | 168 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
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| 167 | 169 | reg-names = "gpmi-nand", "bch"; |
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| 168 | 170 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 216 | 218 | <&clks IMX6QDL_CLK_GPU3D_SHADER>; |
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| 217 | 219 | clock-names = "bus", "core", "shader"; |
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| 218 | 220 | power-domains = <&pd_pu>; |
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| 221 | + #cooling-cells = <2>; |
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| 219 | 222 | }; |
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| 220 | 223 | |
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| 221 | 224 | gpu_2d: gpu@134000 { |
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| .. | .. |
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| 226 | 229 | <&clks IMX6QDL_CLK_GPU2D_CORE>; |
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| 227 | 230 | clock-names = "bus", "core"; |
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| 228 | 231 | power-domains = <&pd_pu>; |
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| 232 | + #cooling-cells = <2>; |
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| 229 | 233 | }; |
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| 230 | 234 | |
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| 231 | 235 | timer@a00600 { |
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| .. | .. |
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| 245 | 249 | interrupt-parent = <&intc>; |
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| 246 | 250 | }; |
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| 247 | 251 | |
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| 248 | | - L2: l2-cache@a02000 { |
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| 252 | + L2: cache-controller@a02000 { |
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| 249 | 253 | compatible = "arm,pl310-cache"; |
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| 250 | 254 | reg = <0x00a02000 0x1000>; |
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| 251 | 255 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 268 | 272 | ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
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| 269 | 273 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
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| 270 | 274 | num-lanes = <1>; |
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| 275 | + num-viewport = <4>; |
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| 271 | 276 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
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| 272 | 277 | interrupt-names = "msi"; |
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| 273 | 278 | #interrupt-cells = <1>; |
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| .. | .. |
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| 283 | 288 | status = "disabled"; |
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| 284 | 289 | }; |
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| 285 | 290 | |
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| 286 | | - aips-bus@2000000 { /* AIPS1 */ |
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| 291 | + bus@2000000 { /* AIPS1 */ |
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| 287 | 292 | compatible = "fsl,aips-bus", "simple-bus"; |
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| 288 | 293 | #address-cells = <1>; |
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| 289 | 294 | #size-cells = <1>; |
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| .. | .. |
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| 317 | 322 | status = "disabled"; |
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| 318 | 323 | }; |
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| 319 | 324 | |
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| 320 | | - ecspi1: ecspi@2008000 { |
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| 325 | + ecspi1: spi@2008000 { |
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| 321 | 326 | #address-cells = <1>; |
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| 322 | 327 | #size-cells = <0>; |
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| 323 | 328 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
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| .. | .. |
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| 331 | 336 | status = "disabled"; |
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| 332 | 337 | }; |
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| 333 | 338 | |
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| 334 | | - ecspi2: ecspi@200c000 { |
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| 339 | + ecspi2: spi@200c000 { |
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| 335 | 340 | #address-cells = <1>; |
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| 336 | 341 | #size-cells = <0>; |
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| 337 | 342 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
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| .. | .. |
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| 345 | 350 | status = "disabled"; |
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| 346 | 351 | }; |
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| 347 | 352 | |
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| 348 | | - ecspi3: ecspi@2010000 { |
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| 353 | + ecspi3: spi@2010000 { |
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| 349 | 354 | #address-cells = <1>; |
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| 350 | 355 | #size-cells = <0>; |
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| 351 | 356 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
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| .. | .. |
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| 359 | 364 | status = "disabled"; |
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| 360 | 365 | }; |
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| 361 | 366 | |
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| 362 | | - ecspi4: ecspi@2014000 { |
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| 367 | + ecspi4: spi@2014000 { |
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| 363 | 368 | #address-cells = <1>; |
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| 364 | 369 | #size-cells = <0>; |
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| 365 | 370 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
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| .. | .. |
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| 498 | 503 | }; |
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| 499 | 504 | |
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| 500 | 505 | pwm1: pwm@2080000 { |
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| 501 | | - #pwm-cells = <2>; |
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| 506 | + #pwm-cells = <3>; |
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| 502 | 507 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
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| 503 | 508 | reg = <0x02080000 0x4000>; |
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| 504 | 509 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 509 | 514 | }; |
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| 510 | 515 | |
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| 511 | 516 | pwm2: pwm@2084000 { |
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| 512 | | - #pwm-cells = <2>; |
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| 517 | + #pwm-cells = <3>; |
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| 513 | 518 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
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| 514 | 519 | reg = <0x02084000 0x4000>; |
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| 515 | 520 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 520 | 525 | }; |
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| 521 | 526 | |
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| 522 | 527 | pwm3: pwm@2088000 { |
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| 523 | | - #pwm-cells = <2>; |
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| 528 | + #pwm-cells = <3>; |
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| 524 | 529 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
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| 525 | 530 | reg = <0x02088000 0x4000>; |
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| 526 | 531 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 531 | 536 | }; |
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| 532 | 537 | |
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| 533 | 538 | pwm4: pwm@208c000 { |
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| 534 | | - #pwm-cells = <2>; |
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| 539 | + #pwm-cells = <3>; |
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| 535 | 540 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
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| 536 | 541 | reg = <0x0208c000 0x4000>; |
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| 537 | 542 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 548 | 553 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
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| 549 | 554 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; |
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| 550 | 555 | clock-names = "ipg", "per"; |
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| 556 | + fsl,stop-mode = <&gpr 0x34 28 0x10 17>; |
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| 551 | 557 | status = "disabled"; |
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| 552 | 558 | }; |
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| 553 | 559 | |
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| .. | .. |
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| 558 | 564 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
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| 559 | 565 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; |
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| 560 | 566 | clock-names = "ipg", "per"; |
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| 567 | + fsl,stop-mode = <&gpr 0x34 29 0x10 18>; |
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| 561 | 568 | status = "disabled"; |
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| 562 | 569 | }; |
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| 563 | 570 | |
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| 564 | | - gpt: gpt@2098000 { |
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| 571 | + gpt: timer@2098000 { |
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| 565 | 572 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
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| 566 | 573 | reg = <0x02098000 0x4000>; |
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| 567 | 574 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 648 | 655 | #interrupt-cells = <2>; |
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| 649 | 656 | }; |
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| 650 | 657 | |
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| 651 | | - kpp: kpp@20b8000 { |
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| 658 | + kpp: keypad@20b8000 { |
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| 652 | 659 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
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| 653 | 660 | reg = <0x020b8000 0x4000>; |
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| 654 | 661 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 656 | 663 | status = "disabled"; |
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| 657 | 664 | }; |
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| 658 | 665 | |
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| 659 | | - wdog1: wdog@20bc000 { |
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| 666 | + wdog1: watchdog@20bc000 { |
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| 660 | 667 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
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| 661 | 668 | reg = <0x020bc000 0x4000>; |
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| 662 | 669 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
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| 663 | | - clocks = <&clks IMX6QDL_CLK_DUMMY>; |
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| 670 | + clocks = <&clks IMX6QDL_CLK_IPG>; |
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| 664 | 671 | }; |
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| 665 | 672 | |
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| 666 | | - wdog2: wdog@20c0000 { |
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| 673 | + wdog2: watchdog@20c0000 { |
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| 667 | 674 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
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| 668 | 675 | reg = <0x020c0000 0x4000>; |
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| 669 | 676 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
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| 670 | | - clocks = <&clks IMX6QDL_CLK_DUMMY>; |
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| 677 | + clocks = <&clks IMX6QDL_CLK_IPG>; |
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| 671 | 678 | status = "disabled"; |
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| 672 | 679 | }; |
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| 673 | 680 | |
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| 674 | | - clks: ccm@20c4000 { |
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| 681 | + clks: clock-controller@20c4000 { |
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| 675 | 682 | compatible = "fsl,imx6q-ccm"; |
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| 676 | 683 | reg = <0x020c4000 0x4000>; |
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| 677 | 684 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
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| .. | .. |
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| 680 | 687 | }; |
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| 681 | 688 | |
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| 682 | 689 | anatop: anatop@20c8000 { |
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| 683 | | - compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
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| 690 | + compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; |
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| 684 | 691 | reg = <0x020c8000 0x1000>; |
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| 685 | 692 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
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| 686 | 693 | <0 54 IRQ_TYPE_LEVEL_HIGH>, |
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| .. | .. |
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| 753 | 760 | regulator-name = "vddpu"; |
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| 754 | 761 | regulator-min-microvolt = <725000>; |
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| 755 | 762 | regulator-max-microvolt = <1450000>; |
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| 756 | | - regulator-enable-ramp-delay = <150>; |
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| 763 | + regulator-enable-ramp-delay = <380>; |
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| 757 | 764 | anatop-reg-offset = <0x140>; |
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| 758 | 765 | anatop-vol-bit-shift = <9>; |
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| 759 | 766 | anatop-vol-bit-width = <5>; |
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| .. | .. |
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| 780 | 787 | anatop-min-bit-val = <1>; |
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| 781 | 788 | anatop-min-voltage = <725000>; |
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| 782 | 789 | anatop-max-voltage = <1450000>; |
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| 790 | + }; |
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| 791 | + |
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| 792 | + tempmon: tempmon { |
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| 793 | + compatible = "fsl,imx6q-tempmon"; |
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| 794 | + interrupt-parent = <&gpc>; |
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| 795 | + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
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| 796 | + fsl,tempmon = <&anatop>; |
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| 797 | + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; |
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| 798 | + nvmem-cell-names = "calib", "temp_grade"; |
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| 799 | + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
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| 800 | + #thermal-sensor-cells = <0>; |
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| 783 | 801 | }; |
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| 784 | 802 | }; |
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| 785 | 803 | |
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| .. | .. |
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| 820 | 838 | status = "disabled"; |
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| 821 | 839 | }; |
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| 822 | 840 | |
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| 841 | + snvs_pwrkey: snvs-powerkey { |
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| 842 | + compatible = "fsl,sec-v4.0-pwrkey"; |
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| 843 | + regmap = <&snvs>; |
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| 844 | + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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| 845 | + linux,keycode = <KEY_POWER>; |
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| 846 | + wakeup-source; |
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| 847 | + status = "disabled"; |
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| 848 | + }; |
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| 849 | + |
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| 823 | 850 | snvs_lpgpr: snvs-lpgpr { |
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| 824 | 851 | compatible = "fsl,imx6q-snvs-lpgpr"; |
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| 825 | 852 | }; |
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| .. | .. |
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| 835 | 862 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
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| 836 | 863 | }; |
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| 837 | 864 | |
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| 838 | | - src: src@20d8000 { |
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| 865 | + src: reset-controller@20d8000 { |
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| 839 | 866 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
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| 840 | 867 | reg = <0x020d8000 0x4000>; |
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| 841 | 868 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
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| .. | .. |
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| 848 | 875 | reg = <0x020dc000 0x4000>; |
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| 849 | 876 | interrupt-controller; |
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| 850 | 877 | #interrupt-cells = <3>; |
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| 851 | | - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
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| 852 | | - <0 90 IRQ_TYPE_LEVEL_HIGH>; |
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| 878 | + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; |
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| 853 | 879 | interrupt-parent = <&intc>; |
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| 854 | 880 | clocks = <&clks IMX6QDL_CLK_IPG>; |
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| 855 | 881 | clock-names = "ipg"; |
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| .. | .. |
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| 886 | 912 | }; |
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| 887 | 913 | }; |
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| 888 | 914 | |
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| 889 | | - iomuxc: iomuxc@20e0000 { |
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| 915 | + iomuxc: pinctrl@20e0000 { |
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| 890 | 916 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; |
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| 891 | 917 | reg = <0x20e0000 0x4000>; |
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| 892 | 918 | }; |
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| .. | .. |
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| 901 | 927 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
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| 902 | 928 | }; |
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| 903 | 929 | |
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| 904 | | - sdma: sdma@20ec000 { |
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| 930 | + sdma: dma-controller@20ec000 { |
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| 905 | 931 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
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| 906 | 932 | reg = <0x020ec000 0x4000>; |
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| 907 | 933 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 913 | 939 | }; |
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| 914 | 940 | }; |
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| 915 | 941 | |
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| 916 | | - aips-bus@2100000 { /* AIPS2 */ |
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| 942 | + bus@2100000 { /* AIPS2 */ |
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| 917 | 943 | compatible = "fsl,aips-bus", "simple-bus"; |
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| 918 | 944 | #address-cells = <1>; |
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| 919 | 945 | #size-cells = <1>; |
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| 920 | 946 | reg = <0x02100000 0x100000>; |
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| 921 | 947 | ranges; |
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| 922 | 948 | |
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| 923 | | - crypto: caam@2100000 { |
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| 949 | + crypto: crypto@2100000 { |
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| 924 | 950 | compatible = "fsl,sec-v4.0"; |
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| 925 | 951 | #address-cells = <1>; |
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| 926 | 952 | #size-cells = <1>; |
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| .. | .. |
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| 932 | 958 | <&clks IMX6QDL_CLK_EIM_SLOW>; |
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| 933 | 959 | clock-names = "mem", "aclk", "ipg", "emi_slow"; |
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| 934 | 960 | |
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| 935 | | - sec_jr0: jr0@1000 { |
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| 961 | + sec_jr0: jr@1000 { |
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| 936 | 962 | compatible = "fsl,sec-v4.0-job-ring"; |
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| 937 | 963 | reg = <0x1000 0x1000>; |
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| 938 | 964 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
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| 939 | 965 | }; |
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| 940 | 966 | |
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| 941 | | - sec_jr1: jr1@2000 { |
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| 967 | + sec_jr1: jr@2000 { |
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| 942 | 968 | compatible = "fsl,sec-v4.0-job-ring"; |
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| 943 | 969 | reg = <0x2000 0x1000>; |
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| 944 | 970 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
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| .. | .. |
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| 981 | 1007 | reg = <0x02184400 0x200>; |
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| 982 | 1008 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
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| 983 | 1009 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
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| 1010 | + fsl,usbphy = <&usbphynop1>; |
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| 1011 | + phy_type = "hsic"; |
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| 984 | 1012 | fsl,usbmisc = <&usbmisc 2>; |
|---|
| 985 | 1013 | dr_mode = "host"; |
|---|
| 986 | 1014 | ahb-burst-config = <0x0>; |
|---|
| .. | .. |
|---|
| 994 | 1022 | reg = <0x02184600 0x200>; |
|---|
| 995 | 1023 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| 996 | 1024 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
|---|
| 1025 | + fsl,usbphy = <&usbphynop2>; |
|---|
| 1026 | + phy_type = "hsic"; |
|---|
| 997 | 1027 | fsl,usbmisc = <&usbmisc 3>; |
|---|
| 998 | 1028 | dr_mode = "host"; |
|---|
| 999 | 1029 | ahb-burst-config = <0x0>; |
|---|
| .. | .. |
|---|
| 1017 | 1047 | <0 119 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| 1018 | 1048 | clocks = <&clks IMX6QDL_CLK_ENET>, |
|---|
| 1019 | 1049 | <&clks IMX6QDL_CLK_ENET>, |
|---|
| 1050 | + <&clks IMX6QDL_CLK_ENET_REF>, |
|---|
| 1020 | 1051 | <&clks IMX6QDL_CLK_ENET_REF>; |
|---|
| 1021 | | - clock-names = "ipg", "ahb", "ptp"; |
|---|
| 1052 | + clock-names = "ipg", "ahb", "ptp", "enet_out"; |
|---|
| 1053 | + fsl,stop-mode = <&gpr 0x34 27>; |
|---|
| 1022 | 1054 | status = "disabled"; |
|---|
| 1023 | 1055 | }; |
|---|
| 1024 | 1056 | |
|---|
| .. | .. |
|---|
| 1029 | 1061 | <0 126 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| 1030 | 1062 | }; |
|---|
| 1031 | 1063 | |
|---|
| 1032 | | - usdhc1: usdhc@2190000 { |
|---|
| 1064 | + usdhc1: mmc@2190000 { |
|---|
| 1033 | 1065 | compatible = "fsl,imx6q-usdhc"; |
|---|
| 1034 | 1066 | reg = <0x02190000 0x4000>; |
|---|
| 1035 | 1067 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| .. | .. |
|---|
| 1041 | 1073 | status = "disabled"; |
|---|
| 1042 | 1074 | }; |
|---|
| 1043 | 1075 | |
|---|
| 1044 | | - usdhc2: usdhc@2194000 { |
|---|
| 1076 | + usdhc2: mmc@2194000 { |
|---|
| 1045 | 1077 | compatible = "fsl,imx6q-usdhc"; |
|---|
| 1046 | 1078 | reg = <0x02194000 0x4000>; |
|---|
| 1047 | 1079 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| .. | .. |
|---|
| 1053 | 1085 | status = "disabled"; |
|---|
| 1054 | 1086 | }; |
|---|
| 1055 | 1087 | |
|---|
| 1056 | | - usdhc3: usdhc@2198000 { |
|---|
| 1088 | + usdhc3: mmc@2198000 { |
|---|
| 1057 | 1089 | compatible = "fsl,imx6q-usdhc"; |
|---|
| 1058 | 1090 | reg = <0x02198000 0x4000>; |
|---|
| 1059 | 1091 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| .. | .. |
|---|
| 1065 | 1097 | status = "disabled"; |
|---|
| 1066 | 1098 | }; |
|---|
| 1067 | 1099 | |
|---|
| 1068 | | - usdhc4: usdhc@219c000 { |
|---|
| 1100 | + usdhc4: mmc@219c000 { |
|---|
| 1069 | 1101 | compatible = "fsl,imx6q-usdhc"; |
|---|
| 1070 | 1102 | reg = <0x0219c000 0x4000>; |
|---|
| 1071 | 1103 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
|---|
| .. | .. |
|---|
| 1111 | 1143 | reg = <0x021ac000 0x4000>; |
|---|
| 1112 | 1144 | }; |
|---|
| 1113 | 1145 | |
|---|
| 1114 | | - mmdc0: mmdc@21b0000 { /* MMDC0 */ |
|---|
| 1146 | + mmdc0: memory-controller@21b0000 { /* MMDC0 */ |
|---|
| 1115 | 1147 | compatible = "fsl,imx6q-mmdc"; |
|---|
| 1116 | 1148 | reg = <0x021b0000 0x4000>; |
|---|
| 1149 | + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; |
|---|
| 1117 | 1150 | }; |
|---|
| 1118 | 1151 | |
|---|
| 1119 | | - mmdc1: mmdc@21b4000 { /* MMDC1 */ |
|---|
| 1152 | + mmdc1: memory-controller@21b4000 { /* MMDC1 */ |
|---|
| 1153 | + compatible = "fsl,imx6q-mmdc"; |
|---|
| 1120 | 1154 | reg = <0x021b4000 0x4000>; |
|---|
| 1155 | + status = "disabled"; |
|---|
| 1121 | 1156 | }; |
|---|
| 1122 | 1157 | |
|---|
| 1123 | 1158 | weim: weim@21b8000 { |
|---|
| .. | .. |
|---|
| 1131 | 1166 | status = "disabled"; |
|---|
| 1132 | 1167 | }; |
|---|
| 1133 | 1168 | |
|---|
| 1134 | | - ocotp: ocotp@21bc000 { |
|---|
| 1169 | + ocotp: efuse@21bc000 { |
|---|
| 1135 | 1170 | compatible = "fsl,imx6q-ocotp", "syscon"; |
|---|
| 1136 | 1171 | reg = <0x021bc000 0x4000>; |
|---|
| 1137 | 1172 | clocks = <&clks IMX6QDL_CLK_IIM>; |
|---|
| 1173 | + #address-cells = <1>; |
|---|
| 1174 | + #size-cells = <1>; |
|---|
| 1175 | + |
|---|
| 1176 | + cpu_speed_grade: speed-grade@10 { |
|---|
| 1177 | + reg = <0x10 4>; |
|---|
| 1178 | + }; |
|---|
| 1179 | + |
|---|
| 1180 | + tempmon_calib: calib@38 { |
|---|
| 1181 | + reg = <0x38 4>; |
|---|
| 1182 | + }; |
|---|
| 1183 | + |
|---|
| 1184 | + tempmon_temp_grade: temp-grade@20 { |
|---|
| 1185 | + reg = <0x20 4>; |
|---|
| 1186 | + }; |
|---|
| 1138 | 1187 | }; |
|---|
| 1139 | 1188 | |
|---|
| 1140 | 1189 | tzasc@21d0000 { /* TZASC1 */ |
|---|