| .. | .. |
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| 53 | 53 | &fec { |
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| 54 | 54 | pinctrl-names = "default"; |
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| 55 | 55 | pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; |
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| 56 | | - phy-mode = "rgmii"; |
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| 57 | | - phy-reset-duration = <2>; |
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| 56 | + phy-mode = "rgmii-id"; |
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| 57 | + |
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| 58 | + /* |
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| 59 | + * The PHY seems to require a long-enough reset duration to avoid |
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| 60 | + * some rare issues where the PHY gets stuck in an inconsistent and |
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| 61 | + * non-functional state at boot-up. 10ms proved to be fine . |
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| 62 | + */ |
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| 63 | + phy-reset-duration = <10>; |
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| 58 | 64 | phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
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| 59 | 65 | status = "okay"; |
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| 66 | + |
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| 67 | + mdio { |
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| 68 | + #address-cells = <1>; |
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| 69 | + #size-cells = <0>; |
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| 70 | + |
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| 71 | + /* |
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| 72 | + * The PHY can appear at either address 0 or 4 due to the |
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| 73 | + * configuration (LED) pin not being pulled sufficiently. |
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| 74 | + */ |
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| 75 | + ethernet-phy@0 { |
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| 76 | + reg = <0>; |
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| 77 | + qca,clk-out-frequency = <125000000>; |
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| 78 | + }; |
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| 79 | + |
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| 80 | + ethernet-phy@4 { |
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| 81 | + reg = <4>; |
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| 82 | + qca,clk-out-frequency = <125000000>; |
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| 83 | + }; |
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| 84 | + }; |
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| 60 | 85 | }; |
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| 61 | 86 | |
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| 62 | 87 | &iomuxc { |
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