| .. | .. |
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| 46 | 46 | */ |
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| 47 | 47 | |
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| 48 | 48 | #include <dt-bindings/gpio/gpio.h> |
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| 49 | +#include <dt-bindings/input/linux-event-codes.h> |
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| 50 | +#include <dt-bindings/interrupt-controller/irq.h> |
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| 49 | 51 | |
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| 50 | 52 | / { |
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| 51 | 53 | /* these are used by bootloader for disabling nodes */ |
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| .. | .. |
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| 66 | 68 | pwms = <&pwm4 0 5000000>; |
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| 67 | 69 | brightness-levels = <0 4 8 16 32 64 128 255>; |
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| 68 | 70 | default-brightness-level = <7>; |
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| 71 | + }; |
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| 72 | + |
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| 73 | + gpio-keys { |
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| 74 | + compatible = "gpio-keys"; |
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| 75 | + #address-cells = <1>; |
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| 76 | + #size-cells = <0>; |
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| 77 | + |
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| 78 | + user-pb { |
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| 79 | + label = "user_pb"; |
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| 80 | + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; |
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| 81 | + linux,code = <BTN_0>; |
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| 82 | + }; |
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| 83 | + |
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| 84 | + user-pb1x { |
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| 85 | + label = "user_pb1x"; |
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| 86 | + linux,code = <BTN_1>; |
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| 87 | + interrupt-parent = <&gsc>; |
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| 88 | + interrupts = <0>; |
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| 89 | + }; |
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| 90 | + |
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| 91 | + key-erased { |
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| 92 | + label = "key-erased"; |
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| 93 | + linux,code = <BTN_2>; |
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| 94 | + interrupt-parent = <&gsc>; |
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| 95 | + interrupts = <1>; |
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| 96 | + }; |
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| 97 | + |
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| 98 | + eeprom-wp { |
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| 99 | + label = "eeprom_wp"; |
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| 100 | + linux,code = <BTN_3>; |
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| 101 | + interrupt-parent = <&gsc>; |
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| 102 | + interrupts = <2>; |
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| 103 | + }; |
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| 104 | + |
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| 105 | + tamper { |
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| 106 | + label = "tamper"; |
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| 107 | + linux,code = <BTN_4>; |
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| 108 | + interrupt-parent = <&gsc>; |
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| 109 | + interrupts = <5>; |
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| 110 | + }; |
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| 111 | + |
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| 112 | + switch-hold { |
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| 113 | + label = "switch_hold"; |
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| 114 | + linux,code = <BTN_5>; |
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| 115 | + interrupt-parent = <&gsc>; |
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| 116 | + interrupts = <7>; |
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| 117 | + }; |
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| 69 | 118 | }; |
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| 70 | 119 | |
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| 71 | 120 | leds { |
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| .. | .. |
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| 94 | 143 | }; |
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| 95 | 144 | |
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| 96 | 145 | memory@10000000 { |
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| 146 | + device_type = "memory"; |
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| 97 | 147 | reg = <0x10000000 0x40000000>; |
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| 98 | 148 | }; |
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| 99 | 149 | |
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| .. | .. |
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| 204 | 254 | pinctrl-0 = <&pinctrl_i2c1>; |
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| 205 | 255 | status = "okay"; |
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| 206 | 256 | |
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| 207 | | - pca9555: gpio@23 { |
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| 257 | + gsc: gsc@20 { |
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| 258 | + compatible = "gw,gsc"; |
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| 259 | + reg = <0x20>; |
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| 260 | + interrupt-parent = <&gpio1>; |
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| 261 | + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; |
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| 262 | + interrupt-controller; |
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| 263 | + #interrupt-cells = <1>; |
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| 264 | + #size-cells = <0>; |
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| 265 | + |
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| 266 | + adc { |
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| 267 | + compatible = "gw,gsc-adc"; |
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| 268 | + #address-cells = <1>; |
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| 269 | + #size-cells = <0>; |
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| 270 | + |
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| 271 | + channel@0 { |
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| 272 | + gw,mode = <0>; |
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| 273 | + reg = <0x00>; |
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| 274 | + label = "temp"; |
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| 275 | + }; |
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| 276 | + |
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| 277 | + channel@2 { |
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| 278 | + gw,mode = <1>; |
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| 279 | + reg = <0x02>; |
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| 280 | + label = "vdd_vin"; |
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| 281 | + }; |
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| 282 | + |
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| 283 | + channel@5 { |
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| 284 | + gw,mode = <1>; |
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| 285 | + reg = <0x05>; |
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| 286 | + label = "vdd_3p3"; |
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| 287 | + }; |
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| 288 | + |
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| 289 | + channel@8 { |
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| 290 | + gw,mode = <1>; |
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| 291 | + reg = <0x08>; |
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| 292 | + label = "vdd_bat"; |
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| 293 | + }; |
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| 294 | + |
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| 295 | + channel@b { |
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| 296 | + gw,mode = <1>; |
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| 297 | + reg = <0x0b>; |
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| 298 | + label = "vdd_5p0"; |
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| 299 | + }; |
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| 300 | + |
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| 301 | + channel@e { |
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| 302 | + gw,mode = <1>; |
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| 303 | + reg = <0xe>; |
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| 304 | + label = "vdd_arm"; |
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| 305 | + }; |
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| 306 | + |
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| 307 | + channel@11 { |
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| 308 | + gw,mode = <1>; |
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| 309 | + reg = <0x11>; |
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| 310 | + label = "vdd_soc"; |
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| 311 | + }; |
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| 312 | + |
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| 313 | + channel@14 { |
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| 314 | + gw,mode = <1>; |
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| 315 | + reg = <0x14>; |
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| 316 | + label = "vdd_3p0"; |
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| 317 | + }; |
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| 318 | + |
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| 319 | + channel@17 { |
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| 320 | + gw,mode = <1>; |
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| 321 | + reg = <0x17>; |
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| 322 | + label = "vdd_1p5"; |
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| 323 | + }; |
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| 324 | + |
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| 325 | + channel@1d { |
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| 326 | + gw,mode = <1>; |
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| 327 | + reg = <0x1d>; |
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| 328 | + label = "vdd_1p8"; |
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| 329 | + }; |
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| 330 | + |
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| 331 | + channel@20 { |
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| 332 | + gw,mode = <1>; |
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| 333 | + reg = <0x20>; |
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| 334 | + label = "vdd_an1"; |
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| 335 | + }; |
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| 336 | + |
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| 337 | + channel@23 { |
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| 338 | + gw,mode = <1>; |
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| 339 | + reg = <0x23>; |
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| 340 | + label = "vdd_2p5"; |
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| 341 | + }; |
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| 342 | + }; |
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| 343 | + }; |
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| 344 | + |
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| 345 | + gsc_gpio: gpio@23 { |
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| 208 | 346 | compatible = "nxp,pca9555"; |
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| 209 | 347 | reg = <0x23>; |
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| 210 | 348 | gpio-controller; |
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| 211 | 349 | #gpio-cells = <2>; |
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| 350 | + interrupt-parent = <&gsc>; |
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| 351 | + interrupts = <4>; |
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| 212 | 352 | }; |
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| 213 | 353 | |
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| 214 | 354 | eeprom1: eeprom@50 { |
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| .. | .. |
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| 246 | 386 | pinctrl-names = "default"; |
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| 247 | 387 | pinctrl-0 = <&pinctrl_i2c2>; |
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| 248 | 388 | status = "okay"; |
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| 389 | + |
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| 390 | + magn@1c { |
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| 391 | + compatible = "st,lsm9ds1-magn"; |
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| 392 | + reg = <0x1c>; |
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| 393 | + pinctrl-names = "default"; |
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| 394 | + pinctrl-0 = <&pinctrl_mag>; |
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| 395 | + interrupt-parent = <&gpio5>; |
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| 396 | + interrupts = <17 IRQ_TYPE_EDGE_RISING>; |
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| 397 | + }; |
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| 249 | 398 | |
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| 250 | 399 | ltc3676: pmic@3c { |
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| 251 | 400 | compatible = "lltc,ltc3676"; |
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| .. | .. |
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| 319 | 468 | }; |
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| 320 | 469 | }; |
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| 321 | 470 | }; |
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| 471 | + |
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| 472 | + imu@6a { |
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| 473 | + compatible = "st,lsm9ds1-imu"; |
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| 474 | + reg = <0x6a>; |
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| 475 | + st,drdy-int-pin = <1>; |
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| 476 | + pinctrl-names = "default"; |
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| 477 | + pinctrl-0 = <&pinctrl_imu>; |
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| 478 | + interrupt-parent = <&gpio4>; |
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| 479 | + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; |
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| 480 | + }; |
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| 322 | 481 | }; |
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| 323 | 482 | |
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| 324 | 483 | &i2c3 { |
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| .. | .. |
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| 381 | 540 | }; |
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| 382 | 541 | |
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| 383 | 542 | &pwm4 { |
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| 543 | + #pwm-cells = <2>; |
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| 384 | 544 | pinctrl-names = "default"; |
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| 385 | 545 | pinctrl-0 = <&pinctrl_pwm4>; |
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| 386 | 546 | status = "okay"; |
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| .. | .. |
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| 483 | 643 | fsl,pins = < |
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| 484 | 644 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
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| 485 | 645 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
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| 646 | + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ |
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| 486 | 647 | >; |
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| 487 | 648 | }; |
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| 488 | 649 | |
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| .. | .. |
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| 500 | 661 | >; |
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| 501 | 662 | }; |
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| 502 | 663 | |
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| 664 | + pinctrl_imu: imugrp { |
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| 665 | + fsl,pins = < |
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| 666 | + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 |
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| 667 | + >; |
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| 668 | + }; |
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| 669 | + |
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| 670 | + pinctrl_mag: maggrp { |
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| 671 | + fsl,pins = < |
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| 672 | + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 |
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| 673 | + >; |
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| 674 | + }; |
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| 675 | + |
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| 503 | 676 | pinctrl_pcie: pciegrp { |
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| 504 | 677 | fsl,pins = < |
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| 505 | 678 | MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ |
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