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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> |
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| 3 | 4 | * Based on imx35-pinfunc.h in the same directory Which is: |
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| 4 | 5 | * Copyright 2013 Freescale Semiconductor, Inc. |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | | - * |
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| 10 | 6 | */ |
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| 11 | 7 | |
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| 12 | 8 | #ifndef __DTS_IMX25_PINFUNC_H |
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| .. | .. |
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| 86 | 82 | #define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 |
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| 87 | 83 | #define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 |
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| 88 | 84 | #define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 |
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| 85 | +#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000 |
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| 89 | 86 | |
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| 90 | 87 | #define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 |
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| 91 | 88 | #define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 |
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| 92 | 89 | #define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 |
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| 90 | +#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 |
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| 93 | 91 | |
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| 94 | 92 | #define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 |
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| 95 | 93 | #define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 |
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| .. | .. |
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| 106 | 104 | #define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 |
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| 107 | 105 | #define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 |
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| 108 | 106 | #define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 |
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| 107 | +#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000 |
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| 109 | 108 | |
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| 110 | 109 | #define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 |
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| 111 | 110 | #define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 |
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| 112 | 111 | #define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 |
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| 113 | 112 | #define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 |
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| 113 | +#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 |
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| 114 | 114 | |
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| 115 | 115 | #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 |
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| 116 | +#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 |
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| 116 | 117 | #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 |
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| 117 | 118 | |
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| 118 | 119 | #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 |
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| 119 | 120 | #define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 |
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| 120 | 121 | #define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 |
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| 122 | +#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000 |
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| 121 | 123 | |
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| 122 | 124 | #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 |
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| 123 | 125 | #define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 |
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| 124 | 126 | #define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 |
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| 127 | +#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 |
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| 125 | 128 | |
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| 126 | 129 | #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 |
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| 127 | 130 | #define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 |
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| .. | .. |
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| 255 | 258 | |
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| 256 | 259 | #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 |
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| 257 | 260 | #define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 |
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| 261 | +#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000 |
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| 258 | 262 | #define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 |
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| 259 | 263 | |
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| 260 | 264 | #define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 |
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| 261 | 265 | #define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 |
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| 266 | +#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000 |
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| 262 | 267 | #define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 |
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| 263 | 268 | |
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| 264 | 269 | #define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 |
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| .. | .. |
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| 283 | 288 | #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 |
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| 284 | 289 | |
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| 285 | 290 | #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 |
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| 286 | | -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 |
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| 291 | +#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 |
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| 292 | +#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 |
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| 287 | 293 | #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 |
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| 288 | 294 | #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 |
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| 289 | 295 | #define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 |
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| .. | .. |
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| 296 | 302 | #define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 |
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| 297 | 303 | #define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 |
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| 298 | 304 | #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 |
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| 299 | | -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 |
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| 305 | +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 |
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| 300 | 306 | |
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| 301 | 307 | #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 |
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| 302 | 308 | #define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 |
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| .. | .. |
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| 308 | 314 | #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 |
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| 309 | 315 | #define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 |
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| 310 | 316 | #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 |
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| 311 | | -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 |
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| 317 | +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 |
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| 312 | 318 | |
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| 313 | 319 | #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 |
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| 314 | 320 | #define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 |
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| 315 | 321 | #define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 |
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| 316 | 322 | #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 |
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| 317 | | -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 |
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| 323 | +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 |
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| 318 | 324 | |
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| 319 | 325 | #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 |
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| 320 | 326 | /* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ |
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| 321 | 327 | #define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 |
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| 322 | 328 | #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 |
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| 323 | 329 | #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 |
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| 330 | +#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 |
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| 324 | 331 | |
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| 325 | 332 | #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 |
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| 326 | 333 | #define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 |
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| 327 | 334 | #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 |
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| 335 | +#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 |
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| 328 | 336 | |
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| 329 | 337 | #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 |
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| 330 | 338 | #define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 |
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| .. | .. |
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| 396 | 404 | |
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| 397 | 405 | #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 |
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| 398 | 406 | #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 |
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| 399 | | -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 |
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| 407 | +#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 |
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| 400 | 408 | #define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 |
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| 401 | 409 | #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 |
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| 402 | 410 | |
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| .. | .. |
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| 413 | 421 | |
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| 414 | 422 | #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 |
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| 415 | 423 | #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 |
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| 416 | | -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 |
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| 424 | +#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 |
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| 417 | 425 | #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 |
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| 426 | +#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 |
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| 418 | 427 | |
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| 419 | 428 | #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 |
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| 420 | 429 | #define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 |
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| 421 | 430 | #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 |
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| 431 | +#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 |
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| 422 | 432 | |
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| 423 | 433 | /* |
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| 424 | 434 | * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD |
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| .. | .. |
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| 444 | 454 | #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 |
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| 445 | 455 | |
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| 446 | 456 | #define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 |
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| 457 | +#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 |
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| 447 | 458 | #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 |
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| 448 | 459 | #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 |
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| 449 | 460 | |
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| 450 | 461 | #define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 |
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| 462 | +#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 |
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| 451 | 463 | #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 |
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| 452 | 464 | #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 |
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| 453 | 465 | |
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| 454 | 466 | #define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 |
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| 467 | +#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 |
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| 455 | 468 | #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 |
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| 456 | 469 | #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 |
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| 457 | 470 | |
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| .. | .. |
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| 516 | 529 | |
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| 517 | 530 | #define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 |
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| 518 | 531 | #define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 |
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| 532 | +#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000 |
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| 519 | 533 | |
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| 520 | 534 | #define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 |
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| 521 | 535 | #define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 |
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| 536 | +#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000 |
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| 522 | 537 | |
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| 523 | 538 | #define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 |
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| 524 | 539 | /* |
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| .. | .. |
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| 560 | 575 | #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 |
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| 561 | 576 | #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 |
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| 562 | 577 | #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 |
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| 578 | +#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 |
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| 579 | +#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 |
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| 563 | 580 | #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 |
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| 581 | +#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 |
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| 564 | 582 | |
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| 565 | 583 | #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 |
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| 566 | 584 | #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 |
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| 567 | 585 | #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 |
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| 586 | +#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 |
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| 568 | 587 | |
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| 569 | 588 | #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 |
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| 570 | 589 | #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 |
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| .. | .. |
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| 589 | 608 | #define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 |
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| 590 | 609 | |
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| 591 | 610 | #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 |
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| 611 | +#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 |
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| 592 | 612 | #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 |
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| 593 | 613 | |
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| 594 | 614 | #define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 |
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