| .. | .. |
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| 33 | 33 | compatible = "samsung,odroid-xu3-audio"; |
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| 34 | 34 | model = "Odroid-XU4"; |
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| 35 | 35 | |
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| 36 | | - assigned-clocks = <&clock CLK_MOUT_EPLL>, |
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| 37 | | - <&clock CLK_MOUT_MAU_EPLL>, |
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| 38 | | - <&clock CLK_MOUT_USER_MAU_EPLL>, |
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| 39 | | - <&clock_audss EXYNOS_MOUT_AUDSS>, |
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| 40 | | - <&clock_audss EXYNOS_MOUT_I2S>, |
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| 41 | | - <&clock_audss EXYNOS_DOUT_SRP>, |
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| 42 | | - <&clock_audss EXYNOS_DOUT_AUD_BUS>, |
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| 43 | | - <&clock_audss EXYNOS_DOUT_I2S>; |
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| 44 | | - |
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| 45 | | - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, |
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| 46 | | - <&clock CLK_MOUT_EPLL>, |
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| 47 | | - <&clock CLK_MOUT_MAU_EPLL>, |
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| 48 | | - <&clock CLK_MAU_EPLL>, |
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| 49 | | - <&clock_audss EXYNOS_MOUT_AUDSS>; |
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| 50 | | - |
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| 51 | | - assigned-clock-rates = <0>, |
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| 52 | | - <0>, |
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| 53 | | - <0>, |
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| 54 | | - <0>, |
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| 55 | | - <0>, |
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| 56 | | - <196608001>, |
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| 57 | | - <(196608002 / 2)>, |
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| 58 | | - <196608000>; |
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| 36 | + samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; |
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| 59 | 37 | |
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| 60 | 38 | cpu { |
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| 61 | | - sound-dai = <&i2s0 0>; |
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| 39 | + sound-dai = <&i2s0 0>, <&i2s0 1>; |
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| 62 | 40 | }; |
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| 63 | 41 | |
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| 64 | 42 | codec { |
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| .. | .. |
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| 67 | 45 | }; |
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| 68 | 46 | }; |
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| 69 | 47 | |
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| 70 | | -&clock_audss { |
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| 71 | | - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, |
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| 72 | | - <&clock CLK_FOUT_EPLL>; |
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| 73 | | - assigned-clock-rates = <(196608000 / 256)>, |
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| 74 | | - <196608000>; |
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| 75 | | -}; |
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| 76 | | - |
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| 77 | 48 | &i2s0 { |
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| 78 | 49 | status = "okay"; |
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| 79 | | - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; |
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| 80 | | - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; |
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| 50 | + |
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| 51 | + assigned-clocks = <&clock CLK_MOUT_EPLL>, |
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| 52 | + <&clock CLK_MOUT_MAU_EPLL>, |
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| 53 | + <&clock CLK_MOUT_USER_MAU_EPLL>, |
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| 54 | + <&clock_audss EXYNOS_MOUT_AUDSS>, |
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| 55 | + <&clock_audss EXYNOS_MOUT_I2S>, |
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| 56 | + <&i2s0 CLK_I2S_RCLK_SRC>, |
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| 57 | + <&clock_audss EXYNOS_DOUT_SRP>, |
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| 58 | + <&clock_audss EXYNOS_DOUT_AUD_BUS>, |
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| 59 | + <&clock_audss EXYNOS_DOUT_I2S>; |
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| 60 | + |
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| 61 | + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, |
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| 62 | + <&clock CLK_MOUT_EPLL>, |
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| 63 | + <&clock CLK_MOUT_MAU_EPLL>, |
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| 64 | + <&clock CLK_MAU_EPLL>, |
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| 65 | + <&clock_audss EXYNOS_MOUT_AUDSS>, |
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| 66 | + <&clock_audss EXYNOS_SCLK_I2S>; |
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| 67 | + |
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| 68 | + assigned-clock-rates = <0>, |
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| 69 | + <0>, |
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| 70 | + <0>, |
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| 71 | + <0>, |
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| 72 | + <0>, |
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| 73 | + <0>, |
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| 74 | + <196608001>, |
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| 75 | + <(196608002 / 2)>, |
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| 76 | + <196608000>; |
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| 81 | 77 | }; |
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| 82 | 78 | |
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| 83 | 79 | &pwm { |
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