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2024-10-16 50a212ec906f7524620675f0c57357691c26c81f 
 kernel/arch/arm/boot/dts/exynos5420.dtsi
....@@ -1,12 +1,12 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * SAMSUNG EXYNOS5420 SoC device tree source
3
+ * Samsung Exynos5420 SoC device tree source
44  *
55  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
66  *		http://www.samsung.com
77  *
8
- * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
9
- * EXYNOS5420 based board files can include this file and provide
8
+ * Samsung Exynos5420 SoC device nodes are listed in this file.
9
+ * Exynos5420 based board files can include this file and provide
1010  * values for board specfic bindings.
1111  */
1212 
....@@ -42,117 +42,119 @@
4242 	 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
4343 	 */
4444 
45
+	cluster_a15_opp_table: opp_table0 {
46
+		compatible = "operating-points-v2";
47
+		opp-shared;
48
+
49
+		opp-1800000000 {
50
+			opp-hz = /bits/ 64 <1800000000>;
51
+			opp-microvolt = <1250000 1250000 1500000>;
52
+			clock-latency-ns = <140000>;
53
+		};
54
+		opp-1700000000 {
55
+			opp-hz = /bits/ 64 <1700000000>;
56
+			opp-microvolt = <1212500 1212500 1500000>;
57
+			clock-latency-ns = <140000>;
58
+		};
59
+		opp-1600000000 {
60
+			opp-hz = /bits/ 64 <1600000000>;
61
+			opp-microvolt = <1175000 1175000 1500000>;
62
+			clock-latency-ns = <140000>;
63
+		};
64
+		opp-1500000000 {
65
+			opp-hz = /bits/ 64 <1500000000>;
66
+			opp-microvolt = <1137500 1137500 1500000>;
67
+			clock-latency-ns = <140000>;
68
+		};
69
+		opp-1400000000 {
70
+			opp-hz = /bits/ 64 <1400000000>;
71
+			opp-microvolt = <1112500 1112500 1500000>;
72
+			clock-latency-ns = <140000>;
73
+		};
74
+		opp-1300000000 {
75
+			opp-hz = /bits/ 64 <1300000000>;
76
+			opp-microvolt = <1062500 1062500 1500000>;
77
+			clock-latency-ns = <140000>;
78
+		};
79
+		opp-1200000000 {
80
+			opp-hz = /bits/ 64 <1200000000>;
81
+			opp-microvolt = <1037500 1037500 1500000>;
82
+			clock-latency-ns = <140000>;
83
+		};
84
+		opp-1100000000 {
85
+			opp-hz = /bits/ 64 <1100000000>;
86
+			opp-microvolt = <1012500 1012500 1500000>;
87
+			clock-latency-ns = <140000>;
88
+		};
89
+		opp-1000000000 {
90
+			opp-hz = /bits/ 64 <1000000000>;
91
+			opp-microvolt = < 987500 987500 1500000>;
92
+			clock-latency-ns = <140000>;
93
+		};
94
+		opp-900000000 {
95
+			opp-hz = /bits/ 64 <900000000>;
96
+			opp-microvolt = < 962500 962500 1500000>;
97
+			clock-latency-ns = <140000>;
98
+		};
99
+		opp-800000000 {
100
+			opp-hz = /bits/ 64 <800000000>;
101
+			opp-microvolt = < 937500 937500 1500000>;
102
+			clock-latency-ns = <140000>;
103
+		};
104
+		opp-700000000 {
105
+			opp-hz = /bits/ 64 <700000000>;
106
+			opp-microvolt = < 912500 912500 1500000>;
107
+			clock-latency-ns = <140000>;
108
+		};
109
+	};
110
+
111
+	cluster_a7_opp_table: opp_table1 {
112
+		compatible = "operating-points-v2";
113
+		opp-shared;
114
+
115
+		opp-1300000000 {
116
+			opp-hz = /bits/ 64 <1300000000>;
117
+			opp-microvolt = <1275000>;
118
+			clock-latency-ns = <140000>;
119
+		};
120
+		opp-1200000000 {
121
+			opp-hz = /bits/ 64 <1200000000>;
122
+			opp-microvolt = <1212500>;
123
+			clock-latency-ns = <140000>;
124
+		};
125
+		opp-1100000000 {
126
+			opp-hz = /bits/ 64 <1100000000>;
127
+			opp-microvolt = <1162500>;
128
+			clock-latency-ns = <140000>;
129
+		};
130
+		opp-1000000000 {
131
+			opp-hz = /bits/ 64 <1000000000>;
132
+			opp-microvolt = <1112500>;
133
+			clock-latency-ns = <140000>;
134
+		};
135
+		opp-900000000 {
136
+			opp-hz = /bits/ 64 <900000000>;
137
+			opp-microvolt = <1062500>;
138
+			clock-latency-ns = <140000>;
139
+		};
140
+		opp-800000000 {
141
+			opp-hz = /bits/ 64 <800000000>;
142
+			opp-microvolt = <1025000>;
143
+			clock-latency-ns = <140000>;
144
+		};
145
+		opp-700000000 {
146
+			opp-hz = /bits/ 64 <700000000>;
147
+			opp-microvolt = <975000>;
148
+			clock-latency-ns = <140000>;
149
+		};
150
+		opp-600000000 {
151
+			opp-hz = /bits/ 64 <600000000>;
152
+			opp-microvolt = <937500>;
153
+			clock-latency-ns = <140000>;
154
+		};
155
+	};
156
+
45157 	soc: soc {
46
-		cluster_a15_opp_table: opp_table0 {
47
-			compatible = "operating-points-v2";
48
-			opp-shared;
49
-			opp-1800000000 {
50
-				opp-hz = /bits/ 64 <1800000000>;
51
-				opp-microvolt = <1250000>;
52
-				clock-latency-ns = <140000>;
53
-			};
54
-			opp-1700000000 {
55
-				opp-hz = /bits/ 64 <1700000000>;
56
-				opp-microvolt = <1212500>;
57
-				clock-latency-ns = <140000>;
58
-			};
59
-			opp-1600000000 {
60
-				opp-hz = /bits/ 64 <1600000000>;
61
-				opp-microvolt = <1175000>;
62
-				clock-latency-ns = <140000>;
63
-			};
64
-			opp-1500000000 {
65
-				opp-hz = /bits/ 64 <1500000000>;
66
-				opp-microvolt = <1137500>;
67
-				clock-latency-ns = <140000>;
68
-			};
69
-			opp-1400000000 {
70
-				opp-hz = /bits/ 64 <1400000000>;
71
-				opp-microvolt = <1112500>;
72
-				clock-latency-ns = <140000>;
73
-			};
74
-			opp-1300000000 {
75
-				opp-hz = /bits/ 64 <1300000000>;
76
-				opp-microvolt = <1062500>;
77
-				clock-latency-ns = <140000>;
78
-			};
79
-			opp-1200000000 {
80
-				opp-hz = /bits/ 64 <1200000000>;
81
-				opp-microvolt = <1037500>;
82
-				clock-latency-ns = <140000>;
83
-			};
84
-			opp-1100000000 {
85
-				opp-hz = /bits/ 64 <1100000000>;
86
-				opp-microvolt = <1012500>;
87
-				clock-latency-ns = <140000>;
88
-			};
89
-			opp-1000000000 {
90
-				opp-hz = /bits/ 64 <1000000000>;
91
-				opp-microvolt = < 987500>;
92
-				clock-latency-ns = <140000>;
93
-			};
94
-			opp-900000000 {
95
-				opp-hz = /bits/ 64 <900000000>;
96
-				opp-microvolt = < 962500>;
97
-				clock-latency-ns = <140000>;
98
-			};
99
-			opp-800000000 {
100
-				opp-hz = /bits/ 64 <800000000>;
101
-				opp-microvolt = < 937500>;
102
-				clock-latency-ns = <140000>;
103
-			};
104
-			opp-700000000 {
105
-				opp-hz = /bits/ 64 <700000000>;
106
-				opp-microvolt = < 912500>;
107
-				clock-latency-ns = <140000>;
108
-			};
109
-		};
110
-
111
-		cluster_a7_opp_table: opp_table1 {
112
-			compatible = "operating-points-v2";
113
-			opp-shared;
114
-			opp-1300000000 {
115
-				opp-hz = /bits/ 64 <1300000000>;
116
-				opp-microvolt = <1275000>;
117
-				clock-latency-ns = <140000>;
118
-			};
119
-			opp-1200000000 {
120
-				opp-hz = /bits/ 64 <1200000000>;
121
-				opp-microvolt = <1212500>;
122
-				clock-latency-ns = <140000>;
123
-			};
124
-			opp-1100000000 {
125
-				opp-hz = /bits/ 64 <1100000000>;
126
-				opp-microvolt = <1162500>;
127
-				clock-latency-ns = <140000>;
128
-			};
129
-			opp-1000000000 {
130
-				opp-hz = /bits/ 64 <1000000000>;
131
-				opp-microvolt = <1112500>;
132
-				clock-latency-ns = <140000>;
133
-			};
134
-			opp-900000000 {
135
-				opp-hz = /bits/ 64 <900000000>;
136
-				opp-microvolt = <1062500>;
137
-				clock-latency-ns = <140000>;
138
-			};
139
-			opp-800000000 {
140
-				opp-hz = /bits/ 64 <800000000>;
141
-				opp-microvolt = <1025000>;
142
-				clock-latency-ns = <140000>;
143
-			};
144
-			opp-700000000 {
145
-				opp-hz = /bits/ 64 <700000000>;
146
-				opp-microvolt = <975000>;
147
-				clock-latency-ns = <140000>;
148
-			};
149
-			opp-600000000 {
150
-				opp-hz = /bits/ 64 <600000000>;
151
-				opp-microvolt = <937500>;
152
-				clock-latency-ns = <140000>;
153
-			};
154
-		};
155
-
156158 		cci: cci@10d20000 {
157159 			compatible = "arm,cci-400";
158160 			#address-cells = <1>;
....@@ -173,7 +175,7 @@
173175 		};
174176 
175177 		clock: clock-controller@10010000 {
176
-			compatible = "samsung,exynos5420-clock";
178
+			compatible = "samsung,exynos5420-clock", "syscon";
177179 			reg = <0x10010000 0x30000>;
178180 			#clock-cells = <1>;
179181 		};
....@@ -235,6 +237,32 @@
235237 			status = "disabled";
236238 		};
237239 
240
+		dmc: memory-controller@10c20000 {
241
+			compatible = "samsung,exynos5422-dmc";
242
+			reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
243
+			interrupt-parent = <&combiner>;
244
+			interrupts = <16 0>, <16 1>;
245
+			interrupt-names = "drex_0", "drex_1";
246
+			clocks = <&clock CLK_FOUT_SPLL>,
247
+				 <&clock CLK_MOUT_SCLK_SPLL>,
248
+				 <&clock CLK_FF_DOUT_SPLL2>,
249
+				 <&clock CLK_FOUT_BPLL>,
250
+				 <&clock CLK_MOUT_BPLL>,
251
+				 <&clock CLK_SCLK_BPLL>,
252
+				 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
253
+				 <&clock CLK_MOUT_MCLK_CDREX>;
254
+			clock-names = "fout_spll",
255
+				      "mout_sclk_spll",
256
+				      "ff_dout_spll2",
257
+				      "fout_bpll",
258
+				      "mout_bpll",
259
+				      "sclk_bpll",
260
+				      "mout_mx_mspll_ccore",
261
+				      "mout_mclk_cdrex";
262
+			samsung,syscon-clk = <&clock>;
263
+			status = "disabled";
264
+		};
265
+
238266 		nocp_mem0_0: nocp@10ca1000 {
239267 			compatible = "samsung,exynos5420-nocp";
240268 			reg = <0x10CA1000 0x200>;
....@@ -271,6 +299,54 @@
271299 			status = "disabled";
272300 		};
273301 
302
+		ppmu_dmc0_0: ppmu@10d00000 {
303
+			compatible = "samsung,exynos-ppmu";
304
+			reg = <0x10d00000 0x2000>;
305
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
306
+			clock-names = "ppmu";
307
+			events {
308
+				ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
309
+					event-name = "ppmu-event3-dmc0_0";
310
+				};
311
+			};
312
+		};
313
+
314
+		ppmu_dmc0_1: ppmu@10d10000 {
315
+			compatible = "samsung,exynos-ppmu";
316
+			reg = <0x10d10000 0x2000>;
317
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
318
+			clock-names = "ppmu";
319
+			events {
320
+				ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
321
+					event-name = "ppmu-event3-dmc0_1";
322
+				};
323
+			};
324
+		};
325
+
326
+		ppmu_dmc1_0: ppmu@10d60000 {
327
+			compatible = "samsung,exynos-ppmu";
328
+			reg = <0x10d60000 0x2000>;
329
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
330
+			clock-names = "ppmu";
331
+			events {
332
+				ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
333
+					event-name = "ppmu-event3-dmc1_0";
334
+				};
335
+			};
336
+		};
337
+
338
+		ppmu_dmc1_1: ppmu@10d70000 {
339
+			compatible = "samsung,exynos-ppmu";
340
+			reg = <0x10d70000 0x2000>;
341
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
342
+			clock-names = "ppmu";
343
+			events {
344
+				ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
345
+					event-name = "ppmu-event3-dmc1_1";
346
+				};
347
+			};
348
+		};
349
+
274350 		gsc_pd: power-domain@10044000 {
275351 			compatible = "samsung,exynos4210-pd";
276352 			reg = <0x10044000 0x20>;
....@@ -292,11 +368,11 @@
292368 			label = "MFC";
293369 		};
294370 
295
-		msc_pd: power-domain@10044120 {
371
+		g3d_pd: power-domain@10044080 {
296372 			compatible = "samsung,exynos4210-pd";
297
-			reg = <0x10044120 0x20>;
373
+			reg = <0x10044080 0x20>;
298374 			#power-domain-cells = <0>;
299
-			label = "MSC";
375
+			label = "G3D";
300376 		};
301377 
302378 		disp_pd: power-domain@100440c0 {
....@@ -311,6 +387,13 @@
311387 			reg = <0x100440E0 0x20>;
312388 			#power-domain-cells = <0>;
313389 			label = "MAU";
390
+		};
391
+
392
+		msc_pd: power-domain@10044120 {
393
+			compatible = "samsung,exynos4210-pd";
394
+			reg = <0x10044120 0x20>;
395
+			#power-domain-cells = <0>;
396
+			label = "MSC";
314397 		};
315398 
316399 		pinctrl_0: pinctrl@13400000 {
....@@ -350,84 +433,76 @@
350433 			power-domains = <&mau_pd>;
351434 		};
352435 
353
-		amba {
354
-			#address-cells = <1>;
355
-			#size-cells = <1>;
356
-			compatible = "simple-bus";
357
-			interrupt-parent = <&gic>;
358
-			ranges;
436
+		adma: adma@3880000 {
437
+			compatible = "arm,pl330", "arm,primecell";
438
+			reg = <0x03880000 0x1000>;
439
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
440
+			clocks = <&clock_audss EXYNOS_ADMA>;
441
+			clock-names = "apb_pclk";
442
+			#dma-cells = <1>;
443
+			#dma-channels = <6>;
444
+			#dma-requests = <16>;
445
+			power-domains = <&mau_pd>;
446
+		};
359447 
360
-			adma: adma@3880000 {
361
-				compatible = "arm,pl330", "arm,primecell";
362
-				reg = <0x03880000 0x1000>;
363
-				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
364
-				clocks = <&clock_audss EXYNOS_ADMA>;
365
-				clock-names = "apb_pclk";
366
-				#dma-cells = <1>;
367
-				#dma-channels = <6>;
368
-				#dma-requests = <16>;
369
-				power-domains = <&mau_pd>;
370
-			};
448
+		pdma0: pdma@121a0000 {
449
+			compatible = "arm,pl330", "arm,primecell";
450
+			reg = <0x121A0000 0x1000>;
451
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
452
+			clocks = <&clock CLK_PDMA0>;
453
+			clock-names = "apb_pclk";
454
+			#dma-cells = <1>;
455
+			#dma-channels = <8>;
456
+			#dma-requests = <32>;
457
+		};
371458 
372
-			pdma0: pdma@121a0000 {
373
-				compatible = "arm,pl330", "arm,primecell";
374
-				reg = <0x121A0000 0x1000>;
375
-				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
376
-				clocks = <&clock CLK_PDMA0>;
377
-				clock-names = "apb_pclk";
378
-				#dma-cells = <1>;
379
-				#dma-channels = <8>;
380
-				#dma-requests = <32>;
381
-			};
459
+		pdma1: pdma@121b0000 {
460
+			compatible = "arm,pl330", "arm,primecell";
461
+			reg = <0x121B0000 0x1000>;
462
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
463
+			clocks = <&clock CLK_PDMA1>;
464
+			clock-names = "apb_pclk";
465
+			#dma-cells = <1>;
466
+			#dma-channels = <8>;
467
+			#dma-requests = <32>;
468
+		};
382469 
383
-			pdma1: pdma@121b0000 {
384
-				compatible = "arm,pl330", "arm,primecell";
385
-				reg = <0x121B0000 0x1000>;
386
-				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
387
-				clocks = <&clock CLK_PDMA1>;
388
-				clock-names = "apb_pclk";
389
-				#dma-cells = <1>;
390
-				#dma-channels = <8>;
391
-				#dma-requests = <32>;
392
-			};
470
+		mdma0: mdma@10800000 {
471
+			compatible = "arm,pl330", "arm,primecell";
472
+			reg = <0x10800000 0x1000>;
473
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
474
+			clocks = <&clock CLK_MDMA0>;
475
+			clock-names = "apb_pclk";
476
+			#dma-cells = <1>;
477
+			#dma-channels = <8>;
478
+			#dma-requests = <1>;
479
+		};
393480 
394
-			mdma0: mdma@10800000 {
395
-				compatible = "arm,pl330", "arm,primecell";
396
-				reg = <0x10800000 0x1000>;
397
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
398
-				clocks = <&clock CLK_MDMA0>;
399
-				clock-names = "apb_pclk";
400
-				#dma-cells = <1>;
401
-				#dma-channels = <8>;
402
-				#dma-requests = <1>;
403
-			};
404
-
405
-			mdma1: mdma@11c10000 {
406
-				compatible = "arm,pl330", "arm,primecell";
407
-				reg = <0x11C10000 0x1000>;
408
-				interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
409
-				clocks = <&clock CLK_MDMA1>;
410
-				clock-names = "apb_pclk";
411
-				#dma-cells = <1>;
412
-				#dma-channels = <8>;
413
-				#dma-requests = <1>;
414
-				/*
415
-				 * MDMA1 can support both secure and non-secure
416
-				 * AXI transactions. When this is enabled in
417
-				 * the kernel for boards that run in secure
418
-				 * mode, we are getting imprecise external
419
-				 * aborts causing the kernel to oops.
420
-				 */
421
-				status = "disabled";
422
-			};
481
+		mdma1: mdma@11c10000 {
482
+			compatible = "arm,pl330", "arm,primecell";
483
+			reg = <0x11C10000 0x1000>;
484
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
485
+			clocks = <&clock CLK_MDMA1>;
486
+			clock-names = "apb_pclk";
487
+			#dma-cells = <1>;
488
+			#dma-channels = <8>;
489
+			#dma-requests = <1>;
490
+			/*
491
+			 * MDMA1 can support both secure and non-secure
492
+			 * AXI transactions. When this is enabled in
493
+			 * the kernel for boards that run in secure
494
+			 * mode, we are getting imprecise external
495
+			 * aborts causing the kernel to oops.
496
+			 */
497
+			status = "disabled";
423498 		};
424499 
425500 		i2s0: i2s@3830000 {
426501 			compatible = "samsung,exynos5420-i2s";
427502 			reg = <0x03830000 0x100>;
428
-			dmas = <&adma 0
429
-				&adma 2
430
-				&adma 1>;
503
+			dmas = <&adma 0>,
504
+				<&adma 2>,
505
+				<&adma 1>;
431506 			dma-names = "tx", "rx", "tx-sec";
432507 			clocks = <&clock_audss EXYNOS_I2S_BUS>,
433508 				<&clock_audss EXYNOS_I2S_BUS>,
....@@ -446,8 +521,8 @@
446521 		i2s1: i2s@12d60000 {
447522 			compatible = "samsung,exynos5420-i2s";
448523 			reg = <0x12D60000 0x100>;
449
-			dmas = <&pdma1 12
450
-				&pdma1 11>;
524
+			dmas = <&pdma1 12>,
525
+				<&pdma1 11>;
451526 			dma-names = "tx", "rx";
452527 			clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
453528 			clock-names = "iis", "i2s_opclk0";
....@@ -462,8 +537,8 @@
462537 		i2s2: i2s@12d70000 {
463538 			compatible = "samsung,exynos5420-i2s";
464539 			reg = <0x12D70000 0x100>;
465
-			dmas = <&pdma0 12
466
-				&pdma0 11>;
540
+			dmas = <&pdma0 12>,
541
+				<&pdma0 11>;
467542 			dma-names = "tx", "rx";
468543 			clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
469544 			clock-names = "iis", "i2s_opclk0";
....@@ -530,7 +605,7 @@
530605 		};
531606 
532607 		mipi_phy: mipi-video-phy {
533
-			compatible = "samsung,s5pv210-mipi-video-phy";
608
+			compatible = "samsung,exynos5420-mipi-video-phy";
534609 			syscon = <&pmu_system_controller>;
535610 			#phy-cells = <1>;
536611 		};
....@@ -545,18 +620,6 @@
545620 			clock-names = "bus_clk", "pll_clk";
546621 			#address-cells = <1>;
547622 			#size-cells = <0>;
548
-			status = "disabled";
549
-		};
550
-
551
-		adc: adc@12d10000 {
552
-			compatible = "samsung,exynos-adc-v2";
553
-			reg = <0x12D10000 0x100>;
554
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
555
-			clocks = <&clock CLK_TSADC>;
556
-			clock-names = "adc";
557
-			#io-channel-cells = <1>;
558
-			io-channel-ranges;
559
-			samsung,syscon-phandle = <&pmu_system_controller>;
560623 			status = "disabled";
561624 		};
562625 
....@@ -671,6 +734,56 @@
671734 			clock-names = "gscl";
672735 			power-domains = <&gsc_pd>;
673736 			iommus = <&sysmmu_gscl1>;
737
+		};
738
+
739
+		gpu: gpu@11800000 {
740
+			compatible = "samsung,exynos5420-mali", "arm,mali-t628";
741
+			reg = <0x11800000 0x5000>;
742
+			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
743
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
744
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
745
+			interrupt-names = "job", "mmu", "gpu";
746
+
747
+			clocks = <&clock CLK_G3D>;
748
+			clock-names = "core";
749
+			power-domains = <&g3d_pd>;
750
+			operating-points-v2 = <&gpu_opp_table>;
751
+
752
+			status = "disabled";
753
+			#cooling-cells = <2>;
754
+
755
+			gpu_opp_table: opp-table {
756
+				compatible = "operating-points-v2";
757
+
758
+				opp-177000000 {
759
+					opp-hz = /bits/ 64 <177000000>;
760
+					opp-microvolt = <812500>;
761
+				};
762
+				opp-266000000 {
763
+					opp-hz = /bits/ 64 <266000000>;
764
+					opp-microvolt = <862500>;
765
+				};
766
+				opp-350000000 {
767
+					opp-hz = /bits/ 64 <350000000>;
768
+					opp-microvolt = <912500>;
769
+				};
770
+				opp-420000000 {
771
+					opp-hz = /bits/ 64 <420000000>;
772
+					opp-microvolt = <962500>;
773
+				};
774
+				opp-480000000 {
775
+					opp-hz = /bits/ 64 <480000000>;
776
+					opp-microvolt = <1000000>;
777
+				};
778
+				opp-543000000 {
779
+					opp-hz = /bits/ 64 <543000000>;
780
+					opp-microvolt = <1037500>;
781
+				};
782
+				opp-600000000 {
783
+					opp-hz = /bits/ 64 <600000000>;
784
+					opp-microvolt = <1150000>;
785
+				};
786
+			};
674787 		};
675788 
676789 		scaler_0: scaler@12800000 {
....@@ -971,7 +1084,6 @@
9711084 			compatible = "samsung,exynos-bus";
9721085 			clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
9731086 			clock-names = "bus";
974
-			operating-points-v2 = <&bus_wcore_opp_table>;
9751087 			status = "disabled";
9761088 		};
9771089 
....@@ -979,7 +1091,6 @@
9791091 			compatible = "samsung,exynos-bus";
9801092 			clocks = <&clock CLK_DOUT_ACLK100_NOC>;
9811093 			clock-names = "bus";
982
-			operating-points-v2 = <&bus_noc_opp_table>;
9831094 			status = "disabled";
9841095 		};
9851096 
....@@ -987,7 +1098,6 @@
9871098 			compatible = "samsung,exynos-bus";
9881099 			clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
9891100 			clock-names = "bus";
990
-			operating-points-v2 = <&bus_fsys_apb_opp_table>;
9911101 			status = "disabled";
9921102 		};
9931103 
....@@ -995,7 +1105,6 @@
9951105 			compatible = "samsung,exynos-bus";
9961106 			clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
9971107 			clock-names = "bus";
998
-			operating-points-v2 = <&bus_fsys_apb_opp_table>;
9991108 			status = "disabled";
10001109 		};
10011110 
....@@ -1003,7 +1112,6 @@
10031112 			compatible = "samsung,exynos-bus";
10041113 			clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
10051114 			clock-names = "bus";
1006
-			operating-points-v2 = <&bus_fsys2_opp_table>;
10071115 			status = "disabled";
10081116 		};
10091117 
....@@ -1011,7 +1119,6 @@
10111119 			compatible = "samsung,exynos-bus";
10121120 			clocks = <&clock CLK_DOUT_ACLK333>;
10131121 			clock-names = "bus";
1014
-			operating-points-v2 = <&bus_mfc_opp_table>;
10151122 			status = "disabled";
10161123 		};
10171124 
....@@ -1019,7 +1126,6 @@
10191126 			compatible = "samsung,exynos-bus";
10201127 			clocks = <&clock CLK_DOUT_ACLK266>;
10211128 			clock-names = "bus";
1022
-			operating-points-v2 = <&bus_gen_opp_table>;
10231129 			status = "disabled";
10241130 		};
10251131 
....@@ -1027,7 +1133,6 @@
10271133 			compatible = "samsung,exynos-bus";
10281134 			clocks = <&clock CLK_DOUT_ACLK66>;
10291135 			clock-names = "bus";
1030
-			operating-points-v2 = <&bus_peri_opp_table>;
10311136 			status = "disabled";
10321137 		};
10331138 
....@@ -1035,7 +1140,6 @@
10351140 			compatible = "samsung,exynos-bus";
10361141 			clocks = <&clock CLK_DOUT_ACLK333_G2D>;
10371142 			clock-names = "bus";
1038
-			operating-points-v2 = <&bus_g2d_opp_table>;
10391143 			status = "disabled";
10401144 		};
10411145 
....@@ -1043,7 +1147,6 @@
10431147 			compatible = "samsung,exynos-bus";
10441148 			clocks = <&clock CLK_DOUT_ACLK266_G2D>;
10451149 			clock-names = "bus";
1046
-			operating-points-v2 = <&bus_g2d_acp_opp_table>;
10471150 			status = "disabled";
10481151 		};
10491152 
....@@ -1051,7 +1154,6 @@
10511154 			compatible = "samsung,exynos-bus";
10521155 			clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
10531156 			clock-names = "bus";
1054
-			operating-points-v2 = <&bus_jpeg_opp_table>;
10551157 			status = "disabled";
10561158 		};
10571159 
....@@ -1059,7 +1161,6 @@
10591161 			compatible = "samsung,exynos-bus";
10601162 			clocks = <&clock CLK_DOUT_ACLK166>;
10611163 			clock-names = "bus";
1062
-			operating-points-v2 = <&bus_jpeg_apb_opp_table>;
10631164 			status = "disabled";
10641165 		};
10651166 
....@@ -1067,7 +1168,6 @@
10671168 			compatible = "samsung,exynos-bus";
10681169 			clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
10691170 			clock-names = "bus";
1070
-			operating-points-v2 = <&bus_disp1_fimd_opp_table>;
10711171 			status = "disabled";
10721172 		};
10731173 
....@@ -1075,7 +1175,6 @@
10751175 			compatible = "samsung,exynos-bus";
10761176 			clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
10771177 			clock-names = "bus";
1078
-			operating-points-v2 = <&bus_disp1_opp_table>;
10791178 			status = "disabled";
10801179 		};
10811180 
....@@ -1083,7 +1182,6 @@
10831182 			compatible = "samsung,exynos-bus";
10841183 			clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
10851184 			clock-names = "bus";
1086
-			operating-points-v2 = <&bus_gscl_opp_table>;
10871185 			status = "disabled";
10881186 		};
10891187 
....@@ -1091,251 +1189,7 @@
10911189 			compatible = "samsung,exynos-bus";
10921190 			clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
10931191 			clock-names = "bus";
1094
-			operating-points-v2 = <&bus_mscl_opp_table>;
10951192 			status = "disabled";
1096
-		};
1097
-
1098
-		bus_wcore_opp_table: opp_table2 {
1099
-			compatible = "operating-points-v2";
1100
-
1101
-			opp00 {
1102
-				opp-hz = /bits/ 64 <84000000>;
1103
-				opp-microvolt = <925000>;
1104
-			};
1105
-			opp01 {
1106
-				opp-hz = /bits/ 64 <111000000>;
1107
-				opp-microvolt = <950000>;
1108
-			};
1109
-			opp02 {
1110
-				opp-hz = /bits/ 64 <222000000>;
1111
-				opp-microvolt = <950000>;
1112
-			};
1113
-			opp03 {
1114
-				opp-hz = /bits/ 64 <333000000>;
1115
-				opp-microvolt = <950000>;
1116
-			};
1117
-			opp04 {
1118
-				opp-hz = /bits/ 64 <400000000>;
1119
-				opp-microvolt = <987500>;
1120
-			};
1121
-		};
1122
-
1123
-		bus_noc_opp_table: opp_table3 {
1124
-			compatible = "operating-points-v2";
1125
-
1126
-			opp00 {
1127
-				opp-hz = /bits/ 64 <67000000>;
1128
-			};
1129
-			opp01 {
1130
-				opp-hz = /bits/ 64 <75000000>;
1131
-			};
1132
-			opp02 {
1133
-				opp-hz = /bits/ 64 <86000000>;
1134
-			};
1135
-			opp03 {
1136
-				opp-hz = /bits/ 64 <100000000>;
1137
-			};
1138
-		};
1139
-
1140
-		bus_fsys_apb_opp_table: opp_table4 {
1141
-			compatible = "operating-points-v2";
1142
-			opp-shared;
1143
-
1144
-			opp00 {
1145
-				opp-hz = /bits/ 64 <100000000>;
1146
-			};
1147
-			opp01 {
1148
-				opp-hz = /bits/ 64 <200000000>;
1149
-			};
1150
-		};
1151
-
1152
-		bus_fsys2_opp_table: opp_table5 {
1153
-			compatible = "operating-points-v2";
1154
-
1155
-			opp00 {
1156
-				opp-hz = /bits/ 64 <75000000>;
1157
-			};
1158
-			opp01 {
1159
-				opp-hz = /bits/ 64 <100000000>;
1160
-			};
1161
-			opp02 {
1162
-				opp-hz = /bits/ 64 <150000000>;
1163
-			};
1164
-		};
1165
-
1166
-		bus_mfc_opp_table: opp_table6 {
1167
-			compatible = "operating-points-v2";
1168
-
1169
-			opp00 {
1170
-				opp-hz = /bits/ 64 <96000000>;
1171
-			};
1172
-			opp01 {
1173
-				opp-hz = /bits/ 64 <111000000>;
1174
-			};
1175
-			opp02 {
1176
-				opp-hz = /bits/ 64 <167000000>;
1177
-			};
1178
-			opp03 {
1179
-				opp-hz = /bits/ 64 <222000000>;
1180
-			};
1181
-			opp04 {
1182
-				opp-hz = /bits/ 64 <333000000>;
1183
-			};
1184
-		};
1185
-
1186
-		bus_gen_opp_table: opp_table7 {
1187
-			compatible = "operating-points-v2";
1188
-
1189
-			opp00 {
1190
-				opp-hz = /bits/ 64 <89000000>;
1191
-			};
1192
-			opp01 {
1193
-				opp-hz = /bits/ 64 <133000000>;
1194
-			};
1195
-			opp02 {
1196
-				opp-hz = /bits/ 64 <178000000>;
1197
-			};
1198
-			opp03 {
1199
-				opp-hz = /bits/ 64 <267000000>;
1200
-			};
1201
-		};
1202
-
1203
-		bus_peri_opp_table: opp_table8 {
1204
-			compatible = "operating-points-v2";
1205
-
1206
-			opp00 {
1207
-				opp-hz = /bits/ 64 <67000000>;
1208
-			};
1209
-		};
1210
-
1211
-		bus_g2d_opp_table: opp_table9 {
1212
-			compatible = "operating-points-v2";
1213
-
1214
-			opp00 {
1215
-				opp-hz = /bits/ 64 <84000000>;
1216
-			};
1217
-			opp01 {
1218
-				opp-hz = /bits/ 64 <167000000>;
1219
-			};
1220
-			opp02 {
1221
-				opp-hz = /bits/ 64 <222000000>;
1222
-			};
1223
-			opp03 {
1224
-				opp-hz = /bits/ 64 <300000000>;
1225
-			};
1226
-			opp04 {
1227
-				opp-hz = /bits/ 64 <333000000>;
1228
-			};
1229
-		};
1230
-
1231
-		bus_g2d_acp_opp_table: opp_table10 {
1232
-			compatible = "operating-points-v2";
1233
-
1234
-			opp00 {
1235
-				opp-hz = /bits/ 64 <67000000>;
1236
-			};
1237
-			opp01 {
1238
-				opp-hz = /bits/ 64 <133000000>;
1239
-			};
1240
-			opp02 {
1241
-				opp-hz = /bits/ 64 <178000000>;
1242
-			};
1243
-			opp03 {
1244
-				opp-hz = /bits/ 64 <267000000>;
1245
-			};
1246
-		};
1247
-
1248
-		bus_jpeg_opp_table: opp_table11 {
1249
-			compatible = "operating-points-v2";
1250
-
1251
-			opp00 {
1252
-				opp-hz = /bits/ 64 <75000000>;
1253
-			};
1254
-			opp01 {
1255
-				opp-hz = /bits/ 64 <150000000>;
1256
-			};
1257
-			opp02 {
1258
-				opp-hz = /bits/ 64 <200000000>;
1259
-			};
1260
-			opp03 {
1261
-				opp-hz = /bits/ 64 <300000000>;
1262
-			};
1263
-		};
1264
-
1265
-		bus_jpeg_apb_opp_table: opp_table12 {
1266
-			compatible = "operating-points-v2";
1267
-
1268
-			opp00 {
1269
-				opp-hz = /bits/ 64 <84000000>;
1270
-			};
1271
-			opp01 {
1272
-				opp-hz = /bits/ 64 <111000000>;
1273
-			};
1274
-			opp02 {
1275
-				opp-hz = /bits/ 64 <134000000>;
1276
-			};
1277
-			opp03 {
1278
-				opp-hz = /bits/ 64 <167000000>;
1279
-			};
1280
-		};
1281
-
1282
-		bus_disp1_fimd_opp_table: opp_table13 {
1283
-			compatible = "operating-points-v2";
1284
-
1285
-			opp00 {
1286
-				opp-hz = /bits/ 64 <120000000>;
1287
-			};
1288
-			opp01 {
1289
-				opp-hz = /bits/ 64 <200000000>;
1290
-			};
1291
-		};
1292
-
1293
-		bus_disp1_opp_table: opp_table14 {
1294
-			compatible = "operating-points-v2";
1295
-
1296
-			opp00 {
1297
-				opp-hz = /bits/ 64 <120000000>;
1298
-			};
1299
-			opp01 {
1300
-				opp-hz = /bits/ 64 <200000000>;
1301
-			};
1302
-			opp02 {
1303
-				opp-hz = /bits/ 64 <300000000>;
1304
-			};
1305
-		};
1306
-
1307
-		bus_gscl_opp_table: opp_table15 {
1308
-			compatible = "operating-points-v2";
1309
-
1310
-			opp00 {
1311
-				opp-hz = /bits/ 64 <150000000>;
1312
-			};
1313
-			opp01 {
1314
-				opp-hz = /bits/ 64 <200000000>;
1315
-			};
1316
-			opp02 {
1317
-				opp-hz = /bits/ 64 <300000000>;
1318
-			};
1319
-		};
1320
-
1321
-		bus_mscl_opp_table: opp_table16 {
1322
-			compatible = "operating-points-v2";
1323
-
1324
-			opp00 {
1325
-				opp-hz = /bits/ 64 <84000000>;
1326
-			};
1327
-			opp01 {
1328
-				opp-hz = /bits/ 64 <167000000>;
1329
-			};
1330
-			opp02 {
1331
-				opp-hz = /bits/ 64 <222000000>;
1332
-			};
1333
-			opp03 {
1334
-				opp-hz = /bits/ 64 <333000000>;
1335
-			};
1336
-			opp04 {
1337
-				opp-hz = /bits/ 64 <400000000>;
1338
-			};
13391193 		};
13401194 	};
13411195 
....@@ -1345,24 +1199,30 @@
13451199 			#include "exynos5420-trip-points.dtsi"
13461200 		};
13471201 		cpu1_thermal: cpu1-thermal {
1348
-		       thermal-sensors = <&tmu_cpu1>;
1349
-		       #include "exynos5420-trip-points.dtsi"
1202
+			thermal-sensors = <&tmu_cpu1>;
1203
+			#include "exynos5420-trip-points.dtsi"
13501204 		};
13511205 		cpu2_thermal: cpu2-thermal {
1352
-		       thermal-sensors = <&tmu_cpu2>;
1353
-		       #include "exynos5420-trip-points.dtsi"
1206
+			thermal-sensors = <&tmu_cpu2>;
1207
+			#include "exynos5420-trip-points.dtsi"
13541208 		};
13551209 		cpu3_thermal: cpu3-thermal {
1356
-		       thermal-sensors = <&tmu_cpu3>;
1357
-		       #include "exynos5420-trip-points.dtsi"
1210
+			thermal-sensors = <&tmu_cpu3>;
1211
+			#include "exynos5420-trip-points.dtsi"
13581212 		};
13591213 		gpu_thermal: gpu-thermal {
1360
-		       thermal-sensors = <&tmu_gpu>;
1361
-		       #include "exynos5420-trip-points.dtsi"
1214
+			thermal-sensors = <&tmu_gpu>;
1215
+			#include "exynos5420-trip-points.dtsi"
13621216 		};
13631217 	};
13641218 };
13651219 
1220
+&adc {
1221
+	clocks = <&clock CLK_TSADC>;
1222
+	clock-names = "adc";
1223
+	samsung,syscon-phandle = <&pmu_system_controller>;
1224
+};
1225
+
13661226 &dp {
13671227 	clocks = <&clock CLK_DP1>;
13681228 	clock-names = "dp";