修改GPIO导出默认初始值

hc

2024-10-16 50a212ec906f7524620675f0c57357691c26c81f

 kernel/arch/arm/boot/dts/exynos4412.dtsi
..
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@@ -45,7 +45,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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-		cpu@a01 {
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+		cpu1: cpu@a01 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA01>;
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@@ -55,7 +55,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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-		cpu@a02 {
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+		cpu2: cpu@a02 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA02>;
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@@ -65,7 +65,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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-		cpu@a03 {
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+		cpu3: cpu@a03 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA03>;
..
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@@ -76,7 +76,7 @@
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 		};
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 	};
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-	cpu0_opp_table: opp_table0 {
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+	cpu0_opp_table: opp-table0 {
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 		compatible = "operating-points-v2";
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 		opp-shared;
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..
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@@ -188,36 +188,38 @@
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 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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-		sysram@2020000 {
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+		sram@2020000 {
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 			compatible = "mmio-sram";
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 			reg = <0x02020000 0x40000>;
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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 			ranges = <0 0x02020000 0x40000>;
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-			smp-sysram@0 {
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+			smp-sram@0 {
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 				compatible = "samsung,exynos4210-sysram";
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 				reg = <0x0 0x1000>;
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 			};
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-			smp-sysram@2f000 {
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+			smp-sram@2f000 {
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 				compatible = "samsung,exynos4210-sysram-ns";
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 				reg = <0x2f000 0x1000>;
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 			};
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 		};
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-		pd_isp: isp-power-domain@10023ca0 {
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+		pd_isp: power-domain@10023ca0 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023CA0 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "ISP";
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 		};
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-		l2c: l2-cache-controller@10502000 {
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+		l2c: cache-controller@10502000 {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x10502000 0x1000>;
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 			cache-unified;
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 			cache-level = <2>;
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+			prefetch-data = <1>;
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+			prefetch-instr = <1>;
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 			arm,tag-latency = <2 2 1>;
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 			arm,data-latency = <3 2 1>;
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 			arm,double-linefill = <1>;
..
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@@ -243,25 +245,16 @@
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 			clock-names = "aclk200", "aclk400_mcuisp";
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 		};
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-		mct@10050000 {
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+		timer@10050000 {
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 			compatible = "samsung,exynos4412-mct";
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 			reg = <0x10050000 0x800>;
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-			interrupt-parent = <&mct_map>;
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-			interrupts = <0>, <1>, <2>, <3>, <4>;
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 			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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 			clock-names = "fin_pll", "mct";
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-
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-			mct_map: mct-map {
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-				#interrupt-cells = <1>;
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-				#address-cells = <0>;
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-				#size-cells = <0>;
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-				interrupt-map =
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-					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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-					<1 &combiner 12 5>,
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-					<2 &combiner 12 6>,
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-					<3 &combiner 12 7>,
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-					<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
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-			};
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+			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+					      <&combiner 12 5>,
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+					      <&combiner 12 6>,
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+					      <&combiner 12 7>,
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+					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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 		watchdog: watchdog@10060000 {
..
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@@ -274,7 +267,7 @@
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 		};
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 		adc: adc@126c0000 {
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-			compatible = "samsung,exynos-adc-v1";
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+			compatible = "samsung,exynos4212-adc";
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 			reg = <0x126C0000 0x100>;
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 			interrupt-parent = <&combiner>;
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 			interrupts = <10 3>;
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@@ -409,7 +402,7 @@
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 			status = "disabled";
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 		};
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-		bus_dmc_opp_table: opp_table1 {
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+		bus_dmc_opp_table: opp-table1 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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@@ -432,10 +425,11 @@
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 			opp-400000000 {
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 				opp-hz = /bits/ 64 <400000000>;
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 				opp-microvolt = <1050000>;
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+				opp-suspend;
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 			};
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 		};
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-		bus_acp_opp_table: opp_table2 {
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+		bus_acp_opp_table: opp-table2 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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..
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@@ -501,7 +495,7 @@
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 			status = "disabled";
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 		};
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-		bus_leftbus_opp_table: opp_table3 {
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+		bus_leftbus_opp_table: opp-table3 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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@@ -520,10 +514,11 @@
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 			opp-200000000 {
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 				opp-hz = /bits/ 64 <200000000>;
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 				opp-microvolt = <1000000>;
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+				opp-suspend;
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 			};
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 		};
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-		bus_display_opp_table: opp_table4 {
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+		bus_display_opp_table: opp-table4 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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..
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@@ -535,7 +530,7 @@
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 			};
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 		};
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-		bus_fsys_opp_table: opp_table5 {
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+		bus_fsys_opp_table: opp-table5 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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..
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@@ -547,7 +542,7 @@
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 			};
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 		};
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-		bus_peri_opp_table: opp_table6 {
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+		bus_peri_opp_table: opp-table6 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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..
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@@ -714,6 +709,53 @@
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 	cpu-offset = <0x4000>;
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 };
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+&gpu {
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+	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+	interrupt-names = "gp",
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+			  "gpmmu",
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+			  "pp0",
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+			  "ppmmu0",
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+			  "pp1",
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+			  "ppmmu1",
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+			  "pp2",
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+			  "ppmmu2",
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+			  "pp3",
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+			  "ppmmu3",
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+			  "pmu";
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+	operating-points-v2 = <&gpu_opp_table>;
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+
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+	gpu_opp_table: opp-table {
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+		compatible = "operating-points-v2";
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+
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+		opp-160000000 {
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+			opp-hz = /bits/ 64 <160000000>;
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+			opp-microvolt = <875000>;
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+		};
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+		opp-267000000 {
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+			opp-hz = /bits/ 64 <267000000>;
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+			opp-microvolt = <900000>;
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+		};
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+		opp-350000000 {
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+			opp-hz = /bits/ 64 <350000000>;
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+			opp-microvolt = <950000>;
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+		};
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+		opp-440000000 {
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+			opp-hz = /bits/ 64 <440000000>;
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+			opp-microvolt = <1025000>;
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+		};
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+	};
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+};
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+
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 &hdmi {
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 	compatible = "samsung,exynos4212-hdmi";
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 };
..
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@@ -735,6 +777,8 @@
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 &pmu {
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 	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
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+	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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+	status = "okay";
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 };
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 &pmu_system_controller {